Basic bistable element

• It is a circuit having two stable conditions

Chapter 6 (states).
• It can be used to store binary symbols.

Flip-Flops and Simple Flip-Flop

Applications

J. C. Huang, 2004 Digital Logic Design 1

Flip-flops Latches vs. flip-flops

A flip-flop is a bistable device, with inputs,
that remains in a given state as long as
power is applied and until input signals are
applied to cause its output to change.
• Latches are flip-flops for which the timing
of the output changes are not controlled.
• For a latch, the output essentially responds
immediately to changes on the input lines
(and possibly the presence of a clock pulse).
• A flip-flop is designed to change its output
at the edge of a controlling clock signal.

J. C. Huang, 2004 Digital Logic Design 2 J. C. Huang, 2004 Digital Logic Design 3

SR (Set-Reset) latch
Next state
• If Q denotes the present state of a memory
device, i.e., the state at the time the input
signals are applied, we shall use Q+ or
Q(t+1) to denote the next state, i.e., the new
state assumed by the device in response to
the input signals.

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1
 R’S’ latch Gated SR latch

J. C. Huang, 2004 Digital Logic Design 6 J. C. Huang, 2004 Digital Logic Design 7

Gated D latch
Timing considerations
• Propagation delays
• Minimum pulse width
• Setup and hold time

J. C. Huang, 2004 Digital Logic Design 8 J. C. Huang, 2004 Digital Logic Design 9

Propagation delay Minimum pulse width

The time it takes a change in the input The minimum amount of time a signal must
signal to produce a change in the output be applied in order to produce a desired
signal. result.

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2
 Setup and hold times JK- and T-type flip-flops
• To achieve a satisfactory operation of a In addition to the SR-type and D-type flip-
gated latch, constraints are normally placed flops discussed above, there are two other
on the time intervals between input changes. types, viz., JK- and T-type flip-flops.
• The minimum time the input signal must be
held fixed before and after the latching
action is called the setup time and hold
time, respectively.

J. C. Huang, 2004 Digital Logic Design 12 J. C. Huang, 2004 Digital Logic Design 13

J JK flip-flops
D Q Q
K Q Q
A JK flip-flop works just like an SR flip-
Clock flop if we consider J input as S(et) input and
(a) Circuit K input as R(eset) input, except when both
J K Q ( t + 1) S and R inputs are set to 1, the output
0 0 Q (t)
JK flip-flop 0 1 0
J Q
simply flips over.
1 0 1
K Q
1 1 Q (t )

(b) Truth table (c) Graphical symbol

J. C. Huang, 2004 Digital Logic Design 14 J. C. Huang, 2004 Digital Logic Design 15

T-type flip-flops Flip-flops

A T flip-flop is obtained from a JK flip-flop • There are four different types of flip-flops:
by tying the J and K inputs together to form SR, D, JK, and T types.
the T input. • The properties of these flip-flops are
summarized in the following 4 slides.
T J Q Q
• The function and application tables are also
C known as characteristic and excitation
K Q' Q'
tables, respectively.

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3
 SR-type flip-flop D-type flip-flop

S Q D Q
Q(t+1) = S + R'Q
C C Q(t+1) = D
R Q' SR = 0 Q'

Graphic symbol Characteristic equation Graphic symbol Characteristic equation

S R Q(t+1) Q Q(t+1) S R Q Q(t+1) D

0 0 Q 0 0 0 X D Q(t+1) 0 0 0
0 1 0 0 1 1 0 0 0 0 1 1
1 0 1 1 0 0 1 1 1 1 0 0
1 1 ? 1 1 X 0 1 1 1
Function table
Function table Application table Application table

J. C. Huang, 2004 Digital Logic Design 18 J. C. Huang, 2004 Digital Logic Design 19

JK-type flip-flop T-type flip-flop

J Q T Q
C C
Q'
Q(t+1) = JQ' + K'Q
Q'
Q(t+1) = TQ' + T'Q
K

Graphic symbol Characteristic equation Graphic symbol Characteristic equation

J K Q(t+1) Q Q(t+1) J K Q Q(t+1) T

T Q(t+1)
0 0 Q 0 0 0 X 0 0 0
0 Q 0 1 1
0 1 0 0 1 1 X
1 0 1 1 0 X 1 1 Q' 1 0 1
1 1 Q' 1 1 X 0 1 1 0
Function table
Function table Application table Application table
J. C. Huang, 2004 Digital Logic Design 20 J. C. Huang, 2004 Digital Logic Design 21

Positive and negative edge Edge-triggered flip-flops

• The transition of a control signal (clock • Edge triggered flip-flops use just one of the
pulse) from its low to high value (0 to 1) in edges of the clock pulse to affect the reading
positive logic is called the positive edge of of the input lines.
the control signal, while the transition from • These flip-flops are designed to be triggered
high to low (1 to 0) is called the negative by either the positive or negative edge.
edge. • In analyzing the behavior of an asynchronous
sequential circuit, one often needs to know
which edge trigger the flip-flops used.
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4
 D D Q Qa level sensitive latch Serial-in, serial-out unidirectional shift register
Clock Clk Q Qa

D Q Qb positive-edge-
Q Qb triggered

D Q Qc negative-edge-
Q Qc
triggered

(a) Circuit

Clock

Qa

Qb

Qc

(b) Timing diagram

J. C. Huang, 2004 Digital Logic Design 24 J. C. Huang, 2004 Digital Logic Design 25

Serial-in, parallel-out unidirectional shift register Parallel-in unidirectional shift register

J. C. Huang, 2004 Digital Logic Design 26 J. C. Huang, 2004 Digital Logic Design 27

Universal shift register

4-bit binary ripple

(asynchronous)
counter with
positive-edge triggered
flip-flops.

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5
A 3-bit Analysis method:
1 T Q T Q T Q
up-counter Q2 Q1 Q0
Clock Q Q Q Construct a list of state changes as follows.
0 0 0
Q0 Q1 Q2
1. Assume that the counter starts with 0 0 1
some values, say, 000. 0 1 0
(a) Circuit 2. Because T=1 for Q0, Q0 will change at 0 1 1
the arrival of every clock pulse. 1 0 0
Clock Complete the listing for Q0. 1 0 1
3. Because T=Q0’, and because the flip-flop 1 1 0
Q0
is triggered by a positive going clock 1 1 1
Q1
input, for Q1, Q1 changes its content 0 0 0
whenever Q0 changes from 1 to 0.
Q2 4. Do the same for the listing for Q2.

Count 0 1 2 3 4 5 6 7 0

(b) Timing diagram

The flip-flops are triggered by positive going edge of the clock input.
J. C. Huang, 2004 Digital Logic Design 30 J. C. Huang, 2004 Digital Logic Design 31

Analysis method:
1 T Q T Q T Q
Q2 Q1 Q0
Clock Q Q Q Construct a list of state changes as follows.
0 0 0
A 3-bit 1. Assume that the counter starts with 1 1 1
Q0 Q1 Q2
down-counter some values, say, 000. 1 1 0
(a) Circuit 2. Because T=1 for Q0, Q0 will change at 1 0 1
the arrival of every clock pulse. 1 0 0
Clock Complete the listing for Q0. 0 1 1
3. Because T=Q0, and because the flip-flop 0 1 0
Q0
is triggered by a positive going clock 0 0 1
input, for Q1, it changes its content 0 0 0
Q1
whenever Q0 changes from 0 to 1.
Q2 4. Do the same for the listing for Q2.

Count 0 7 6 5 4 3 2 1 0

(b) Timing diagram

The flip-flops are triggered by positive going edge of the clock input
J. C. Huang, 2004 Digital Logic Design 32 J. C. Huang, 2004 Digital Logic Design 33

Four-bit synchronous binary counter

The following synchronous counter can be analyzed similarly

Q0 Q1 Q2 Q2 Q1 Q0
0 0 0
1 T Q T Q T Q
0 0 1
Clock Q Q Q 0 1 0
1 1 1
0 0 0

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6
 Four-bit synchronous binary counter variation Four-bit synchronous binary counter with parallel load inputs

J. C. Huang, 2004 Digital Logic Design 36 J. C. Huang, 2004 Digital Logic Design 37

Synchronous mod-10 counter 8-bit synchronous binary counter constructed

from two 4-bit synchronous binary counters

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Mod-4 ring counter Mod-8 twisted-ring counter

(or Johnson counter)

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7
 Mod-7 twisted-ring counter

Control signal generators

• A control signal generator is a sequential
circuit that generate a sequence of bit
patterns, each of which contains only one 1.
It is used to activate various devices in turn.
• Shown in the next slide are the wave forms
of 4-bit control signals.

J. C. Huang, 2004 Digital Logic Design 42 J. C. Huang, 2004 Digital Logic Design 43

4-bit control pulses

Control-signal generator (continued)

CP

There are three ways to generate control signals

T0
(with n bits):
1. Use an n-bit ring counter (need n flip-flops)
T1 2. Use a binary counter and a decoder ( need k flip-flops and
n AND gates with k inputs, where n ≤ 2k)
T2
3. Use a Johnson counter (need n/2 flip-flops) and n 2-input
AND gates.
T3

J. C. Huang, 2004 Digital Logic Design 44 J. C. Huang, 2004 Digital Logic Design 45

T0 T1 T2 T3 Q0 Q1 Qn – 1

y0 y 1 y 2 y3

2-to-4 decoder
w1 w0 D Q D Q D Q
En

Q Q Q
1
Reset
Q1 Q0
Clock Clock
Up-counter
Clear Reset
An n-bit Johnson counter, augmented with 2n AND-gates, will generate
2n-bit control signals. It uses n/2 flip-flops, 2n 2-input, AND gates.
A part of the control circuit for the processor
Figure 7.30 Johnson counter
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8
 Counting sequence of a 3-bit Johnson counter
A'
T0
C'
A B C
A B C .
A
T1
0 0 0 B'

1 0 0
B
D Q D Q D Q T2
1 1 0 C'

Q Q Q 1 1 1 A
T3
0 1 1 C
Reset
Clock 0 0 1 A'
T4
C
0 0 0
B'
T5
Figure 7.30 A 3-bit Johnson counter A Johnson counter, augmented with a bank of C
AND gates, becomes a control-signal generator
J. C. Huang, 2004 Digital Logic Design 48 J. C. Huang, 2004 Digital Logic Design 49

Synchronous counters
A synchronous counter is a special kind of
synchronous sequential circuit, the analysis
and design of such a circuit will be
discussed in the next chapter.

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