UNIDADES TECNOLOGICAS DE SANTANDER

LABORATORIO DE ELECTRONICA DIGITAL II

IDENTIFICACION
Nombre de la practica: Fecha:
EDAPLAYGROUND 11/09/2021
Integrante: Grupo:
Guerreo Baez Yoyle Gissela E 152
Programa: Docente:
TECNOLOGIA EN IMPLEMENTACIÓN DE Cesar Hernando Valencia Niño
SISTEMAS ELECTRÓNICOS INDUSTRIALES

PROCEDIMIENTO
Diseñar y simular una compuerta AND, NOR, NAND, NOR, XOR, XNOR y NOT mediante VHDL
en EdaPlayground.
 F1SalidaAND
 F2 Salida OR.
 F3SalidaNAND
 F4 Salida NOR.
 F5SalidaXOR.
 F6 Salida XNOR.
 F7SalidaNOT.
Presentaren un único visorinteractivo las 7 respuestas.

Testbench.vhd Desing.vhd
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Simulacion is use IEEE.std_logic_unsigned.all;
--
end Simulacion; entity compuertas is
Port ( A : in STD_LOGIC;
architecture Behavioral of simulacion is B : in STD_LOGIC;
F : out STD_LOGIC;
component compuertas F1 : out STD_LOGIC;
Port ( A : in STD_LOGIC; F2 : out STD_LOGIC;
B : in STD_LOGIC; F3 : out STD_LOGIC;
F : out STD_LOGIC; F4 : out STD_LOGIC;
F1 : out STD_LOGIC; F5 : out STD_LOGIC;
F2 : out STD_LOGIC; F6 : out STD_LOGIC;
F3 : out STD_LOGIC; F7 : out STD_LOGIC
F4 : out STD_LOGIC; );
F5 : out STD_LOGIC;
F6 : out STD_LOGIC; end compuertas;
F7 : out STD_LOGIC
); architecture Behavioral of compuertas is
end component;
begin
--Señales de las entradas F <= A and B ;
signal A_s : STD_LOGIC:= '0'; F1 <= A or B ;
signal B_s : STD_LOGIC:= '0'; F2 <= A nand B ;
F3 <= A nor B ;
-- Señales de salida F4 <= A xor B ;
signal F_s : STD_LOGIC; F5 <= A xnor B ;
signal F1_s : STD_LOGIC; F6 <= not A ;
signal F2_s : STD_LOGIC; F7 <= not B ;
signal F3_s : STD_LOGIC;
signal F4_s : STD_LOGIC; end Behavioral;
signal F5_s : STD_LOGIC;
signal F6_s : STD_LOGIC;
signal F7_s : STD_LOGIC;

begin

UO: Compuertas Port map (

A => A_s,
B => B_s,
F => F_s,
F1 => F1_s,
F2 => F2_s,
F3 => F3_s,
F4 => F4_s,
F5 => F5_s,
F6 => F6_s,
F7 => F7_s
);

process begin

--- Estimulos de la simulacion wait for 100

ns;
wait for 100 ns;

A_s <= '0';

B_s <= '0';
wait for 100 ns;

A_s <= '1';

B_s <= '0';
wait for 100 ns;

A_s <= '0';

B_s <= '1';
wait for 100 ns;
A_s <= '1';
B_s <= '1';
wait for 100 ns;

A_s <= '0';

B_s <= '0';
wait for 100 ns;

wait;
end process;
end Behavioral;