Pstyro-Fpgasp3 User Manual

PSTYRO-FPGASP3
SPARTAN3 Starter Kit
Hardware & Software User Manual
1 www.pantechsolutions.net K-scheme VLSI Lab Manual

Contents
1. Introduction .................................................................................................................................... 3
1.1– Packages .................................................................................................................................. 3
1.2- Technical or Customer Support ................................................................................................. 3
2. Key Components and Features ........................................................................................................ 4
2.1 - General Block Diagram ............................................................................................................. 5
3. Jumper Details................................................................................................................................. 6
4. Connector Details ............................................................................................................................ 7
5. Power Supply .................................................................................................................................. 8
6. On-board Peripherals ...................................................................................................................... 9
6.1 - Light Emitting Diodes ............................................................................................................. 10
6.2 – Digital Inputs......................................................................................................................... 11
6.3 - RS-232 Communication(USART) ............................................................................................. 12
6.4 – JTAG Programmer ................................................................................................................. 13
6.5 – Clock Source ......................................................................................................................... 14
6.6 - VGA Interface ........................................................................................................................ 15
6.7 - PS/2 Interface ........................................................................................................................ 18
7. Board Layout ................................................................................................................................. 21
8. VLSI Lab Experiments ......................................................................................................................... 23
9 - Getting Started with Xilinx ISE ........................................................................................................... 93

1. Introduction
Thank you for purchasing the Xilinx Spartan-3 Evaluation Kit. You will find it useful in developing
your Spartan-3 FPGA application.
FPGASP3 Kit (STK) is an exclusive general-purpose kit for the SPARTAN family. The intention of
the design is to endorse the engineers and scholars to exercise and explore the capabilities of
FPGA architectures with many interfacing modules on board point LEDs, Slide switches, UART,
VGA, and PS/2 with ease to create a stand-alone versatile test platform.
1.1 – Packages
 Spartan3 Starter Kit (XC3S200)

 Serial Port Cable
 JTAG Programming Cable
 Printed User Manual
 CD contains
o Software (Programmers, ISE)
o Example Programs
o User Manual
1.2 - Technical or Customer Support
E-mail questions to : support@pantechsolutions.net
Send questions by mail to

Pantech Solutions Pvt Ltd.,
151/34, Mambalam High Road,
Sri Ranga Building, T. Nagar,
Chennai - 600 017
Tamilnadu, India
Phone : +91-44-4260 6470
Fax : +91-44-4260 6350
Website : www.pantechsolutions.net

2. Key Components and Features
 200,000-gate Xilinx Spartan 3 FPGA in a 144-TQFP (XC3S200-4TQG144C)

 4,320 logic cell equivalents
 Twelve 18K-bit block RAMs (216K bits)
 Twelve 18x18 hardware multipliers
 Four Digital Clock Managers (DCMs)
 Up to 97 user-defined I/O signals
 3-bit, 8-color VGA display port.
 RS-232 Serial Port.
 DB9 9-pin male connector with RS-232 transceiver/level translator
 Uses straight-through serial cable to connect PC or workstation serial port
 PS/2-connector( for mouse/keyboard interface) port
 8 Nos. Slide Switches for digital inputs
 8 nos. of Point LEDs for Digital outputs
 50 MHz crystal oscillator clock source
 3 Nos. 20-pin I/o connector for interface external peripherals modules
 40-pin Expansion connector for interface additional i/o modules
 JTAG port for download user program through cable
 9V AC/DC power input through adapter
 Power-on indicator LED
 On-board 5V, 3.3V, 2.5V, and 1.2V regulators.

2.1 - General Block Diagram
9V Input JTAG
+5V/3.3V/1.2V Port
USB UART
Power Supply Serial Comm
40Pin Expansion 3-bit 8-color

Connector
VGA Interface
PS/2 8 Nos. LED

Digital Outputs
XC3S200
3 Nos. 20-pin 8 Slide Switch
connector Digital Outputs

3. Jumper Details
Jumper and Main Switch Selection Details
3 2 1 PROM Execution
PROM
JTAG/
J3
3 2 1 JTAG Executions

4. Connector Details
40-Pin Expansion Connector

J5
IO123 1 2 IO124
IO125 3 4 IO128
IO129 5 6 IO130
IO131 7 8 IO132
IO135 9 10 IO137
IO140 11 12 IO141
IO1 13 14 IO2
IO4 15 16 IO5
17 18
+5V 19 20 +5V
GND 21 22 GND
3V3 23 24 3V3
IO6 25 26 IO7
IO11 27 28 IO12
IO13 29 30 IO14
IO15 31 32 IO17
IO18 33 34 IO20
IO21 35 36 IO23
IO24 37 38 IO25
IO26 39 40 IO27
EXTENSION CONN
20pin – Box Connector
J6 J7 J8
IO60 1 2 IO63 IO32 1 2 IO33 IO12 1 2 IO13

IO68 3 4 IO69 IO35 3 4 IO36 IO14 3 4 IO15
IO70 5 6 IO73 IO40 5 6 IO41 IO17 5 6 IO18
IO74 7 8 IO76 IO44 7 8 IO46 IO20 7 8 IO21
IO77 9 10 IO78 IO47 9 10 IO50 IO23 9 10 IO24
IO79 11 12 IO80 IO51 11 12 IO52 IO25 11 12 IO26
IO82 13 14 IO83 IO53 13 14 IO56 IO27 13 14 IO28
IO84 15 16 IO85 IO57 15 16 IO59 IO30 15 16 IO31
17 18 17 18 17 18
19 20 19 20 19 20
CONN TRBLK 8x2 CONN TRBLK 8x2 CONN TRBLK 8x2

+5V +5V +5V
JTAG Connector
J2
1 TMS
2 TDI
3 TDO
4 TCK
5 GND
6 VCC
CON6

5. Power Supply
The external power can be AC or DC, with a voltage between (9V, 1A output) at 230V AC input.
The SPARTAN3 board produces +5V using an LM7805 voltage regulator, which provides supply to
the peripherals.
USB socket meant for power supply and USB communication, user can select either USB or Ext
power supply through SW1. Separate On/Off Switch (SW1) for controlling power to the board.
ON/OFF Power +5V ON -External through Adaptor

SW1
Power +5V ON - Internal through USB
There are multiple voltages supplied on the Spartan-3 Evaluation Kit, 3.3V, 2.5V and 1.2V
regulators. Similarly, the 3.3V regulator feeds all the VCCO voltage supply inputs to the FPGA’s
I/O banks and powers most of the components on the board. The 2.5V regulator supplies power
to the FPGA’s VCCAUX supply inputs. The VCCAUX voltage input supplies power to Digital Clock
Managers (DCMs) within the FPGA and supplies some of the I/O structures.
In specific, all of the FPGA’s dedicated configuration pins, such as DONE, PROG_B, CCLK, and the
FPGA’s JTAG pins, are powered by VCCAUX. The FPGA configuration interface on the board is
powered by 3.3V. Consequently, the 2.5V supply has a current shunt resistor to prevent reverse
current. Finally, a 1.2V regulator supplies power to the FPGA’s VCCINT voltage inputs, which
power the FPGA’s core logic. The board uses four discrete regulators to generate the necessary
voltages.

6. On-board Peripherals
The Evaluation Kit comes with many interfacing options

 8-Nos. of Point LED’s (Digital Outputs)
 8-Nos. of Digital Inputs (Slide Switches)
 UART for serial port communication through PC
 JTAG Programmer
 Clock Source
 3-bit, 8 Color VGA Interface
 PS/2 Keyboard interface

6.1 - Light Emitting Diodes
 Light Emitting Diodes (LEDs) are the most commonly used components, usually for displaying
pin’s digital states.
 The FPGASP3 KIT has 8 nos., of Point LEDs, connected with port pins (details tabulated
below); the cathode of each LED connects to ground via a 220Ω resistor. To light an
individual LED, drive the associated FPGA control signal to High.
SPARTAN3
Point LEDs LED Selection
FPGA Lines
LED-D11 P97
LED-D10 P98 LED1

DIGITAL OUTPUTS
R1 330E
LED-D9 P99
LED-D8 P100
LED-D7 P102 Make Pin High – LED ON
LED-D6 P103 Make Pin Low – LED OFF
LED-D5 P104
LED-D4 P105

6.2 – Digital Inputs
 This is another simple interface, of 8-Nos. of slide switch, mainly used to give an input to the
port lines, and for some control applications also.
 The FPGASP3 KIT, slide switches (SW3-SW10) directly connected with FPGA I/O lines (details
tabulated below), user can give logical inputs high through slide switches.
The switches are connected to +3.3V, in order to detect a switch state, by default lines are pull-
downed through resistors. The switches typically exhibit about 2 ms of mechanical bounce and
there is no active de-bouncing circuitry, although such circuitry could easily be added to the FPGA
design programmed on the board. A 10KΩ series resistor provides nominal input protection.
Slide SPARTAN3
Slide Switch Logic
Switches FPGA Lines
SW3 P86
VCC
SW4 P87
R 10k
2 1
SW5 P89
DIGITAL INTPUTS
R SW1
10k
SW6 P90
SW7 P92
Make Switch Close – High
SW8 P93
Make Switch Open – Low
SW9 P95
SW10 P96

6.3 - RS-232 Communication(USART)
USART stands for Universal Synchronous Asynchronous Receiver Transmitter. FPGASP3 Kit provides
an RS232 port that can be driven by the Spartan-3 FPGA. A subset of the RS232 signals is used on the
Spartan 3 kit to implement this interface (RxD and TxD signals).
 RS-232 communication enables point-to-point data transfer. It is commonly used in data

acquisition applications, for the transfer of data between the microcontroller/FPGA and a PC.
 The voltage levels of a FPGA and PC are not directly compatible with those of RS-232, a level
transition buffer such as MAX3232 be used.
UART SPARTAN3
Serial Port Section
DB-9 Connector FPGA Lines
TXD P122
MAX
UART
SPARTAN3 3232
RXD P127

6.4 – JTAG Programmer
The FPGASP3 Kit includes a JTAG programming and debugging chain. Pantech JTAG3 low-cost
parallel to JTAG cable is included as part of the kit and connects to the JTAG header. DB-25
parallel port connector to 6 pin female header connector. The JTAG cable connect directly to the
parallel port of a PC and to a standard 6 pin JTAG programming header in the kit, can program a
devices that have a JTAG voltage of 1.8V or greater.
6-Pin SPARTAN3
JTAG Signals
Header FPGA Lines
JTAG Cable – III
1 TMS P111
2 TDI P144
Programmer
3 TDO P109
JTAG
4 TCK P110
5 GND
6 VCC
The Pantech low-cost parallel port to JTAG cable fits directly over the header stake pins, as
shown in above figure. When properly fitted, the cable is perpendicular to the board. Make sure
that the signals at the end of the JTAG cable align with the labels listed on the board. The other
end of the Pantech cable connects to the PC’s parallel port. The Pantech cable is directly
compatible with the Xilinx iMPACT software.

6.5 – Clock Source
The FPGASP3 Kit has a dedicated 50 MHz series clock oscillator source and an optional socket for
another clock oscillator source.
SPARTAN3
U10 Signal Crystal Oscillator
FPGA Lines
Oscillator
50MHz Clock P55

6.6 - VGA Interface
The FPGASP3 Kit includes a VGA display port through DB15 connector, Connect this port directly
to most PC monitors or flat-panel LCD displays using a standard monitor cable As shown in table,
the Spartan-3 FPGA controls five VGA signals: RED (R) its 1ST pin in connector, GREEN (G) its 2nd
pin, BLUE (B) its 3rd pin, Horizontal Sync (HS) 13th pin, and Vertical Sync (VS) its 14th pin, all
available on the VGA connector.
DB-15 SPARTAN3
VGA Signals
Connector FPGA Lines
Vertical Sync(VS) P12
Horizontal Sync(HS) P13
Blue P16
Green P18
Red P19
Each color line has a series resistor to provide 3-bit color, with one bit each for Red, Green, and
Blue. The series resistor uses the 75 ohm VGA cable termination to ensure that the color signals
remain in the VGA-specified 0V to 0.7V range. The HS and VS signals are TTL level. Drive the R, G,
and B signals High or Low to generate the eight possible colors shown in below table.
RED GREEN BLUE RESULTING COLOUR
0 0 0 BLACK
0 0 1 BLUE
0 1 0 GREEN
0 1 1 CYAN
1 0 0 RED
1 0 1 MAGNETA
1 1 0 YELLOW
1 1 1 WHITE
VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics
Standards Association (VESA). The following VGA system and timing information is provided as

an example of how the FPGA might drive VGA monitor in 640 by 480 modes. For more precise
information or for information on higher VGA frequencies, refer to documents available on the
VESA website or other electronics Websites: Video Electronics Standards Association
http://www.vesa.org
VGA Timing Information

http://www.epanorama.net/documents/pc/vga_timing.html
Signal Timing for a 60Hz, 640x480 VGA Display
CRT-based VGA displays use amplitude-modulated, moving electron beams (or cathode rays) to
display information on a phosphor-coated screen. LCD displays use an array of switches that can
impose a voltage across a small amount of liquid crystal, thereby changing light permittivity
through the crystal on a pixel by- pixel basis.
Although the following description is limited to CRT displays, LCD displays have evolved to use
the same signal timings as CRT displays. Consequently, the following discussion pertains to both
CRTs and LCD displays. Within a CRT display, current waveforms pass through the coils to
produce magnetic fields that deflect electron beams to transverse the display surface in a
“raster” pattern, horizontally from left to right and vertically from top to bottom.
As shown in below figure, information is only displayed when the beam is moving in the
“forward” direction—left to right and top to bottom—and not during the time the beam returns
back to the left or top edge of the display. Much of the potential display time is therefore lost in
“blanking” periods when the beam is reset and stabilized to begin a new horizontal or vertical
display pass.
The size of the beams, the frequency at which the beam traces across the display, and the
frequency at which the electron beam is modulated determine the display resolution. Modern
VGA displays support multiple display resolutions, and the VGA controller indicates the
resolution by producing timing signals to control the raster patterns. The controller produces
TTL-level synchronizing pulses that set the frequency at which current flows through the
deflection coils, and it ensures that pixel or video data is applied to the electron guns at the

correct time. Video data typically comes from a video refresh memory with one or more bytes
assigned to each pixel location.
The Spartan-3 Evaluation Kit uses three bits per pixel, producing one of the eight possible colors
shown in above table. The controller indexes into the video data buffer as the beams move
across the display. The controller then retrieves and applies video data to the display at precisely
the time the electron beam is moving across a given pixel.
The VGA controller generates the HS (horizontal sync) and VS (vertical sync) timings signals and
coordinates the delivery of video data on each pixel clock. The pixel clock defines the time
available to display one pixel of information. The VS signal defines the “refresh” frequency of the
display, or the frequency at which all information on the display is redrawn. The minimum
refresh frequency is a function of the display’s phosphor and electron beam intensity, with
practical refresh frequencies in the 60 Hz to 120 Hz range.
The number of horizontal lines displayed at a given refresh frequency defines the horizontal
“retrace” frequency.

6.7 - PS/2 Interface
The FPGASP3 Kit includes a PS/2 port and the standard 6-pin mini-DIN connector, labeled U11 on
the board. User can connect PS/2 Devices like keyboard, mouse to the FPGASP3 KIT. PS/2’s DATA
(P8) and CLK (P10) lines connected to SPARTAN3 FPGA I/O Lines.
6PIN MINI SPARTAN3

PS/2 PS/2 PORT SELECT
Connector FPGA Lines
U11 DATA P8 SPARTAN3
PS/2
CLK P10
Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a host
device, the Spartan-3 FPGA in this case. The PS/2 bus includes both clock and data. Both a mouse
and keyboard drive the bus with identical signal timings and both use 11-bit words that include a
start, stop and odd parity bit. However, the data packets are organized differently for a mouse
and keyboard. Furthermore, the keyboard interface allows bidirectional data transfers so the
host device can illuminate state LEDs on the Keyboard.
The PS/2 bus timing appears as shown in above figure. The clock and data signals are only driven
when data transfers occur; otherwise they are held in the idle state at logic High. The timing
defines signal requirements for mouse-to-host communications and bidirectional keyboard
communications. The attached keyboard or mouse writes a bit on the data line when the clock
signal is High, and the host reads the data line when the clock signal is Low.

Keyboard
The keyboard uses open-collector drivers so that either the keyboard or the host can drive the
two-wire bus. If the host never sends data to the keyboard, then the host can use simple input
pins. A ps/2-style keyboard uses scan codes to communicate key press data nearly all keyboards
in use today are ps/2 style. Each key has a single, unique scan code that is sent whenever the
corresponding key is pressed.
The scan codes for most keys appear in below figure. If the key is pressed and held, the keyboard
repeatedly sends the scan code every 100 ms or so. When a key is released, the keyboard sends
an “f0” key-up code, followed by the scan code of the released key. the keyboard sends the
same scan code, regardless if a key has different shift and non-shift characters and regardless
whether the shift key is pressed or not. The host determines which character is intended. Some
keys, called extended keys, send an “e0” ahead of the scan code and furthermore, they might
send more than one scan code. When an extended key is released, an “e0 f0” key-up code is
sent, followed by the scan code.
The host can also send commands and data to the keyboard. Below figure provides a short list of
some often-used

Commands
Command Description
ED Turn on/off Num Lock, Caps Lock, and Scroll Lock LEDs
EE Echo. Upon receiving an echo command, the keyboard replies with the same
scan code “EE”.
F3 Set scan code repeat rate. The keyboard acknowledges receipt of an “F3” by
returning an “FA”, after which the host sends a second byte to set the repeat
rate.
FE Resend. Upon receiving a resend command, the keyboard resends the last scan
code sent
FF Reset. Resets the keyboard
The keyboard sends commands or data to the host only when both the data and clock lines are
High, the Idle state, Because the host is the bus master, the keyboard checks whether the host is
sending data before driving the bus. The clock line can be used as a clear to send signal. If the
host pulls the clock line Low, the keyboard must not send any data until the clock is released.
The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by eight
bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit.

7. Board Layout

VLSI LAB Examples
(K-Scheme)

Contents
8. VLSI Lab Experiments

1. VHDL code and implement on FPGA kit
a. Addition
b. Subtraction
c. Multiplication
d. Division
2. VHDL code for
a. 8-bit Digital Output -LED Interface
b. 8-bit Digital Inputs (Switch Interface)
3. 4 × 4 Matrix Keypad Interface
4. VHDL code for
a. Relay Interface
b. Buzzer Interface
5. VHDL code for 7-Segment Display Interface
6. Stepper Motor Interface
7. Traffic Light Controller Interface
8. VHDL code to simulate 4-Bit Binary Counter by software
9. 2x16 character based LCD Interface
10. DC motor Control using PWM Generation
11. Design of MUX and DEMUX implement on FPGA kit
12. Design of Encoder / Decoder / Shift Register, implement on FPGA Kit

• Addition
• Subtraction
• Multiplication
• Division
• Hardware - FPGASP3 Kit
Description
Arithmetic operators can perform a variety of operations in VHDL such as addition, subtraction,
multiplication and division. VHDL arithmetic operators operate on numeric and physical operand
data types. The below table shows the VHDL arithmetic operators and data types required for
input as A ,B and output as Y.
Operator Description Input Data Type Output Data Type

+ Addition A numeric Numeric
A+B B numeric
- Subtraction A numeric Numeric
A–B B numeric
* Multiplication A integer or real Integer or Real
A* B B integer or real
* Multiplication A Physical Physical
A* B B integer or real
* Multiplication A integer or real Physical
A* B B Physical
/ Division A integer or real Integer or Real
A/B B integer or real
/ Division A Physical Physical
A/B B integer or real
/ Division A integer or real Physical
A/B B Physical
Connection Details
HW : FPGASP3 Kit ( CON - J6 ) - LED| Switch Card

CODE : PSTRYO-FPGASP3\Code\EXA-1\..............

1. A1 – Addition (Program for4-bit addition using arithmetic operator)
Consider the addition of two numbers of a + b, where a and b are 4 bit numbers and the output
of addition is taken in y as 8 bit number.
Output Y as 8
Input A as 4 Input B as 4 = bit
bit
+ bit
Flow Chart
START
Initialize
Entity
SET input A
SET input B
Verify output Y
END
Code Listing
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; -- Library declaration
use IEEE.STD_LOGIC_ARITH.ALL;
entity code is
Port (a : in STD_LOGIC_VECTOR (3 downto 0); -- input/output declaration

b : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC_VECTOR (7 downto 0));
end code;
architecture Behavioral of code is

begin
y <= a + b; -- This is a assignment statement
end Behavioral;

1. A2 - Program for Half Adder design using logical operator
A half adder ADD 2 input bits A , B and output the results as 2 bits - 1 bit for the Sum and
another 1 bit for the Carryout.
Flow Chart
Logical Diagram
START
Initialize
Entity
SET input A
Truth Table
SET input B
A B Sum Carryout
0 0 0 0
Verify Truth table 0 1 1 0
1 0 1 0
1 1 1 1
END
Code Listing
library IEEE; -- Library declaration
use IEEE.STD_LOGIC_1164.ALL;
entity halfadder is
Port ( a: in std_logic;
b: in std_logic; -- input / output declaration
Sum: out std_logic;
carryout: out std_logic);
end halfadder;
architecture behavior of halfadder is

begin
Sum <= a xor b; -- This is a signal assignment statement.
Carryout <= a and b; -- This is a signal assignment statement.
end HA_DtFl;

1. B – Subtraction (Program for 4-bit subtraction using arithmetic operator)
Consider the subtraction of two numbers of a - b, where a and b are 4 bit numbers and the
output of subtraction is taken in y as 4 bit number.
Input A as 4 Input B as 4 Output Y as 4 bit

- =
bit bit
Flow Chart
START
Initialize
Entity
SET input A
SET input B
Verify output Y
END
Code Listing
library IEEE;
entity code is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0); -- input / output declaration
end code;

begin
y <= a - b; -- This is a assignment statement.
end Behavioral;

1. C1 – Multiplication (Program for simple 2x2 multiplications using arithmetic operator)
Consider the multiplication of two numbers as 2 x2 a * b, where a and b are 4 bit numbers and
the output of multiplication is taken in y as 8 bit number.
Flow Chart
START
Initialize
Entity
SET input A
SET input B
Verify output Y
END
Code Listing
library IEEE;
entity code is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0); -- input / output declaration
end code;

begin
y <= a * b; -- This is a assignment statement
end Behavioral;

1. C2 – Multiplication (Program for 2 x 2 combinational array multiplications)
Consider the multiplication of two numbers as 2 x2 a * b, where a and b are 2 bit numbers and
the output of multiplication is taken in P as 4 bit number.
A (1) A (0)
B (1) B (0)
B (0) x A (1) B (0) x A (0)

B (1) x A (1) B (1) X A (0)
P (3) P (2) P (1) P (0)
P (0) = B (0) A (0)

P (1) = B (0) A (1) Plus B (1) A (0)
P (2) = B (1) A (1) Plus carryout of P (1)
P (3) = carryout of P (2)

Flow Chart
START
Initialize
Entity
SET input A
SET input B
Verify Truth table
END
Code Listing
library IEEE; -- Library declaration
entity mult_arry is
Port (a, b: in std_logic_vector (1 downto 0); -- input / output declaration
P: out std_logic_vector (3 downto 0));
end mult_arry;
architecture MULT_DF of mult_arry is

begin
-- For simplicity propagation delay times
-- are not considered in this example.
P (0) <= a(0) and b(0);
P (1) <= (a(0) and b(1)) xor (a(1) and b(0));
P (2) <= (a(1) and b(1)) xor ((a(0) and b(1)) and (a(1) and b (0)));
P (3) <= (a(1) and b(1)) and ((a(0) and b(1)) and (a(1) and b (0)));
end MULT_DF;

1. D1 – Division (Program to divide even numbers)
Consider the division of two numbers as a / b, where ‘a’ is 8 bit numbers and the output of
division is taken in Y as 8-bit number.
Flow Chart
START
Initialize
Entity
SET input A
Dividend
SET input B
Divisor
Verify Truth table
END
Code Listing
library IEEE;
entity code is
port ( a : in std_logic_vector(7 downto 0); --dividend
b : out std_logic_vector (7 downto 0));
end code;
begin
b <= CONV_STD_LOGIC_VECTOR((CONV_INTEGER(a)/4),8);
end Behavioral;

2. LED & Switch Interface Card
• Experiments Coverd
• 8-bit Digital Output -LED Interface
• 8-bit Digital Inputs (Switch Interface)
Hardware Description
 LED & Switch Card has 8 nos. of Point LEDs, are the most commonly used components, usually
for displaying Logical output of Device pin’s states.
 LED & Switch Card has 8 Nos. of Slide Switch, to give a digital input to the devices to evaluate the
pin states. LED Lines/Switch lines connected by 20pin box connector.
20PIN
MODULES LED & Switch Card Pin Details
CONNECTOR
1 SW1
VCC
2 SW2
R 10k
3 SW3
SLIDE SWITCH
2 1
SW1
4 SW4 R
10k
5 SW5
6 SW6 Make Switch Close – High
7 SW7 Make Switch Open – Low
8 SW8
9 LED1
10 LED2
LED1
R1 330E
11 LED2
12 LED2
LED
13 LED2 Make Pin High – LED ON

14 LED2 Make Pin Low – LED OFF
15 LED2
16 LED2
PWR 17,19 Vcc
Supply form FPGASP3 Kit
18,20 Gnd

2. a – 8-Bit Digital Output (Program to Blink 8 LEDs at Once)
Description
In this program to blink 8 Nos. of point LEDs at once in 250msec delay, Spartan3 FPGA
lines (P77 - P80 and P82 – P85) are configured has LED Outputs. User could verify the
result by using “LED & Switch Card” connected to the FPGASP3 Kit at connector J6
Flow Chart
START
Initialize
Entity
SET LED high
Delay for 250ms
SET LED low
Delay for 250ms
END

Code Listing
library IEEE;
entity code is
port ( clk : in std_logic; -- clock i/p
led : out std_logic_vector(7 downto 0)); -- 8-led o/p
end code;
begin
process(clk)
variable i,j : integer := 0;
begin
if clk'event and clk = '1' then
if i < 25000000 then --on delay logic
i := i + 1;
led(j) <= '1';
elsif i = 25000000 then
i := 0;
led(7 downto 0) <= "00000000";
if j < 7 then --checking for 8 display
j := j + 1;
elsif j = 7 then
j := 0;
end if;
end if;
end if;
end process;
end Behavioral;
RESULT
HW : FPGASP3 KIT ( CON ( J6 ) - LED | Switch Card
SW : PSTYRO-FPGASP3\Code\EXA-2a\..............

2. b 8-Bit Digital Input (Program to Read Switch Status and displayed in LEDs)
Description
In this program to give digital inputs from slide switches and switch status could be
viewed by point LEDs, In Spartan3 FPGA lines (P60, P63, P68, P69, P70, P73, P74, P76)
are configured has Digital Inputs and LEDs configured as (P77-P80 and P82-P85) outputs.
User could verify the result by using “LED & Switch Card” connected to the FPGASP3 Kit
at connector J6
Flow Chart
START
Initialize
Entity
SET Switch Close (ON)
Verify Switch status

In LED
END
Code Listing
library IEEE;
entity code is
port ( SW : in std_logic_vector(7 downto 0); ---data i/p
LED : out std_logic_vector(7 downto 0)); ---data o/p
end code;

begin
LED <= SW; ---data assignment
end Behavioral;
RESULT
HW : FPGASP3 KIT ( CON ( J6 ) - LED | Switch Card

SW : PSTYRO-FPGASP3\Code\EXA-2b\..............

3. 4x4 Matrix Keypad Card
• Key Press Displayed in LED
• Key Press Displayed in LCD
 Key arranged by matrix format, FOR each row and column section pulled by high, all row lines
(R1 – R4) and column lines (C1 – C4) connected directly by the 20pin box connector.
20PIN
MODULES 4X4 Matrix Keypad Card
CONNECTOR
1 R1
C2
C3
C4
C1
SW1 SW2 SW3 SW4

2 R2
R1
3 R3
SW5 SW6 SW7 SW8
SWITCHS
4 R4 R2
5 C1 SW9 SW10 SW11 SW12
6 C2 R3
SW13 SW14 SW15 SW16

7 C3
R4
8 C4
9-16 NC Pins 9-16 Not used
PWR 17,19 Vcc
18,20 Gnd

3.a 4 X 4 Matrix Keypad Card Interface (program to Scan Row & Column lines in 4 X 4 Matrix Keypad)
Description
In this example to scan Row and Column lines in 4 X 4 Matrix Keypad and view the result
in LED. In Spartan3 FPGA lines (P60, P63, P68 and 69) are configured for Horizontal
(ROW) lines. Pins (P70, 73, 74 and P76) are configured for Vertical (column) lines. User
could verify the result by “4 X 4 Matrix Keypad Interface Card” connected to the
FPGASP3 Kit at connector J6.
Flow Chart
Truth Table
START
4 x4 Matrix Row LEDs lines Column LEDs lines
Keypad D4 D5 D6 D7 D8 D9 D10 D11
Initialize Entity SW1 1 0 0 0 1 0 0 0
SW2 1 0 0 0 0 1 0 0
SW3 1 0 0 0 0 0 1 0
SW4 1 0 0 0 0 0 0 1
Send ROW lines = ‘1’ SW5 0 1 0 0 1 0 0 0
SW6 0 1 0 0 0 1 0 0
SW7 0 1 0 0 0 0 1 0
Scan Column lines with
respect to GND SW8 0 1 0 0 0 0 0 1
SW9 0 0 1 0 1 0 0 0
SW10 0 0 1 0 0 1 0 0
SET LED in on board high in SW11 0 0 1 0 0 0 1 0
Column & Row lines
SW12 0 0 1 0 0 0 0 1
SW13 0 0 0 1 1 0 0 0
END
SW14 0 0 0 1 0 1 0 0
SW15 0 0 0 1 0 0 1 0
SW16 0 0 0 1 0 0 0 1
Code Listing - Refer CD: \PSTYRO-FPGASP3\Code\EXA-3a \.....
RESULT
HW : FPGASP3 KIT ( CON ( J6 ) - 4x4 Keypad Interface Card


3. b - 4 X 4 Matrix Keypad Card Interface (Press 4 X 4 Matrix Keypad view result in 2 X16 LCD)
Description
In Spartan3 FPGA lines (P60, P63 and P68) - LCD control lines Pins (P77 to P80 and P82
to P85) LCD data lines. (P32, P33 P35 and P36) - Horizontal (ROW) lines. Pins (P40, P41,
P44 and P46) - Vertical (column) lines. User could verify the result by “4X4 Matrix
Keypad Interface Card” connected to the FPGASP3 Kit at connector J7 and “2X16 LCD
Interface Card” connected to the FPGASP3 Kit at connector J6.
Flow Chart
START
Initialize Entity
Send ROW lines = ‘1’
Scan Column lines with respect

to GND
SET LCD control line

RS = ‘0’
R/W = ‘0’
E =’1’
Send LCD display message

sequence with Row & Column
lines in keypad
(Ex. ROW: 1 COL: 1)
END
Code Listing: Refer CD: \PSTYRO-FPGASP3\Code\EXA-3b \.....

RESULT
HW : FPGASP3 KIT ( CON ( J7 ) - 4x4 Keypad Interface Card
( CON ( J6 ) - LCD Interface Card

4. Relay & Buzzer Interface Card
• Relay Interface
• Buzzer Interface
Relay & Buzzer Card , consists of 6 Nos. 5V SPDT Relay with output terminations, and 2 Nos. of
continuous buzzer connected to the 20pin box connector to study relay and buzzer modules.
ULN2803 is used as a driver for port I/O lines, drivers output connected to relay modules and
buzzers. Connector provided for external power supply if needed.
Relay / Buzzer Module : Make port pins high devices “relay/buzzer” activated.
20PIN
MODULES Relay & Buzzer Card
CONNECTOR
1 RELAY1
VCC
5
2 RELAY2 3
4
RELAYS
3 RELAY3 1 0
1
I/P - HIGH
2 RELAY
4 RELAY4
DRIVER
RELAY SPDT
5 RELAY5
LS1
1
6 RELAY6 I/P - HIGH 0 BUZZER
7 BUZZER1
BUZZER
Make Pins High – Relay/Buzzer ON
8 BUZZER2
9-16 NC Pins 9-16 Not used
17,19 Vcc
PWR Supply form FPGASP3 Kit
18,20 Gnd
Note: Separate switch provided to enable Buzzer ON/Off.

4. A - Relay (Toggle Relay On/Off with 1sec Delay)
Description
In this program to toggle relays On/Off continuously with 1 sec delay time. In Spartan3
FPGA lines (P60, P63, P68, P69, P70, and P73) are configured for relays. User could verify
the result by using “Relay & Buzzer Card” connected to the FPGASP3 KIT at connector
J6.
Flow Chart
START
Initialize Entity
IF relay R0-R5
>>1
Relay - ON
1sec Delay
Relay - OFF
1sec Delay
END

Code Listing
library IEEE;
use IEEE.STD_LOGIC_ARITH.ALL; --library declaration
entity first is
port ( clk : in std_logic;
relay : out std_logic_vector(5 downto 0) := "000000");
end first;
architecture Behavioral of first is

begin
process(clk)
variable i,j : integer := 0;
begin
if i < 50000000 then
i := i + 1;
i := 0 ;
if j < 5 then
j := j + 1;
elsif j = 5 then
j := 0;
end if;
end if;
if j = 0 then
relay <= "100000";
elsif j = 1 then
relay <= "010000";
elsif j = 2 then
relay <= "001000";
elsif j = 3 then
relay <= "000100";
elsif j = 4 then
relay <= "000010";
elsif j = 5 then
relay <= "000001";
end if;
end if;
end process;
end Behavioral;
Result
HW : FPGASP3 KIT  Relay & Buzzer card


4.b - Buzzer (To Generate Sound Continuously On/Off with 1sec Delay)
Description
In this program to generate sound signal continuously with delay of 1sec interval using
piezo-electric buzzer. In Spartan3 FPGA lines Buzzer1 (P74) and Buzzer2 (P76) are
configured for Buzzers. User could verify the result by using “Relay & Buzzer Card”
connected to the FPGASP3 KIT at connector J6.
Note: In Interfacing card separate switch provided to enable Buzzer On/Off.
Flow Chart
START
Initialize Entity
Buzzer 1 - ON
Buzzer 2 - OFF
Delay for 1sec
Buzzer 1 - OFF
Buzzer 2 - ON
Delay for 1sec
END

Code Listing
library IEEE;
use IEEE.STD_LOGIC_ARITH.ALL; --library declaration
entity first is
port ( clock : in std_logic;
buzzer1 : out std_logic; --i/o declaration
buzzer2 : out std_logic);
end first;

begin
process(clock)
variable i : integer := 0;
begin
if clock'event and clock = '1' then --delay statement
if i <= 50000000 then
i := i + 1;
buzzer1 <= '1'; --buzzer1 ON
buzzer2 <= '0';
elsif i > 50000000 and i < 100000000 then
i := i + 1;
buzzer1 <= '0';
buzzer2 <= '1'; --buzzer2 ON
i := 0;
end if;
end if;
end process;
end Behavioral;
Result
HW : FPGASP3 KIT  Relay & Buzzer card


5. 7-segment Display Card
• Simple Message Display("012345")
• Simple Counter Program(0 - 1000)
It has 6 nos. of common anode seven segment displays are used. The segment lines of seven
segments LED is being terminated at 20pin connector pin 9-to 16. The digit select lines are
connected to the 20pin box connector pin1- to pin6. All the common anode displays consume
very small amount of current.
20PIN
MODULES 7-Segment Display Card
CONNECTOR
1 Digit - 1
2 Digit – 2 VCC
Digit select lines
3 Digit – 3
1
1K
Digit - 1 2
4 Digit - 4
5 Digit – 5 3
6 Digit – 6 U1
3
seg-a 7
7 NC
CA
CA
Seg-b 6 A
Seg-c 4 B
8 NC seg-d 2 C
seg-e 1 D
9 Seg - a seg-f 9 E
seg-g 10 F
10 Seg – b seg--dp 5 G
DP
11 Seg – c
Segment Lines
7 SEG DISP
12 Seg – d
a
13 Seg – e
f g b Make high to - digit selection
14 Seg – f e d c Make low to - segment
15 Seg – g
16 Seg – dp
PWR 17,19 Vcc
18,20 Gnd

5.a – 7-segment Display (To Display Message “000000” to “ FFFFFF”)
Description
In this program to display simple message “000000” to”FFFFFF” the 7-seg display
module. In Spartan3 FPGA lines (P60, P63, P68, P69, P70, and P73) are configured for
digit selection lines. Pins (P77 - P80 and P82 – P85) are configured by data lines. User
could verify the result by “7-SEG Display Card” connected to the FPGASP3 KIT at
connector J6.
Flow Chart
START
Initialize Entity
Enable Digit Selection

(Digit1- Digit6)
Display Message
‘000000’ –‘FFFFFF’
END
Code Listing : Refer CD: \PSTYRO-FPGASP3\Code\EXA-5a \.....
Result
HW : FPGASP3 KIT CON(J6)  7-SEG Display Card


5.b – 7-segment Display (Simple Counter “0-1000”)
Description
In This example to display simple counter for “0- 1000” to the 7-seg display module. In
Spartan3 FPGA lines (P60, P63, P68, P69) are configured for (Digit-1 to Digit-4) selection
lines. Pins (P77 - P80 and P82 – P85) are configured by data lines. User could verify the
result by “7-SEG Display Card” connected to the FPGASP3 KIT at connector J6.
Flow Chart
START
Initialize Entity
Enable Digit Selection

(Digit1- Digit4)
Counter Display
(0-1000)
END
Code Listing : Refer CD: \PSTYRO-FPGASP3\Code\EXA-5b \.....
Result
HW : FPGASP3 KIT CON(J6)  7-SEG Display Card


6. DC Motor / Stepper Motor Card
• Stepper Motor Interface
• DC motor Speed Control using PWM
Stepper Motor
 Bipolar Stepper Motor driven by h-bridge driver, facility to connect external power supply to the
motor. 5V Stepper Motor speed, direction (clockwise/counterclockwise) and angle rotation
through user program.
DC Motor
 5V DC Motor speed has controlled through PWM signal. Motor can run both clockwise/counter
clockwise, Motor speed controlled by varying ENA (duty cycle) signal through program.
20PIN
MODULES Stepper Motor / DC motor Card
CONNECTOR
1 COIL-A VCC MOTOR_PWR
STEPPER
STEPPER MOTOR
2 COIL-B COIL-A 1
VS
VSS
COIL-B IN1 OUT1 2

3 COIL-C COIL-C IN2 OUT2 3 MG1
COIL-D IN3 OUT3
IN4 OUT4
4 COIL-D
4
6
EN1
EN2
5-8 NC
9 PWM1 VCC
10 PWM2
DC MOTOR
MOTOR SERVO
VS
VSS
11 ENA PWM1 1 2
A
+
PWM2 IN1 OUT1

IN2 OUT2
ENA MG2
EN1
12-16 NC
PWR 17,19 Vcc

18,20 Gnd

6. – Stepper Motor (To Rotate Motor Clockwise/Counter clockwise continuously)
Description
In this example to rotate stepper motor clockwise/counter clockwise continuously the
motor interface card. For that in Spartan3 FPGA lines (P60, P63, P68, P69) are configured
for (Coil-A to Coil-D). Separate switch provided for changing direction of the motor to
the FPGASP3 KIT board Switch SW0 (P86). User could verify the result by “Stepper/DC
motor Card” connected to the FPGASP3 KIT at connector J6.
Flow Chart
START
Initialize Entity
OFF
IF SW0?
ON
Send Data Sequence Send Data Sequence
with delay with delay
‘0001’ ‘1000’
‘0010’ ‘0100’
0100’ ‘0010’
‘1000’ ‘0001’
END

Code Listing
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity stepper is
port
(
Clk : in STD_LOGIC; -- clock I/P
CW_CCW : in STD_LOGIC; -- direction control
Rst : in STD_LOGIC; -- system reset
Step_En : in STD_LOGIC; -- step enable
FS_HS : in STD_LOGIC; -- Half step / Full step control
W1, W2, W3, W4 : out STD_LOGIC ); -- Winding o/ps
end stepper;
architecture behave of stepper is
signal div : std_logic_vector(16 downto 0); -- clock divider

signal clk_s : std_logic; -- divided clock signal
signal motor : std_logic_vector(3 downto 0);
signal Ps_state, Nx_state : state;
type state is(reset,first, second, third, fourth, half1,half2,half3,half4);
begin
------------------------------------------------------------------------
process (Clk,rst)
begin
if Rst='0' then --starting process
div <= (others=>'0');
elsif Clk'event and Clk='1' then
div <= div + 1;
end if;
end process;
------------------------------------------------------------------------
-- divided clock signal
-- change this value to control the speed of motor.
clk_s <= div(16);
------------------------------------------------------------------------
process (clk_s,rst)
begin
if Rst='0' then
Ps_state <= reset;
elsif clk_s'event and clk_s='1' then
if Step_en='1' then
Ps_state <= Nx_state;
end if;
end if;
end process;
------------------------------------------------------------------------
process (ps_state,CW_CCW,Step_en,rst,FS_HS)
begin
case(ps_state) is
when reset =>

Nx_state <= first;
when first =>
if FS_HS='0' then -- FS_HS='1' then HALF STEPs
if CW_CCW='1' then

Nx_state <= second; --assigning each step of motor rotation
else
Nx_state <= fourth;
end if;
else
if CW_CCW='1' then
Nx_state <= half1;
else
Nx_state <= half4;
end if;
end if;
when half1 =>

if CW_CCW='1' then
Nx_state <= second;
else
Nx_state <= first;
end if;
when second =>
if CW_CCW='1' then
Nx_state <= third;
else
Nx_state <= first;
end if;
else
if CW_CCW='1' then
Nx_state <= half2;
else
Nx_state <= half1;
end if;
end if;
when half2 =>
if CW_CCW='1' then
Nx_state <= third;
else
Nx_state <= second;
end if;
when third =>
if CW_CCW='1' then
Nx_state <= fourth;
else
Nx_state <= second;
end if;
else
if CW_CCW='1' then
Nx_state <= half3;
else
Nx_state <= half2;
end if;
end if;
when half3 =>
if CW_CCW='1' then
Nx_state <= fourth;
else
Nx_state <= third;
end if;
when fourth =>

if CW_CCW='1' then
Nx_state <= first;
else
Nx_state <= third;
end if;
else
if CW_CCW='1' then
Nx_state <= half4;
else
Nx_state <= half3;
end if;
end if;
when half4 =>
if CW_CCW='1' then
Nx_state <= first;
else
Nx_state <= fourth;
end if;
when others => Nx_state <= reset;
end case;
end process;
------------------------------------------------------------------------
W4 <= motor(3); -- Assigning O/Ps
W3 <= motor(2);
W2 <= motor(1);
W1 <= motor(0);
------------------------------------------------------------------------
process(ps_state)
begin
case ps_state is
when reset =>
Motor <= "0000"; --assigning motor control on/off
when first =>
Motor <= "1000";
when half1 =>
Motor <= "1100";
when second =>
Motor <= "0100";
when half2 =>
Motor <= "0110";
when third =>
Motor <= "0010";
when half3 =>
Motor <= "0011";
when fourth =>
Motor <= "0001";
when half4 =>
Motor <= "1001";
when others =>
Motor <= "0000";
end case;
end process;
end behave;
Result
HW : FPGASP3 KIT CON(J6)  DC Motor / Stepper Motor card

SW : PSTYRO-FPGASP3\Code\EXA-6\..............

7. Traffic Light Controller Card
• Simple 4 way traffic controller system
Traffic light controller card consist of 12 Nos. point led arranged by 4Lanes. Each lane has
Go(Green), Listen(Yellow) and Stop(Red) LED is being placed. Each LED has provided for current
limiting resistor to limit the current flows to the LEDs. LED1 to LED12 are terminated by the
20pin box header.
LAN 20PIN
MODULES Traffic Light Controller Card
Direction CONNECTOR
SOUTH 1 GO
330E
2 LISTEN GO
3 STOP LISTEN
330E
EAST 4 GO
330E
5 LISTEN STOP
6 STOP
NORTH 7 GO LANE
NORTH
8 LISTEN
9 STOP
LANE LANE
WEST 10 GO WEST EAST
11 LISTEN
12 STOP Make high to - LED On
Make low to – LED Off LANE
SOUTH
13-16 NC
PWR 17,19 Vcc
18,20 Gnd

7. – Traffic light controller (program to control 4 way traffic light module with sequence delay)
Description
In this example to control 4-way traffic light module with sequence delay. In Spartan3 FPGA lines
(P60, P63 and P68) are configured for (NORTH GO, LISTEN & STOP) lines. Pins (P69, P70 and P73)
are configured for (EAST GO, LISTEN & STOP) lines. Pins (P74, P76 and P77) are configured for
(SOUTH GO, LISTEN & STOP) lines. Pins (P78, P79 and P80) are configured for (WEST GO, LISTEN
& STOP) lines. Pins P86 are configured for control switches. User could verify the result by
“Traffic light controller cad” connected to the FPGASP3 KIT at connector J6.
Flow Chart
START
IF SWITCH?
ON
Send Data Sequence with delay
NORTH GO
SOUTH STOP
EAST STOP
WEST STOP

EAST GO
NORTH STOP
SOUTH STOP
WEST STOP

SOUTH GO
EAST STOP
NORTHSTOP
WEST STOP

WEST GO
SOUTH STOP
EAST STOP
NORTH STOP

Code Listing :
library IEEE;
use IEEE.STD_LOGIC_ARITH.ALL; -------- Library declaration
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity first is
rst : in std_logic;
northgreen : out std_logic;
northred : out std_logic;
northyel : out std_logic;
southgreen : out std_logic;
southred : out std_logic;
southyel : out std_logic; --------- I / O declaration
eastgreen : out std_logic;
eastred : out std_logic;
eastyel : out std_logic;
westred : out std_logic;
westgreen : out std_logic;
westyel : out std_logic);
end first;
type contol is (north,south,east,west);

signal control,control1 : contol := north;
begin
process(clk,rst)
begin
if rst = '1' then
if i < 1500000000 then
i := i + 1;
Control <= control1;
i := 0;
end if;
if control = north then ------- North direction selection
if i >= 0 and i <= 750000000 then
northgreen <= '0';

northred <= '1';
northyel <= '1';
southgreen <= '1';
southred <= '0';
southyel <= '1';
eastgreen <= '1';
eastred <= '0';
eastyel <= '1';
westred <= '0';
westgreen <= '1';
westyel <= '1';

elsif i > 750000000 and i <= 1000000000 then
northgreen <= '1';
northred <= '1';
northyel <= '0';
southgreen <= '1';
southred <= '0';
southyel <= '1';
eastgreen <= '1';
eastred <= '1';
eastyel <= '0';
westred <= '0';
westgreen <= '1';
westyel <= '1';
elsif i > 1000000000 and i < 1500000000 then
northgreen <= '1';
northred <= '0';
northyel <= '1';
southgreen <= '1';
southred <= '0';
southyel <= '1';
eastgreen <= '0';
eastred <= '1';
eastyel <= '1';
westred <= '0';
westgreen <= '1';
westyel <= '1';
control1 <= east;
end if;
elsif control = east then ---- EAST direction selection
if i >= 0 and i <= 750000000 then
northgreen <= '1';
northred <= '0';
northyel <= '1';
southgreen <= '1';
southred <= '0';
southyel <= '1';
eastgreen <= '0';
eastred <= '1';
eastyel <= '1';
westred <= '0';
westgreen <= '1';
westyel <= '1';
elsif i > 750000000 and i <= 1000000000 then
northgreen <= '1';
northred <= '0';
northyel <= '1';
southgreen <= '1';
southred <= '1';
southyel <= '0';
eastgreen <= '1';
eastred <= '1';
eastyel <= '0';
westred <= '0';
westgreen <= '1';
westyel <= '1';

elsif i > 1000000000 and i < 1500000000 then
northgreen <= '1';
northred <= '0';
northyel <= '1';
southgreen <= '0';
southred <= '1';
southyel <= '1';
eastgreen <= '1';
eastred <= '0';
eastyel <= '1';
westred <= '0';
westgreen <= '1';
westyel <= '1';
control1 <= south;

end if;
elsif control = south then ---------South direction
if i >= 0 and i <= 750000000 then
northgreen <= '1';

northred <= '0';
northyel <= '1';
southgreen <= '0';
southred <= '1';
southyel <= '1';
eastgreen <= '1';
eastred <= '0';
eastyel <= '1';
westred <= '0';
westgreen <= '1';
westyel <= '1';
elsif i > 750000000 and i <= 1000000000 then
northgreen <= '1';
northred <= '0';
northyel <= '1';
southgreen <= '1';
southred <= '1';
southyel <= '0';
eastgreen <= '1';
eastred <= '0';
eastyel <= '1';
westred <= '1';
westgreen <= '1';
westyel <= '0';
elsif i > 1000000000 and i < 1500000000 then
northgreen <= '1';
northred <= '0';
northyel <= '1';
southgreen <= '1';
southred <= '0';
southyel <= '1';
eastgreen <= '1';
eastred <= '0';
eastyel <= '1';
westred <= '1';
westgreen <= '0';
westyel <= '1';

control1 <= west;
end if;
elsif control = west then ----- WEST direction
if i >= 0 and i <= 750000000 then

northgreen <= '1';
northred <= '0';
northyel <= '1';
southgreen <= '1';
southred <= '0';
southyel <= '1';
eastgreen <= '1';
eastred <= '0';
eastyel <= '1';
westred <= '1';
westgreen <= '0';
westyel <= '1';
elsif i > 750000000 and i <= 1000000000 then
northgreen <= '1';
northred <= '1';
northyel <= '0';
southgreen <= '1';
southred <= '0';
southyel <= '1';
eastgreen <= '1';
eastred <= '0';
eastyel <= '1';
westred <= '1';
westgreen <= '1';
westyel <= '0';
elsif i > 1000000000 and i < 1500000000 then
northgreen <= '0';
northred <= '1';
northyel <= '1';
southgreen <= '1';
southred <= '0';
southyel <= '1';
eastgreen <= '1';
eastred <= '0';
eastyel <= '1';
westred <= '0';
westgreen <= '1';
westyel <= '1';
control1 <= north;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
Result
HW : FPGASP3 KIT CON ( J6 )  Traffic Light Controller Card

8. VHDL code to simulate 4-bit Binary Counter by Software
• Up Counter
• Down Counter
• Up/Down Counter
• Software - Xilinx ISE 9.2
VHDL code to simulate 4-Bit Binary Counter by software
COUNTERS
A counter is a device which stores the number of times a particular event or process has occurred,
often in relationship to a clock signal. There are two types of counters:
 up counters
 down counters
Up counters
Each of the higher-order flip-flops are made ready to toggle (both J and K inputs "high") if the Q
outputs of all previous flip-flops are "high." Otherwise, the J and K inputs for that flip-flop will
both be "low," placing it into the "latch" mode where it will maintain its present output state at
the next clock pulse. Since the first (LSB) flip-flop needs to toggle at every clock pulse, its J and K
inputs are connected to Vcc or Vdd, where they will be "high" all the time.

8.a. Up Counter (Program for 4-bit binary counter using behavior description)
Description
In this program an up counter has a 1- bit input and a 4- bit output. Additional control signals
may be added such as enable. The output of the multiplexers depends on the level of the select
line.
Flow Chart
START
Initialize Entity
IF CLR=1
ON
Enable Clock
Counter
Value Increase from
(0 to 15)
END

Code Listing
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(Clock, CLR : in std_logic;
Q : out std_logic_vector(3 downto 0));
end counter;
architecture archi of counter is
signal tmp: std_logic_vector(3 downto 0);
begin
process (Clock, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (Clock'event and Clock='1') then
tmp <= tmp + 1;
end if;
end process;
Q <= tmp;
end archi;
 Result

8-b. . Down Counter (Program for 4-bit binary counter using behavior description)
Description
In this program a down counter has a 1- bit input and a 4- bit output. Additional control signals
may be added such as enable. The output of the multiplexers depends on the level of the select
line.
Flow Chart
START
Initialize Entity
IF CLR=1
ON
Enable Clock
Counter
Value
Decreases from (15 to 0)
END

Code Listing
library ieee;
entity counter is
port(Clock, CLR : in std_logic;
end counter;

begin
process (Clock, CLR)

begin
if (CLR='1') then
tmp <= "1111";
elsif (Clock'event and Clock='1') then
tmp <= tmp - 1;
end if;
end process;
Q <= tmp;
end archi;
 Result

8.c - . Up/Down Counter (Program for 4-bit binary counter using behavior description)
Description
The Up/Down control input line simply enables either the upper string or lower string of AND
gates to pass the Q/Q' outputs to the succeeding stages of flip-flops. If the Up/Down control line
is "high," the top AND gates become enabled. If the Up/Down control line is made "low," the
bottom AND gates become enabled.
Flow Chart
START
Initialize Entity
NO
IF CLR=1
YES
Counter Counter
Value Value
Increases Decreases
from (0 to 15) From (15 to 0)
END

Code Listing
library ieee;
entity counter is
port(C, CLR, up_down : in std_logic;
end counter;

begin
process (C, CLR)
begin
if (CLR='1') then
tmp <= "0000";
elsif (C'event and C='1') then
if (up_down='1') then
tmp <= tmp + 1;
else
tmp <= tmp - 1;

end if;
end if;
end process;
Q <= tmp;
end archi;
Result
SW : PSTYRO-FPGASP3\Code\EXA-8c\..............

9. 2x16 Character LCD Interface Card
• Display Message "PANTECH SOLUTIONS" - 1st Line
• Display Message " PANTECH SOLUTIONS " - 2nd Line
The 2x16 character LCD interface card with supports both modes 4-bit and 8-bit interface, and
also facility to adjust contrast through trim pot. In 8-bit interface 11 lines needed to create 8-bit
interface; 8 data bits (D0 – D7), three control lines, address bit (RS), read/write bit (R/W) and
control signal (E). The LCD controller is a standard KS0070B or equivalent, which is a very well-
known interface for smaller character based LCDs.
 LCD’s Control Lines and Data lines are terminated with 20pin box connector.
20PIN
LCD
CONNECT LED & Switch Card Pin Details
MODULES
OR
1 RS
CONTROL
2 RW
LINES
3 E
4-8 NC
9 D0
+LED-
GND
VCC
LED
R/W
VEE
RS
D0
D1
D2
D3
D4
D5
D6
D7
E
10 D1
LCD – DATA LINES
11 D2
12 D3
13 D4
14 D5
15 D6
16 D7
PWR 17,19 Vcc
18,20 Gnd

9. 2 X 16 LCD interface (program to display message “PANTECH SOLUTIONS “ in 2 x 16 LCD)
Description
In this example to display message “PANTECH SOLUTIONS” in 2 X 16 LCD first line. In Spartan3
FPGA lines (P60, P63 and P68) are configured for LCD control lines like (RS, RW & E). Pins (P77 to
P80 and P82 to P85) are configured for LCD data lines. User could verify the result by “2 X 16 LCD
Interface Card” connected to the FPGASP3 KIT at connector J6. User can modify the LCD display
message by changing the data in VHDL code.
Flow Chart
START
Initialize Entity
Set LCD control line

RS = ‘0’
R/W = ‘0’
E =’1’
Send LCD initialize Data

Sequence with delay
Hex : 0x38
Hex : 0x0C
Hex : 0x06
Hex : 0x80
‘1000’
Send LCD Display

message sequence with
delay “PANTECH
SOLUTIONS”
END

Code Listing :
library IEEE;
entity lcd is
port ( clk : in std_logic; ----clock i/p
lcd_rw : out std_logic; ---read&write control

lcd_e : out std_logic; ----enable control
lcd_rs : out std_logic; ----data or command control
data : out std_logic_vector(7 downto 0)); ---data line
end lcd;
architecture Behavioral of lcd is

constant N: integer :=22;
type arr is array (1 to N) of std_logic_vector(7 downto 0);
constant datas : arr :=
(X"38",X"0c",X"06",X"01",X"C0",X"50",x"41",x"4e",x"54",x"45",x"43",x"48",x"20",x"
53",x"4f",x"4c",x"55",
x"54",x"49",x"4f",x"4e",X"53"); --command and
data to display
begin
lcd_rw <= '0'; ----lcd write
process(clk)
variable j : integer := 1;
begin

if i <= 1000000 then
i := i + 1;
lcd_e <= '1';
data <= datas(j)(7 downto 0);
elsif i > 1000000 and i < 2000000 then
i := i + 1;
lcd_e <= '0';
j := j + 1;
i := 0;
end if;
if j <= 5 then
lcd_rs <= '0'; ---command signal
elsif j > 5 then
lcd_rs <= '1'; ----data signal
end if;
if j = 22 then ---repeated display of data
j := 5;
end if;
end if;
end process;
end Behavioral;
Result
HW : FPGASP3 KIT CON ( J6 )  2x16 CHAR LCD Interface card


9.b – 2 X 16 LCD interface (program to display message “SPARTAN 3 EVK “ in second line of 2 x 16 LCD)
Description
In this example to display message “PANTECH SOLUTIONS” in 2 X 16 LCD second line. In
Spartan3 FPGA lines (P60, P63 and P68) are configured for LCD control lines like (RS, RW &
E). Pins (P77 to P80 and P82 to P85) are configured for LCD data lines. User could verify the
result by “2 X 16 LCD Interface Card” connected to the FPGASP3 KIT at connector J6. User
can modify the LCD display message by changing the data in VHDL code.
Flow Chart
START
Initialize Entity
Set LCD control line

RS = ‘0’
R/W = ‘0’
E =’1’
Send LCD initialize Data

Sequence with delay
Hex : 0x38
Hex : 0x0C
Hex : 0x06
Hex : 0xC0
Send LCD Display

message sequence with
delay “PANTECH
SOLUTIONS”
END

Code Listing :
library ieee;
use ieee.std_logic_arith.all;
entity lcd is
port(clock:in std_logic;
led:out std_logic;
rw: out std_logic;
rs:out std_logic;
en:out std_logic;
data:out std_logic_vector(7 downto 0));
end lcd;
architecture arch of lcd is

signal clkout:std_logic:='0';
type state is( state1,state2,state3,state4,state5,state6,state7,state8, state9,
state10,state111,state22,state23,state24,state25,state26,state27,state28,state29,
state30,state31,state32,state11,state12,state13,state14,state15,state16,state17,
state18,state19,state110,state121,state212,state213,state214,state215,state216,
state217,state218,state219,state300,state310,state320);
signal current_state,next_state:state;
signal count:integer:=0;
begin
process(clock)
begin
if clock'event and clock='1' then
count<=count + 1; -- count for delay
if count =500000 then

clkout<= not clkout;
count<=0;
end if;
end if;
end process;
led<=clkout;
process(clkout)
begin
if clkout'event and clkout='1' then
current_state<=next_state;
end if;
end process;
process(current_state,next_state)
begin
en<='1';
rw<='0';
case current_state is
when state1=>
data<="00111000";
en<='1';
rs<='0';
rw<='0';

next_state<=state11;
when state11=>
data<="00111000";
rs<='0';
rw<='0';
en<='0';
next_state<=state2;
when state2=>
data<="00001110";
en<='1';
rs<='0';
rw<='0';
when state12=>
data<="00001110";
rs<='0';
rw<='0';
en<='0';
next_state<=state3;
when state3=>
data<="00000001";
en<='1';
rs<='0';
rw<='0';
when state13=>
data<="00000001";
rs<='0';
rw<='0';
en<='0';
next_state<=state4;
when state4=>
data<="00000110";
en<='1';
rs<='0';
rw<='0';
when state14=>
data<="00000110";
rs<='0';
rw<='0';
en<='0';
next_state<=state5;
when state5=>
data<="10000000";
en<='1';
rs<='0';
rw<='0';
when state15=>
data<="10000000";
rs<='0';
rw<='0';
en<='0';
next_state<=state6;
when state6=>
data<="01010000"; -- ascii code for "P"
en<='1';
rs<='1';
rw<='0';

when state16=>
data<="01010000"; -- ascii code for "P"
rs<='1';
rw<='0';
en<='0';
next_state<=state7;
when state7=>
data<="01000001"; -- ascii code for "A"
en<='1';
rs<='1';
rw<='0';
when state17=>
data<="01000001"; -- -- ascii code for "A"
rs<='1';
rw<='0';
en<='0';
next_state<=state9;
when state9=>
data<="01001110"; -- ascii code for "N"
en<='1';
rs<='1';
rw<='0';
when state19=>
rs<='1';
rw<='0';
en<='0';
when state10=>
data<="01010100"; -- ascii code for "T"
en<='1';
rs<='1';
rw<='0';
when state110=>
rs<='1';
rw<='0';
en<='0';
when state111=>
data<="01000101"; -- ascii code for "E"
en<='1';
rs<='1';
rw<='0';
when state121=>
data<="01000101"; -- ascii code for "E"
rs<='1';
rw<='0';
en<='0';
when state22=>
data<="01000011"; -- ascii code for "C"
en<='1';
rs<='1';
rw<='0';

when state212=>
data<="01000011"; -- ascii code for "C"
rs<='1';
rw<='0';
en<='0';
when state23=>
data<="01001000"; -- ascii code for "H"
en<='1';
rs<='1';
rw<='0';
when state213=>
data<="01001000"; -- ascii code for "H"
rs<='1';
rw<='0';
en<='0';
when state32=>
data<="00100000"; -- ascii code for " "
en<='1';
rs<='1';
rw<='0';
when state320=>
data<="00100000"; -- ascii code for " "
rs<='1';
rw<='0';
en<='0';
when state24=>
data<="01010011"; -- ascii code for "S"
en<='1';
rs<='1';
rw<='0';
when state214=>
data<="01010011"; -- ascii code for "S"
rs<='1';
rw<='0';
en<='0';
when state25=>
data<="01001111"; -- ascii code for "O"
en<='1';
rs<='1';
rw<='0';
when state215=>
rs<='1';
rw<='0';
en<='0';
when state26=>
data<="01001100"; -- ascii code for "L"
en<='1';
rs<='1';
rw<='0';
when state216=>

data<="01001100"; -- ascii code for "L"
rs<='1';
rw<='0';
en<='0';
when state27=>
data<="01010101"; -- ascii code for "U"
en<='1';
rs<='1';
rw<='0';
when state217=>
data<="01010101"; -- ascii code for "U"
rs<='1';
rw<='0';
en<='0';
when state28=>
en<='1';
rs<='1';
rw<='0';
when state218=>
rs<='1';
rw<='0';
en<='0';
when state29=>
data<="01001001"; -- ascii code for "I"
en<='1';
rs<='1';
rw<='0';
when state219=>
data<="01001001"; -- ascii code for "I"
rs<='1';
rw<='0';
en<='0';
when state30=>
en<='1';
rs<='1';
rw<='0';
when state300=>
rs<='1';
rw<='0';
en<='0';
when state31=>
data<="01001110"; -- ascii code for "n"
en<='1';
rs<='1';
rw<='0';
when state310=>

rs<='1';
rw<='0';
en<='0';
next_state<=state8;
when state8=>
next_state<=state8;
when others=>
next_state<=state8;
end case;
end process;
end arch;
Result
HW : FPGASP3 KIT CON ( J6 )  2x16 CHAR LCD Interface card


10. –DC Motor (To controlled speed of DC Motor using PWM)
Description
In this example to rotate DC motor clockwise/counter clockwise continuously the motor
interface card. For that in Spartan3 FPGA lines (P77, P78) are configured for (Coil-A to
Coil-B). FPGA Lines (P79) to enable the dc motor. User could verify the result by
“Stepper/DC motor Card” connected to the FPGASP3 KIT at connector J6.
Flow Chart
START
Initialize Entity
IF EN=1
Clock Wise
Coil ‘A’ = 1;
Coil ‘B’ = 0;
END

Code Listing :
library IEEE;
entity first is
rst : in std_logic;
enable : out std_logic;
output1 : out std_logic;
output2 : out std_logic);
end first;
begin
process(rst,clk)
begin
if rst = '1' then
enable <= '1';
if i <= 1005000 then
i := i + 1;
output1 <= '0';
output2 <= '0';
elsif i > 1005000 and i < 1550000 then
i := i + 1;
output1 <= '1';
output2 <= '0';
i := 0;
end if;
end if;
end if;
end process;
end Behavioral;
Result
HW : FPGASP3 KIT CON (J6)  DC Motor / Stepper Motor card


• Multiplexers
• Demultiplexers
• Hardware - FPGASP3 Starter Kit | LED & Switch Card
Description - MULTIPLEXERS
Multiplexer is a logic circuit that receives binary information from several inputs and transmits
information to single output. The input selected is controlled by a set of select inputs.

11.a1 – MULTIPLEXERS (Program for 2 x 1 multiplexers using data flow descriptions)
Description
In this program a 2 x 1 multiplexer has two 1- bit inputs, a 1-bit select line and a 1- bit output.
Additional control signals may be added such as enable. The output of the multiplexers depends
on the level of the select line.
Facts:
 Data flow descriptions simulate the system by showing the signals flows from system inputs to
outputs. For example the Boolean function of the output or logical structure of the system shows
such a signal flow. Signal assignment statements are concurrent.
Code Listing
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; ------ library declaration
entity mux2x1 is
port (A, B, SEL, Gbar : in std_logic;
Y : out std_logic); ------ I/O declaration
end mux2x1;
architecture MUX_DF of mux2x1 is

signal S1, S2, S3, S4, S5 : std_logic;
Begin
st1: Y <= S4 or S5 after 7 ns;

st2: S4 <= A and S2 and S1 after 7 ns;
st3: S5 <= B and S3 and S1 after 7 ns; --- functional declaration
st4: S2 <= not SEL after 7 ns;
st5: S3 <= not S2 after 7 ns;
st6: S1 <= not Gbar after 7 ns;
end MUX_DF;
Result
HW : FPGASP3 Starter Kit (Switches - SW3 , SW4, SW5) Selection Lines
LED | Switch Card - LED1 ( Mux O/P)
- SW1 - SW8 ( Mux I/P)
SW : PSTYRO-FPGASP3\Code\EXA-11a1\..............

11. a2 – MULTIPLEXERS (Program for 8 x 1 multiplexers using behavior descriptions)
Description
In this program an 8 x 1 multiplexer has 8- bit inputs, a 3-bit select line and a 1- bit output.
Additional control signals may be added such as enable. The output of the multiplexers depends
on the level of the select line.
Flow Chart
START
Initialize
Entity
Read A, B, SELECT &

ENABLE
IF
ENABLE = 1
IF
Y=A
SELECT = 1
Y=B
Facts:
 The behavioral description describes the system by showing how the outputs behave according
to changes in the inputs.
 In this description we don’t need to know the logic diagram of the system what must be known
is how the output behaves in response to change in the input.
 In VHDL the major behavioral description statement is process.

Code Listing
library IEEE;
entity MUX_if is
port (A, B, SEL, Gbar : in std_logic; Y : out std_logic);
end MUX_if;
architecture MUX_bh of MUX_if is

begin
process (SEL, A, B, Gbar)
-- SEL, A, B, and Gbar are the sensitivity list of

--the process.
variable temp : std_logic;
begin
if Gbar = '0' then
if SEL = '1' then
temp := B;
else
temp := A;
end if;
Y <= temp;
else
Y <= 'Z';
end if;
end process;
end MUX_bh;
Result
LED | Switch Card - LED1 ( Mux O/P)
- SW1 - SW8 ( Mux I/P)
SW : PSTYRO-FPGASP3\Code\EXA-11a2\..............

De-multiplexer
Description
A de-multiplexer performs the reverse operation of a multiplexer. It is a digital function that
receives information on a single line and transmits this information to one of the 2n possible
output lines. The output line being selected is determined by the bit combination of the selected
lines.

11. b1 – DEMULTIPLEXER (Program for 1 x 8 de-multiplexer using gate level descriptions)
Description
In this program a 1 x 8 de-multiplexer have two 1- bit inputs, a 3-bit select line and a 8- bit
output. Additional control signals may be added such as enable. The output of the multiplexers
depends on the level of the select line.
Flow Chart
START
Initialize
Entity
When A & B = ‘0’

IN = Out0
When A = ‘0’& B = ‘1’

IN = Out1
When A = ‘1’ & B = ‘0’

IN = Out2
When A = ‘1’ & B = ‘1’

IN = Out3
END

Code Listing
library ieee;
use ieee.std_logic_arith.all;
entity demultiplexer is
port(e : in std_logic;
s : in std_logic_vector(0 to 2);
y : out std_logic_vector(0 to 7));
end demultiplexer;
architecture data of demultiplexer is
signal s_n : std_logic_vector(0 to 2);

begin
s_n(0) <= not s(0);

s_n(1) <= not s(1);
s_n(2) <= not s(2);
y(0) <= (e and s_n(0)and s_n(1)and s_n(2));
y(1) <= (e and s(0) and s_n(1) and s_n(2));
y(2) <= (e and s_n(0) and s(1) and s_n(2));
y(3) <= (e and s(0) and s(1) and s_n(2));
y(4) <= (e and s_n(0) and s_n(1) and s(2));
y(5) <= (e and s(0) and s_n(1) and s(2));
y(6) <= (e and s_n(0) and s(1) and s(2));
y(7) <= (e and s(0) and s(1) and s(2));
end data;
Result
HW : FPGASP3 Kit ( CON J6 ) - LED | Switch Card

- (SW5, SW6, SW7) - Demux Selection
- (LED1 - LED8) - Demux O/P
- (SW1 - Demux I/P)
SW : PSTYRO-FPGASP3\Code\EXA-11b1\..............

• Encode
• Decoder
• Shift register
• Hardware - FPGASP3 Starter Kit
Encoder:
An encoder has 2n input lines and n output lines. The output lines generate a binary code
corresponding to the input value. For example a single bit 4 to 2 encoder takes in 4 bits and
outputs 2 bits. It is assumed. That there are only 4 types of input signals these are 0001, 0010,
0100 and 1000.
Logical Diagram
Truth Table
A3 A2 A1 A0 F1 F0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

12. a – Encoder (Program for 4 x 2 Encoder using behavior descriptions)
Description
In this program an 8 x 1 encoder has 4- bit inputs and a 2- bit output. The output of the encoders
depends on the level of the input line.
Flow Chart
START
Initialize
Entity
Read input lines
IF
Input = 0001
Output = 00
IF
Input = 0010
Output = 01
IF
Input = 0100
Output = 10
IF
Input = 1000
Output = 11

Code Listing
library IEEE;
entity first is
port ( input : in std_logic_vector(3 downto 0);
output : out std_logic_vector(1 downto 0));
end first;
begin
process(input)
begin
case input is
when "0001" =>
output <= "00";
when "0010" =>
output <= "10";
when "0100" =>
output <= "01";
when "1000" =>
output <= "11";
when others =>
null;
end case;
end process;
end Behavioral;
Result
LED | Switch Card - LED1 ( Encoder O/P)
- SW1 - SW8 ( Encoder I/P)

Decoder:
A decoder is a device which does the reverse of an encoder undoing so that the original
information can be retrieved. The same method used to encode is usually just reversed in order
to decode. In digital electronics this would mean that a decoder is a multiple input, multiple
output logic circuit that converts coded inputs into coded outputs where the input and output
codes are different. E.g. n-to-2n
Logical Diagram

12. b – De-coder (Program for 2 x4 De-coder using behavior descriptions)
Description
In this program a 2 x 4 de-coder has 2- bit inputs and a 4- bit output. The output of the decoders
depends on the level of the input line.
Flow Chart
START
Initialize Entity
Read input lines
When input lines
input =”00” output =”0001

When others
Output = “0000”
END

Code Listing
library IEEE;
entity first is
port ( input : in std_logic_vector(1 downto 0);
output : out std_logic_vector(3 downto 0));
end first;
begin
process(input)
begin
case input is
when "00" =>
output <= "1110";
when "01" =>
output <= "1101";
when "10" =>
output <= "1011";
when "11" =>
output <= "0111";
when others =>
output <= "1111";
end case;
end process;
end Behavioral;
Result

- (SW5, SW6, SW7) - Decoder Selection
- (LED1 - LED8) - Decoder O/P
- (SW1 - Decoder I/P)

Shift register
Serial-in, serial-out shift registers delay data by one clock time for each stage. They will store a
bit of data for each register. The data string is presented at 'Data In', and is shifted right one
stage each time 'Data Advance' is brought high. At each advance, the bit on the far left (i.e. 'Data
In') is shifted into the output. The bit on the far right (i.e. 'Data Out') is shifted out and lost.
Data present th before clock time at D is transferred to Q

12. c – Shift Register (Program for 8-bit shifter using behavior descriptions)
Description
In this program a 8bit shift register has one control line (SW1) made switch ‘ON’ position to
enable the shift register. Every negative edge clock pulses, 1-bit shifted alternatively to right
side, output could verified by ‘LED interface card’.
Flow Chart
START
Initialize
Entity
Enable Clock
Shift 8 bit data one

by one
(‘-‘edge of clock)
END
Code Listing: Refer CD: \PSTYRO-FPGASP3\Code\EXA-12C\.....
Result

- (LED1 - LED8) - Shifter O/P
- (SW1 - Enable I/P)
SW : PSTYRO-FPGASP3\Code\EXA-12c\..............

Getting Started with Xilinx ISE
(Tutorial)

9 - Getting Started with Xilinx ISE
Starting the ISE 8.1 software
To start ISE, double – click the desktop icon,
Or start ISE from the start menu by selecting:

Start → All Programs → Xilinx ISE 8.1i → Project Navigator.
Create a New Project

Create a new ISE project which will target the FPGA device on the Spartan-3 FPGASP3 Kit.

To create a new project:
1. Select File > New Project... The New Project Wizard appears.
2. Type tutorial in the Project Name field.
3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is created
automatically.
4. Verify that HDL is selected from the Top-Level Source Type list.
5. Click Next to move to the device properties page.

6. Fill in the properties in the table as shown below:
 Product Category: All
 Family: Spartan3
 Device: XC3S200
 Package: TQ144 selected.
 Speed Grade: -4
 Top-Level Module Type: HDL
 Synthesis Tool: XST (VHDL/Verilog)

 Simulator: ISE Simulator (VHDL/Verilog)
 Verify that Enable Enhanced Design Summary is
Leave the default values in the remaining fields.
When the table is complete, your project properties will look like the following:
7. Click Next to proceed to the Create New Source window in the New Project Wizard.
Create an HDL Source

You will create the top-level HDL file for your design. Determine the language that you wish to use for
the tutorial. Then, continue either to the “Creating a VHDL Source” section below, or creating a “Creating
a Verilog Source” similar to VHDL source creating.
Creating a VHDL Source

Create a VHDL source file for the project as follows:
1. Click the New Source button in the New Project Wizard.
2. Select VHDL Module as the source type.

3. Type in the file name counter.
4. Verify that the Add to project checkbox is selected.
5. Click Next.
6. Declare the ports for the counter design by filling in the port information as shown below:

8. Click Next, then Finish in the New Source Information dialog box to complete the new source file
template.
+ Refer Lab Examples
Let us we will see source code for Four Digit 7 segment LED display to configure in Spartan 3 FPGA with
synthesis and implementation.
Step 1: copy the above source code and paste it in project window in ISE 8.1i as shown below.

Step 2: Save the file by selecting File → Save the file with .vhd extension.
Step 3: Add your source code in your source window place a cursor above the IC number xc3s200-
4tq144.

Right click → Add source → Open .vhd file.
Step 4: verify that your code is added with synthesis and implementation.
Step 5: Click ok.

Step 6: Checking the Syntax of the 7SEGMENT COUNTER Module
When the source files added complete, check the syntax of the design to find errors and typos.
 Verify that Synthesis/Implementation is selected from the drop-down list in the Sources
window.

 Select the object_co design source in the Sources window to display the related processes in the
Processes window.
 Click the “+” next to the Synthesize-XST process to expand the process group.
 Double-click the Check Syntax process.

Note: You must correct any errors found in your source files. You can check for errors in the
Console tab of the Transcript window. If you continue without valid syntax, you will not be able
to simulate or synthesize your design.
Step 7: Assigning Pin Location Constraints
Specify the pin locations for the ports of the design so that they are connected correctly on the Spartan-3
Advance development board.
To constrain the design ports to package pins, do the following before that refer the chapter 4 for giving
the pin location.
 Verify that object_co is selected in the Sources window.
 Double-click the Assign Package Pins process found in the User Constraints process group. The
Xilinx Pin out and Area Constraints Editor (PACE) opens.
 Select the Package View tab.

 In the Design Object List window, enter a pin location for each pin in the Loc column using the
chapter 4 refer page number 9.
 Select File → Save. You are prompted to select the bus delimiter type window will open. Select
synplify VHDL/exemplar default [] and click OK.
 Close PACE.

Step 8: Implementing the Design
 Select the object_beh source file in the Sources window.
 Double-click the Implement Design process in the Processes tab.
 Notice that after Implementation is complete, the Implementation processes have a green check
mark next to them indicating that they completed successfully without Errors or Warnings.
Step 9: Download Design to the Spartan™-3 Advance Development Board.
This is the last step in the design verification process.
 Connect the 9V AC/DC power cable to the power input on the advance development board (J1).
 Connect the download cable between the PC and development board (J4).
 Select Synthesis/Implementation from the drop-down list in the Sources window.
 Select object_beh in the Sources window.
 In the Processes window, click the “+” sign to expand the Generate Programming File processes.
 Double-click the Configure Device (iMPACT) process.
 In the Welcome dialog box, select Configure devices using Boundary-Scan (JTAG).
 Verify that Automatically connect to a cable and identify Boundary-Scan chain is selected.
 Click Finish.
 If you get a message saying that there are two devices found, click OK to continue.

 The devices connected to the JTAG chain on the board will be detected and displayed in the
iMPACT window
 The Assign New Configuration File dialog box appears. To assign a configuration file to the
xc3s200 device in the JTAG chain, select the object_beh.bit file and click Open.
 If you get a Warning message, click OK.

 Select Bypass to skip any remaining devices.
 Right-click on the xc3s200 device image, and select Program... The Programming Properties
dialog box opens.
 Click OK to program the device.
When programming is complete, the Program Succeeded message is displayed.
On the board, 4 Digits 7 SEG indicating that the counter is running.

 Close iMPACT without saving.

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PSTYRO-FPGASP3

SPARTAN3 Starter Kit

Hardware & Software User Manual

1 www.pantechsolutions.net K-scheme VLSI Lab Manual

2 www.pantechsolutions.net K-scheme VLSI Lab Manual

 Spartan3 Starter Kit (XC3S200)

1.2 - Technical or Customer Support

E-mail questions to : support@pantechsolutions.net

Send questions by mail to

3 www.pantechsolutions.net K-scheme VLSI Lab Manual

 200,000-gate Xilinx Spartan 3 FPGA in a 144-TQFP (XC3S200-4TQG144C)

4 www.pantechsolutions.net K-scheme VLSI Lab Manual

40Pin Expansion 3-bit 8-color

PS/2 8 Nos. LED

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Jumper and Main Switch Selection Details

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40-Pin Expansion Connector

20pin – Box Connector

IO60 1 2 IO63 IO32 1 2 IO33 IO12 1 2 IO13

CONN TRBLK 8x2 CONN TRBLK 8x2 CONN TRBLK 8x2

7 www.pantechsolutions.net K-scheme VLSI Lab Manual

ON/OFF Power +5V ON -External through Adaptor

8 www.pantechsolutions.net K-scheme VLSI Lab Manual

The Evaluation Kit comes with many interfacing options

9 www.pantechsolutions.net K-scheme VLSI Lab Manual

LED-D10 P98 LED1

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11 www.pantechsolutions.net K-scheme VLSI Lab Manual

 RS-232 communication enables point-to-point data transfer. It is commonly used in data

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50MHz Clock P55

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RED GREEN BLUE RESULTING COLOUR

15 www.pantechsolutions.net K-scheme VLSI Lab Manual

VGA Timing Information

Signal Timing for a 60Hz, 640x480 VGA Display

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17 www.pantechsolutions.net K-scheme VLSI Lab Manual

6PIN MINI SPARTAN3

U11 DATA P8 SPARTAN3

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19 www.pantechsolutions.net K-scheme VLSI Lab Manual

20 www.pantechsolutions.net K-scheme VLSI Lab Manual

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8. VLSI Lab Experiments

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Operator Description Input Data Type Output Data Type

HW : FPGASP3 Kit ( CON - J6 ) - LED| Switch Card

24 www.pantechsolutions.net K-scheme VLSI Lab Manual

Port (a : in STD_LOGIC_VECTOR (3 downto 0); -- input/output declaration

architecture Behavioral of code is

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architecture behavior of halfadder is

26 www.pantechsolutions.net K-scheme VLSI Lab Manual

Input A as 4 Input B as 4 Output Y as 4 bit

architecture Behavioral of code is

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architecture Behavioral of code is

28 www.pantechsolutions.net K-scheme VLSI Lab Manual

B (0) x A (1) B (0) x A (0)