module(input [4:0] datain,input clk,input reset,output reg [4:0] dataout,output

empty,output full)
reg [4:0]FIFO[0:7]; //8 locations of 5 bit each.
reg [3:0]fifo_cnt; //full at the 8th location
reg [2:0] wr_ptr,rd_ptr;

always@(posedge clk)
begin
if(rd_en & !empty)
rd_ptr<=rd+ptr+1;
else if(reset)
begin
rd_ptr<=0;
end
end

always@(posedge clk)
begin
if(wr_en & !full)
wr_ptr<=wr_ptr+1;
else if(reset)
begin
wr_ptr<=0;
end
end

always@(posedge clk)
begin
if(rd_en && !empty)
dataout<=FIFO[rd_ptr];
else if(wr_en && !full)
FIFO[wr_ptr]<=datain;
else if(reset)
dataout<=0;
end

assign empty=(fifo_cnt==0)?1:0
assign full=(fifo_cnt==8)?1:0

endmodule