3-D Space Vector PWM Implementation for

Four-Leg Voltage Source Inverter

João I. Y. Ota∗§ , Marcelo G. Villalva∗ ‡ , Fujio Sato† and Ernesto Ruppert∗
∗ Department of Energy Control and Systems (DSCE-FEEC)
UNICAMP (University of Campinas), Campinas-SP, Brazil
† Department of Power Systems (DSEE-FEEC)
UNICAMP (University of Campinas), Campinas-SP, Brazil
‡ Group of Automation and Integrated Systems (GASI)

UNESP, Sorocaba-SP, Brazil

§ Email: joao.inacio.ota@gmail.com

Abstract—The Space Vector PWM implementation and opera- II. SVPWM FOR 3- LEG VSI A PPLICATIONS
tion for a Four-leg Voltage Source Inverter (VSI) is detailed and
discussed in this paper. Although less common, four-leg VSIs
The SVPWM is based on the representation of the voltage
are a viable solution for situations where neutral connection reference in space vector on the αβ0 plan [1], [4], [8]–[11].
is necessary, including Active Power Filter applications. This The αβ0 components can be obtained through the Clarke’s
topology presents advantages regarding the VSI DC link and Transformation [4], [8]:
capacitance, which make it useful for high power devices. Theory,     
implementation and simulations are also discussed in this paper.
Xα r 1 − 12 − 21 Xa
 Xβ  = 2  0
   √ √  
3 3 
Index Terms—Space vector pulse width modulation, Voltage 2 − 2 Xb  (1)
Source Inverters.
  3    
1 1 1
X0 √
2
√
2
√
2
Xc
I. I NTRODUCTION
Three-phase inverters are nowadays used extensively for The variables Xabc and Xαβ0 in (1) can be replaced either
a wide range of applications related to Power Electronics by voltages or currents variables.
and Energy Control Applications. Some solutions for Power A three-leg VSI is showed in Fig.1. The inverter can
Quality issues demand that the inverter should be able to deal assume eight switching states, which six of them represent
with a neutral connection from the load. The use of a neutral non-zero voltage values. The switching states are showed on
connection in a Three-Phase Voltage Source Inverter (VSI) Table I, normalized by VDC . Considering that there is no
may be performed in two ways [1], [2]: neutral connection between the load and the VSI (vn and
• using a three-leg inverter, with a split DC link (or split vn′ in Fig.1 are isolated), the condition va + vb + vc = 0 is
capacitor) topology [3], [4]; satisfied; therefore, in this case, the zero-sequence component
• using a four-leg inverter topology, where one leg stands is unnecessary. Fig.2 shows the representation of the switching
for synthesize the neutral voltage or current [1], [5], [6]. states in the αβ plan.
Although four-leg inverters are less common than three-leg
inverters, this topology presents a robust solution for handling
load imbalances and the need of the neutral current. Also, a
smaller DC capacitance is required [2], and a simpler control +
VDC
(e.g. PI scheme) for the DC voltage may be used, comparing 2
2CDC
S1 S2 S3

with a split-capacitor topology [3]; these features are useful − va

vb
when high power systems applications are considered [2]. vn
′
vn
vc
Lately technological development and cost reduction of power +
electronics equipments are overcoming the issues regarding VDC
S4 S5 S6

costs due to the inverter extra leg. 2

2CDC
−
In order to synthesize currents for positive, negative
and zero-sequence, a Space Vector Pulse Width Modulation
(SVPWM) for a four-leg VSI will be detailed and discussed
in this paper. The objective of using a SVPWM in a four- Fig. 1. Three-leg Voltage Source Inverter.
leg inverter is obtaining the same advantages of a SVPWM
implementation that is used for three-wire cases [7], mainly For a given a voltage reference V ~ ∗ , the output can be
for the higher DC link voltage utilization [1], [2], [5]. synthesized by changing the switching states (or space vectors)

978-1-4577-1646-1/11/$26.00 ©2011 IEEE 79

 TABLE I
N ORMALIZED THREE - LEG VSI OUTPUT VOLTAGES . where d1 and d2 are the respective ratios of the modulation
period which the activation of the space vectors V ~d and
1

S1 S2 S3 Van Vbn Vcn Vα Vβ

~
Vd2 occurs. The remaining time to complete the modulation
~d1 nor V
period (which neither V ~d2 is active) is filled using the
~1
V 000 0 0 0 0 0 ~ ~
q q zero-state vectors V1 and V8 . Their period ratio (dz ) may be
~2
V 001 − 13 − 31 2
− 1
− 1
obtained by
3 6 2
q q
~3
V 010 − 13 2
− 13 − 1 1
3
q6 2
dz = 1 − d1 − d2 (3)
~4
V 011 2
− 31 − 13 − 2
0
3 3
~5 2
q One of them or either zero-state vectors can be used for
V 100 − 31 − 13 2
0
3
q3 q synthesizing the reference voltage. This decision will depend
~6
V 101 − 13 − 31 2 1
− 1
on the sequencing of the space vectors during the modulation
3
q6 q 2
~7
V 110 1
− 32 1 1 1 period [4], [7], [12].
3 3 6 2
In this case, since the SVPWM is only being considered in
~8
V 111 0 0 0 0 0
the plan defined by the αβ variables, this method is called
~3 ~7 as 2-D SVPWM by some authors. The 2-D SVPWM is
V V appropriated for three-wire applications, where there is no
neutral connection with the load. More details about this
Sector 2
procedure can be seen at [4], [7].
When the neutral connection is being considered, the afore-
Sector 3 Sector 1
mentioned 2-D SVPWM may be seen as a three-dimensional
~4 ~8
V ~1
V ~5 SVPWM [4], [11]. A split DC link topology is used, and a
V V
neutral connection for the load is provided (vn and vn′ in Fig.1
Sector 4 Sector 6
are connected). The restriction va + vb + vc = 0 is no more
satisfied, so the zero-sequence must be considered. The values
β
Sector 5 for the new space vectors are showed in Table II. They can
describe a three-dimensional space, as showed in [4], [11].
α
~2
V ~6
V TABLE II
N ORMALIZED THREE - LEG VSI OUTPUTS VOLTAGES FOR 3-D SVPWM.
Fig. 2. 2-d representation.
S1 S2 S3 Van Vbn Vcn Vα Vβ V0
√
~1
V 000 − 12 − 21 − 21 0 0 − 3
from the Table I , within a modulation period [4], [7]; the q q 2

average value of the selected space vectors along the time ~2

V 001 − 12 − 21 1
− 1
− 1
− √1
2
~ ∗ . The time period which q6 2 2 3
will reproduce the reference vector V ~3
V 010 − 12 1
− 21 − 1
q
1
− √ 1
each space vector must be active is obtained by projecting V~∗ 2
q6 2 2 3
~4
V 011 − 12 1 1
− 2
0 1
on the space vectors located at the αβ plan, as presented in 2 2
q 3
√
2 3
Fig.3. ~5
V 100 1
2
− 21 − 21 2
3
0 − √ 1
q q 2 3

V~7 (101)
~6
V 101 1
− 21 1 1
− 1 1
√
2 2 6 2 2 3
q q
~7
V 110 1 1
− 21 1 1 1
β 2 2 6 2
√
2 3
√
~8
V 111 1 1 1
0 0 3
2 2 2 2

V~d2 = d2 · V~7
V~∗ By comparing Tables I and II, it is visible that vectors V~1
and V~8 are no longer zero vectors; they now must be used for
Vm
the synthesis of the voltage output. This method can create the
θ V~5 (100) appropriated voltages for the three-phase inverter connected
α
V~d1 = d1 · V~5 to a four-wire system, but it suffers of a tighter restriction
regarding generating sinusoidal reference and also a reduction
of the modulation index comparing to the 2-D SVM approach
Fig. 3. Reference projection. [4].

This combination can be resumed as (within a modulation III. 3-D SVPWM FOR 4- LEG VSI A PPLICATIONS
period): A. Definitions
A four-leg inverter topology is shown in figure 2. Since
~ ∗ = d1 V
V ~ d + d2 V
~d (2) the neutral connection is been considered, the zero-sequence
1 2

80
 V~8
component from (1) is not zero. Also, due to the inverter
topology, the terminals can present now sixteen switching
states, which fourteen are non-zero voltage values. They are
V~7
V~4
shown in Table III in both abc and αβ0 frame. V~3
010X 110X

V~6

V~5
V~2
S1 S2 S3 S4
+ V~1 V~16 011X 000X 111X 100X
va
vb
VDC vc V~15
CDC V~12 β
V~11
vn
α
−
S5 S6 S7 S8 001X 101X
V~14 V~13
V~10
0
β
(b)
α

Fig. 4. Four-Leg Voltage Source Inverter. V~9

(a)
Fig. 5. (a) 3-D space representation of the four-leg VSI outputs; (b) Projection
TABLE III of four-leg VSI outputs in αβ plan.
N ORMALIZED F OUR -L EG VSI OUTPUTS VOLTAGES .

S1 S2 S3 S4 Van Vbn Vcn Vα Vβ V0

VSI topology. The steps to achieve this objective can be listed
~1
V 0000 0 0 0 0 0 0 as following:
q q
~2 1 1 1 i. identify the vectors to be used in the voltage synthesize;
V 0010 0 0 1 − 6
− 2
√
3
q q ii. determine the periods of activation of each vector;
~3
V 0100 0 1 0 − 1 1 1
√ iii. determine the sequencing of activation for the gate signals.
6 2 3
q
~4
V 0110 0 1 1 − 2
0 2
√
3 3
q B. Reference Vector Synthesis
~5
V 1000 1 0 0 2
0 1
√
3 3
q q The synthesis of the voltage reference follows the same rules
~6
V 1010 1 0 1 1
− 1 2
√ briefly explained at Section II. However, since the reference
6 2 3
q q
~7
V 1100 1 1 0 1 1 2
√
is inserted in a three-dimensional space, three non-zero space
6 2 3
√ vectors should be used to reproduce the reference vector.
~8
V 1110 1 1 1 0 0 3 To reduce power losses due to VSI switching and current
~9
V 0001 −1 −1 −1 0 0
√
− 3 deviation due to the switching during the modulation period,
q q the selected vectors should be the adjacent ones to the ref-
~10
V 0011 −1 −1 0 − 1
− 1
− √23 erence vector. For a 2-D SVPWM, there are various ways
6 2
q q
~11
V 0101 −1 0 −1 − 1 1
− √23 to find the given reference vector in order to determine the
6 2
q space vectors [1], [4], [12]. Generally it consists in determine
~12
V 0111 −1 0 0 − 2
0 − √13 a region (sector, as seen in Fig.2) in the αβ plan where the
3
q
~13
V 1001 0 −1 −1 2
0 − √23 reference vector is located, since the space vectors defines a
3
q q hexagon on the given reference frame.
~14
V 1011 0 0 1 1
− √13
−1 6
− 2 For the 3-D case, the same strategy can be used, but instead
q q
~15
V 1101 0 0 −1 1 1
− √13 of six sectors divided in a hexagon, twenty-four tetrahedrons
6 2
can be defined by the space vectors presented in Table III [1],
~16
V 1111 0 0 0 0 0 0 [8]. The aforementioned sectors defined for the 2-D case can
now be seen as prisms, which contain within each one four
The space vectors from Table III can describe a three- tetrahedrons. Fig.6 shows how these tetrahedrons are situated
dimensional space, showed at Fig.5(a). Observing Fig.5(b), it in the αβ0 space.
can be seen that the projections of the basic space vectors on Therefore, with the reference vector given in a αβ0 refer-
the αβ plan corresponds to the same space vectors obtained ence frame (accordingly with (1), we can define the tetra-
hedron where the vector V ~ ∗ is inserted. Equations (4) to
for the 2-D SVPWM case (Fig.2).
(7) define in which prism, according with figure 3(b), V ~ ∗ is
Using the presented definitions, and accordingly with the
2-D SVPWM synthesis strategy presented in section II, the located.
modulation problem can be resumed in reproducing the refer-  T
~ ∗ using the basic space vectors defined by the
ence vector V ~ ∗ = vα∗
V vβ∗ v0∗ (4)

81
 V~8 TABLE IV
T ETRAHEDRON C OMPOSING S PACE V ECTORS

Prism Tetrahedron ~d
V ~d
V ~d
V
1 2 3

T1 (J = 10) ~5
V ~13
V ~15
V
V~7 V~7 T2 (J = 11) ~5
V V~7 ~15
V
V~5 Prism I (N = 3)
V~5 T13 (J = 9) ~9
V ~13
V ~15
V
T14 (J = 12) ~5
V V~7 V~8
T3 (J = 3) ~3
V V~7 ~15
V
T4 (J = 2) ~3
V ~11
V ~15
V
Prism II (N = 1)
T15 (J = 1) ~9
V ~11
V ~15
V
V~15
T16 (J = 4) ~3
V V~7 V~8
(a) (b)
T5 (J = 18) ~3
V ~
V11 ~
V12
T6 (J = 19) ~3
V V~4 ~12
V
Prism III (N = 5)
T17 (J = 17) ~9
V ~
V11 ~12
V
T18 (J = 20) ~3
V V~4 V~8
V~5 ~2 ~4 ~12
T7 (J = 15) V V V
T8 (J = 14) ~2
V ~10
V ~12
V
Prism IV (N = 4)
T19 (J = 13) ~9
V ~10
V ~12
V
T20 (J = 16) ~2
V V~4 V~8
V~15 ~2 ~10 ~14
V~15
T9 (J = 22) V V V
0
V~13 ~2 ~6 ~14
V~13 T10 (J = 23) V V V
Prism V (N = 6)
β T21 (J = 21) ~9
V ~10
V ~14
V
α V~9 ~2 ~6 ~8
T22 (J = 24) V V V
(c) (d) T11 (J = 7) ~5
V V~6 ~14
V
T12 (J = 6) ~5
V ~13
V ~14
V
Fig. 6. Tetrahedrons in Prism I: (a) Tetrahedron 14; (b) Tetrahedron 2; Prism VI (N = 2)
(c) Tetrahedron 1; (d) Tetrahedron 13. T23 (J = 8) ~5
V V~6 V~8
T24 (J = 5) ~9
V ~
V13 ~
V14

   
v 0 1   Using the obtained variable J it is possible, through Table
 1  √  v∗
   3  α IV, to find the corresponding non-zero space vectors to be used
v2  =  2 − 21    (5) ~ ∗ . The corresponding
   √  v∗ for synthesizing the voltage reference V
β
v3 − 23 − 21 values for each composing space vectors V ~ d ,V
~d and V~d in
1 2 3

 αβ0 reference frame can be found on aforementioned Table

1 if vi >0 III.
sign(vi ) = i = 1, 2, 3 (6)
0 if vi ≤0
C. Application Interval
N = sign(v1 ) + 2 sign(v2 ) + 4 sign(v3 ) (7) The reference voltage, once the space vector are already
The variable N returns a numerical value identifying the defined, can be synthesize by:
prism. Equations (4) to (7) can also be used for sector
identification on 2-D SVPWM [4]. Once knowing which prism ~ ∗ = d1 V
V ~ d + d2 V
~ d + d3 V
~d (11)
1 2 3

is located, the correct tetrahedron can be found by using the ~ d ,V

~d and V ~d correspond to the non-zero com-
value of V~∗ given in abc reference frame values and the where V 1 2 3

variable N obtained [9], [10]: posing space vectors, and d1 , d2 and d3 to the ratios of the
modulation period.
Since the space vectors V ~ d ,V
~d and V ~d and the reference
~ ∗ = [v ∗
V ∗
vbn ∗
vcn ]
T
(8) 1 2 3
an ~ ∗
vector V are known, directly from (11) is possible to deter-
mine the ratios period d1 , d2 and d3 :
∗
ai = sign vin , i = a, b, c (9)    ∗
d1  −1 vα∗
X d2  = V~d V ~d V ~d  vβ  (12)
1 2 3
J = 4 (N − 1) + 1 + ai (10) d3 | {z } v0∗
i [M ]

The variable J returns a numerical value identifying the The matrix M is composed by the composing space vectors
tetrahedron. Table IV shows the corresponding prisms and ~ d ,V
V ~d and V ~d obtained before. As an example, for the
1 2 3
tetrahedrons accordingly to the obtained variables N and J. Tetrahedron 1 (T1, J = 10), Equation (12) will become:

82
 q q q −1
  2 2 1  ∗ dz
d1  3 3 q6  vα tw = ∆Tm (15)
d2  =  1  vβ∗  (13) 4
 0 0 2 

d1

d3 √1
v0∗ tx = ∆Tm tw + (16)
3
− √23 − √13 2
 
The modulation time ratio for the zero vectors can be d2
ty = ∆Tm tx + (17)
obtained by: 2
 
d3
tz = ∆Tm ty + (18)
dz = 1 − d1 − d2 − d3 (14) 2

There are two zero vectors, V ~1 and V

~16 . As just in the 2-D In equations (15)-(18), ∆Tm is the modulation period, and
case, one or both of them can use for synthesizing the output d1 , d2 , d3 and dz are the duty cycles obtained, corresponding
respectively to the selected space vectors V ~ d ,V
~d , V~d and
vector. It will depending on the switching sequence define for 1 2 3

the transistor gates activation. the zero vectors. Since each tetrahedron will have an different
switching sequence, tw , tx , ty and tz will correspond to a
D. Switching sequence different leg switching each time. For example, for Tetrahedron
1, by doing tw = ta , tx = tn , ty = tb and tz = tc , the chosen
Since the duty ratio of the space vectors is already de- pattern is reproduced. Table V resumes the relations for each
termined, it is necessary to define the switching sequence. tetrahedron.
Although the switching sequence does not affect the average
value of the resulting voltage, it has influence on the harmonic TABLE V
ACTIVATING ORDER OF C OMPARISON L EVEL S IGNALS .
content of VSI output and also on the power losses. Also,
depending on the used strategy, one or both zero states may
Tetrahedron tw tx ty tz Tetrahedron tw tx ty tz
be used in the sequence [1], [2], [8].
For this work, it was defined the pattern sequence presented T1 ta tn tb tc T13 tn ta tb tc
in Fig.7. This sequence uses both zero vectors V ~1 and V
~16 ,
T2 ta tb tn tc T14 ta tb tc tn
has symmetry within the modulation period and consequently
T3 tb ta tn tc T15 tn tb ta tc
minimizes the harmonics produced in the inverter output [1],
[4], [8]. Fig.7 shows the sequencing use for the Tetrahedron T4 tb tn ta tc T16 tb ta tc tn
1. For each tetrahedron, there will be a different switching T5 tb tn tc ta T17 tn tb tc ta
sequence, based on the pattern presented in Fig.7. T6 tb tc tn ta T18 tb tc ta tn
T7 tc tb tn ta T19 tn tc tb ta
T8 tc tn tb ta T20 tc tb ta tn
T9 tc tn ta tb T21 tn tc ta tb
T10 tc ta tn tb T22 tc ta tb tn
T11 ta tc tn tb T23 tn ta tc tb
T12 ta tn tc tb T24 ta tc tb tn

Other references [1], [8] explore the use of different pat-

terns, depending on the objectives and also on the power
switches used in the VSI.

IV. D ISCUSSIONS AND S IMULATION

Fig. 7. Switching Sequence for the Tetrahedron 1 space vectors. S1 S2 S3 S4
correspond to the upper switches in the four-leg VSI
For a digital implementation the gate signals can be com-
pared in a up-down counter [4], [10]. Consider tw , tx , ty and
tz the instants that each upper switch in the four-leg VSI
is triggered. They can be given by (in the aforementioned
switching sequence, for Tetrahedron 1):
A. DC Link Capacitance
The use of a four-leg inverter structure can also be justified
by the fact that, in comparison with a capacitor-split three-leg
inverter structure, the DC-link capacitance needed is smaller.
Reference [2] shows how to obtain the minimum capaci-
tance based on the voltage ripple allowed for the DC-link.
For a four-leg inverter, the capacitance may be dimensioned
based on the voltage ripple caused by an unbalanced load. The
minimum capacitance due to the negative-sequence current I −
is given as follow:

83
 √ p
min 3 Vline I−
Cneg = (19) 1.5
4 VDC ω ∆VDC
For a three-leg inverter with a split-capacitor, besides the 1
load unbalance, the DC link will also have a ripple due to the
load neutral current. The minimum equivalent capacitance to 0.5
handle the neutral current In = Ia + Ib + Ic that flows through
the DC-link middle-point is given as follow:
0

min 1 In
Cneutral = (20)
2 ω ∆VDC −0.5
0 0.01 0.02 0.03 0.04 0.05
As a design example, if the same voltage ripple and a (a)
equal rated current are being considered, and for a ratio of
p
Vline /VDC = 0.848, the minimum capacitance for the three- 0.7
leg VSI will be about four times the value of the capacitance 0.65
needed for a four-leg VSI. 0.6

B. DC Link Utilization 0.55

0.5
From the Fig.reffig-2-d-limits, it is possible to observe that
0.45
the SVPWM can synthesize√ a sinusoidal reference without
distortion within VDC / 2 in the αβ plan. Considering in abc 0.4

reference frame,√the inverter will have an maximum voltage 0.35

output of VDC / 3 for each phase, in this case.
0 0.01 0.02 0.03 0.04 0.05
(b)

Fig. 9. Reference waveforms to the switch gates activation for a sinusoidal

output: (a) waveforms for phases abc and (b) waveforms for neutral phase.
VDC
√
2

C. Saturation

β
α
Fig. 8. Maximum voltage for a linear output in 2-D SVPWM.
The Sinusoidal PWM method [12] can synthesize a maxi-
mum sinusoidal phase voltage output of VDC /2. Comparing
the both methods, SVPWM can produce a voltage output
approximated 15% higher using the same reference signal [5],
[12].
Fig.9 shows the waveforms references produced for gate
activation in a digital implementation, considering the switch-
ing sequence given in section III-D. The reference vector V ~∗
is a balanced sinusoidal voltage. Analyzing the waveforms,
this modulation has similar characteristics of a SPWM with
a injection of a 3rd harmonic component [4], [12]. This
performance is lost on the 3-D SVPWM for three-leg VSI
[4], once switching sequences must be modified due to the
~1 and V
fact that vectors V ~8 are no more zero vectors.
Observing the obtained values of V ~1 on Tables II and III,
it is also possible to conclude that the four-leg configuration
allows a higher zero-sequence voltage value synthesis.
The saturation of the SVPWM may happen when the
reference vector V~ ∗ presents a module value higher than
the modulations limits, i.e., when it locates outside the area
showed in Fig.8. Saturation in SVPWM may allow a higher
use of the DC link use, but it will also increase the harmonics
on the VSI output.
In order to handle the saturation, limitations strategies may
be used [8], [13]. They basically consist in delimiting the
voltage synthesis in a linear region. In the 2-D SVPWM case,
it consists in creating boundaries in a circular area inside the
space vector hexagon, as shown in Fig.8.
For the 3-D SVPWM, following the restriction of the 2-
D case, the projection of the V ~ ∗ on the αβ plan may have
∗
the same boundaries form the 2-D case (|vαβ | 6 VDC ) [8];
consequently a cylindrical boundary can be delimited. For the
zero-sequence voltage, in order to avoid distortions, a spherical
boundary can be set when the reference vector is located
in the tetrahedrons that are not around the αβ plan [13]. It
can be seen in Fig.10. Another option
√ is∗ delimiting a√conical
constrain, which may be given by 2|vαβ | + |v0∗ | 6 3VDC
[8]. Both methods can be resumed by the representations in
Fig.10.

84
 20

iCa (A)
0

−20
0.02 0.04 0.06 0.08 0.1 0.12 0.14
20

iCb (A)
0

−20
0.02 0.04 0.06 0.08 0.1 0.12 0.14
20
0

iCc (A)
0

α β −20
0.02 0.04 0.06 0.08 0.1 0.12 0.14
20

iCn (A)
(a) (b) 0

−20
0.02 0.04 0.06 0.08 0.1 0.12 0.14
20
Fig. 10. Synthesis boundaries for 3-D SVPWM: (a) Conical boundary [8]
iSource (A)
(b) Cylindrical boundary [13]
0

−20
0.02 0.04 0.06 0.08 0.1 0.12 0.14
D. Simulation of 4-leg VSI Application Time(s)

An Active Power Filter (APF) was simulated in order to

validate the 3-D SVPWM method presented. The compen- Fig. 12. Active Filter Current outputs (iCa ,iCb ,iCc ,iCn ). iSource corre-
sation strategy was the elimination of harmonics and the sponds to the AC source currents.
compensation of unbalanced load by using the Instantaneous
Power Theory [14], [15]. Fig.11 shows the circuit scheme used
in this simulation. V. C ONCLUSIONS
The four-leg VSI is presented as a viable solution for
AC Source handling with systems and loads that demands a neutral
Non-Linear
connection. The basic use of a SVPWM technique for this kind
load of application was detailed. Although this method may have a
definition and a reference synthesis algorithm more complex
than the three-leg case, it maintains the advantages of the
traditional SVPWM implementation. Besides, it was showed
that four-leg VSI demands a smaller DC link capacitance
and the use of the 3-D SVPWM technique allows a higher
utilization of the DC link voltage; these features make them a
Active Filter interesting alternative for high power applications and devices.
Also, handling the DC link voltage in a single-capacitor
Fig. 11. Circuit Scheme used for simulation of the four-leg VSI with the configuration is simpler, and it avoid a high energy flow in
3-D SVPWM.
the VSI DC link.

The current control loop was based on a Linear Resonant R EFERENCES

Controller [16]. The simulations were performed in MATLab
and PSIM software environment. The DC link voltage was set
to 450V , the VSI output filter was adjusted to L = 2mH
and C = 20uF and the 3-D SVPWM used f = 1/∆T m =
20kHz.
Fig.12 shows the currents synthesized by the APF. It can be
observed that the neutral current is compensated satisfactorily
by the injection of iCn .
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