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Renesas Technology Corp.

Customer Support Dept.
April 1, 2003
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contained therein.
 HD404318 Series

Rev. 6.0
Sept. 1998

Description

The HD404318 Series is 4-bit HMCS400-series microcomputer with large-capacity memory designed to
increase program productivity. Each microcomputer has an A/D converter and input capture timer built in.
They also come with high-voltage I/O pins that can directly drive a fluorescent display.

The HD404318 Series includes four chips: the HD404318 with 8-kword ROM; the HD404316 with 6-
kword ROM; the HD404314 with 4-kword ROM; the HD4074318 with 8-kword PROM.

The HD4074318 is a PROM version ZTAT microcomputer. Programs can be written to the PROM by a
PROM writer, which can dramatically shorten system development periods and smooth the process from
debugging to mass production. (The PROM program specifications are the same as for the 27256.)

ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.

Features

• 34 I/O pins
 One input-only pin
 33 input/output pins: 21 pins are high-voltage pins (40 V, max.)
• On-chip A/D converter (8-bit × 8-channel)
• Three timers
 One event counter input
 One timer output
 One input capture timer
• 8-bit clock-synchronous serial interface (1 channel)
• Alarm output
• Built-in oscillators
 Ceramic or crystal oscillator
 External clock drive is also possible
HD404318 Series
• Seven interrupt sources
 Two by external sources
 Three by timers
 One each by the A/D converter and serial interface
• Two low-power dissipation modes
 Standby mode
 Stop mode
• Instruction cycle time 1 µs (fosc = 4 MHz)

Ordering Information
Type Model Name ROM (words) RAM (digit) Package
Mask ROM HD404314S 4,096 384 DP-42S
HD404314H FP-44A
HD404316S 6,144 DP-42S
HD404316H FP-44A
HD404318S 8,192 DP-42S
HD404318H FP-44A
ZTAT HD4074318S 8,192 DP-42S
HD4074318H FP-44A

Recommended PROM Programmers and Socket Adapters

PROM Programmer Socket Adapter
Manufacture Model Name Package Manufacturer Model Name
DATA I/O Corp. 121B DP-42S Hitachi HS4318ESS01H
FP-44A HS4318ESH01H
AVAL Corp. PKW-1000 DP-42S Hitachi HS4318ESS01H
FP-44A HS4318ESH01H

2
 HD404318 Series
Pin Arrangement

RA1/Vdisp 1 42 R23
R00/SCK 2 41 R22
R01/SI 3 40 R21
R02/SO 4 39 R20
R03/TOC 5 38 R13
TEST 6 37 R12
RESET 7 36 R11
OSC1 8 35 R10
OSC2 9 34 R83
GND 10 33 R82
DP-42S
AVSS 11 32 R81
R30/AN0 12 31 R80
R31/AN1 13 30 D8
R32/AN2 14 29 D7
R33/AN3 15 28 D6
R40/AN4 16 27 D5
R41/AN5 17 26 D4/STOPC
R42/AN6 18 25 D3/BUZZ
R43/AN7 19 24 D2/EVNB
AV CC 20 23 D1/INT1
V CC 21 22 D0/INT0
RA1/Vdisp
R03 /TOC

R00 /SCK
R02 /SO
R01 /SI

R23
R22
R21
R20
R13
NC
44
43
42
41
40
39
38
37
36
35
34

TEST 1 33 R12
RESET 2 32 R11
OSC1 3 31 R10
OSC2 4 30 R83
GND 5 29 R82
AVSS 6 FP-44A 28 R81
R30/AN0 7 27 R80
R31/AN1 8 26 D8
R32/AN2 9 25 D7
R33/AN3 10 24 D6
R40/AN4 11 23 D5
12
13
14
15
16
17
18
19
20
21
22
R42/AN6
R43/AN7
AVCC
VCC
D0/INT0
D1/INT1
D2/EVNB
D3/BUZZ
D4/STOPC
NC
R41/AN5

3
HD404318 Series
PinDescription
Pin Number
Item Symbol DP-42S FP-44A I/O Function
Power supply VCC 21 16 Applies power voltage
GND 10 5 Connected to ground
Vdisp (shared 1 39 Used as a high-voltage output power supply pin when
with RA1) selected by the mask option
Test TEST 6 1 I Cannot be used in user applications. Connect this pin
to GND.
Reset RESET 7 2 I Resets the MCU
Oscillator OSC 1 8 3 I Input/output pin for the internal oscillator. Connect these
pins to the ceramic or crystal oscillator, or OSC 1 to an
external oscillator circuit.
OSC 2 9 4 O
Port D0–D 8 22–30 17–21, I/O Input/output pins addressed individually by bits; D0–D 8
23–26 are all high-voltage I/O pins. Each pin can be
individually configured as selected by the mask option.
RA 1 1 39 I One-bit high-voltage input port pin
R0 0–R0 3, 2–5, 40–43, I/O Four-bit input/output pins consisting of standard voltage
R3 0–R4 3 12–19 7–14 pins

R1 0–R2 3, 31–42 27–38 I/O Four-bit input/output pins consisting of high voltage pins
R8 0–R8 3
Interrupt INT0, INT1 22, 23 17, 18 I Input pins for external interrupts
Stop clear STOPC 26 21 I Input pin for transition from stop mode to active mode
Serial SCK 2 40 I/O Serial interface clock input/output pin
interface
SI 3 41 I Serial interface receive data input pin
SO 4 42 O Serial interface transmit data output pin
Timer TOC 5 43 O Timer output pin
EVNB 24 19 I Event count input pin
Alarm BUZZ 25 20 O Square waveform output pin
A/D AVCC 20 15 Power supply for the A/D converter. Connect this pin as
converter close as possible to the VCC pin and at the same voltage
as VCC. If the power supply voltage to be used for the
A/D converter is not equal to VCC, connect a 0.1-µF
bypass capacitor between the AV CC and AV SS pins.
(However, this is not necessary when the AV CC pin is
directly connected to the VCC pin.)
AVSS 11 6 Ground for the A/D converter. Connect this pin as close
as possible to GND at the same voltage as GND.
AN 0–AN 7 12–19 7–14 I Analog input pins for the A/D converter

4
 HD404318 Series
Pin Description in PROM Mode

The HD4074318 is a PROM version of a ZTAT microcomputer. In PROM mode, the MCU stops
operating, thus allowing the user to program the on-chip PROM.

Pin Number MCU Mode PROM Mode

DP-42S FP-44A Pin I/O Pin I/O
1 39 RA 1/V disp I
2 40 R0 0/SCK I/O VCC
3 41 R0 1/SI I/O VCC
4 42 R0 2/SO I/O
5 43 R0 3/TOC I/O
6 1 TEST I VPP
7 2 RESET I RESET I
8 3 OSC 1 I VCC
9 4 OSC 2 O
10 5 GND GND
11 6 AVSS GND
12 7 R3 0/AN0 I/O O0 I/O
13 8 R3 1/AN1 I/O O1 I/O
14 9 R3 2/AN2 I/O O2 I/O
15 10 R3 3/AN3 I/O O3 I/O
16 11 R4 0/AN4 I/O O4 I/O
17 12 R4 1/AN5 I/O O5 I/O
18 13 R4 2/AN6 I/O O6 I/O
19 14 R4 3/AN7 I/O O7 I/O
20 15 AVCC VCC
21 16 VCC VCC
22 17 D0/INT0 I/O M0 I
23 18 D1/INT1 I/O M1 I
24 19 D2/EVNB I/O A1 I
25 20 D3/BUZZ I/O A2 I
26 21 D4/STOPC I/O
27 23 D5 I/O A3 I
28 24 D6 I/O A4 I
29 25 D7 I/O A9 I
30 26 D8 I/O VCC

5
HD404318 Series
Pin Number MCU Mode PROM Mode
DP-42S FP-44A Pin I/O Pin I/O
31 27 R8 0 I/O CE I
32 28 R8 1 I/O OE I
33 29 R8 2 I/O A13 I
34 30 R8 3 I/O A14 I
35 31 R1 0 I/O A5 I
36 32 R1 1 I/O A6 I
37 33 R1 2 I/O A7 I
38 34 R1 3 I/O A8 I
39 35 R2 0 I/O A0 I
40 36 R2 1 I/O A10 I
41 37 R2 2 I/O A11 I
42 38 R2 3 I/O A12 I
I/O: Input/output pin; I: Input pin; O: Output pin

6
 HD404318 Series
Block Diagram

STOPC
RESET

OSC1
OSC2
TEST

GND
VCC
INT0
System control
Interrupt
control D0
INT1 RAM D1
(384 × 4 bits) D2
D3

D port
D4
W
D5
Timer A (2 bits)
D6
X D7
(4 bits) D8

R00

R0 port
EVNB Timer B R01
SPX
(4 bits) R02
R03
Y
(4 bits)
R10

R1 port
Internal address bus

TOC Timer C R11

R12
Internal data bus

Internal data bus

SPY
R13
(4 bits)

SI R20

R2 port
Serial R21
SO
interface
R22
SCK
R23
ALU

AVSS
R30
R3 port

AN0 R31
• •
A/D ST CA R32
• •
• • converter (1 bit) (1 bit) R33
AN7
A
AVCC (4 bits) R40
R4 port

R41
B
(4 bits) R42
BUZZ Buzzer R43
SP
(10 bits)
R80
Data bus
R8 port

Instruction PC R81
decoder (14 bits) R82
R83
High voltage
pin ROM
(4,096 × 10 bits)
(6,144 × 10 bits)
RA port

(8,192 × 10 bits) RA1

Directional
signal line

7
HD404318 Series

Memory Map

ROM Memory Map

Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines.

Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.

Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction.

Program Area ($0000–$0FFF (HD404314), $0000–$17FF (HD404316), $0000–$1FFF (HD404318,

HD4074318)): The entire ROM area can be used for program coding.

$0000 $0000 JMPL instruction

Vector address $0001 (jump to RESET, STOPC routine)
(16 words)
$000F $0002 JMPL instruction
$0003 (jump to INT 0 routine)
$0010
$0004 JMPL instruction
Zero-page subroutine (jump to INT 1 routine)
$0005
(64 words)
$0006 JMPL instruction
$003F
$0007 (jump to timer A routine)
$0040
$0008 JMPL instruction
Pattern $0009 (jump to timer B routine)
(4,096 words)
$000A JMPL instruction
HD404314
Program $000B (jump to timer C routine)
(4,096 words) $000C JMPL instruction
$0FFF $000D (jump to A/D converter routine)
$1000 $000E JMPL instruction
$000F (jump to serial routine)

HD404316
Program
(6,144 words)

$17FF
$1800

HD404318, HD4074318
Program
(8,192 words)

$1FFF

Note: Since the ROM address areas between $0000-$0FFF overlap, the user can determine how these areas
are to be used.

Figure 1 ROM Memory Map

8
 HD404318 Series
RAM MemoryMap

Initial values
after reset
$000 $000
Interrupt control bits area
RAM-mapped registers $003
$004 Port mode register A (PMRA) W 0000
$040 Memory registers (MR) $005 Serial mode register (SMR) W 0000
$050 $006 Serial data register lower (SRL) R/W Undefined
$007 Serial data register upper (SRU) R/W Undefined
$008 Timer mode register A (TMA) W -000
Data (304 digits) $009 Timer mode register B1 (TMB1) W 0000
*2/0000 *1
$00A Timer B (TRBL/TWBL) R/W
$00B (TRBU/TWBU) R/W Undefined
$00C Miscellaneous register (MIS) W 00--
$180 $00D Timer mode register C (TMC) W 0000
$00E Timer C (TRCL/TWCL) R/W *2/0000
$00F (TRCU/TWCU) R/W Undefined
Not used

Not used
$3C0
Stack (64 digits)
$016 A/D channel register (ACR) W -000
$3FF $017 A/D data register lower (ADRL) R 0000
$018 A/D data register upper (ADRU) R 1000
$019 A/D mode register 1 (AMR1) W 0000
$01A A/D mode register 2 (AMR2) W --00

Not used

$020
Register flag area
$023
$024 Port mode register B (PMRB) W 0000
$025 Port mode register C (PMRC) W 00-0
$026 Timer mode register B2 (TMB2) W -000

Not used

Notes: 1. Two registers are mapped

on the same area ($00A,
$00B, $00E, $00F).
$030 Port R0 DCR (DCR0) W 0000
2. Undefined.
Not used
R: Read only
W: Write only $033 Port R3 DCR (DCR3) W 0000
R/W: Read/write $034 Port R4 DCR (DCR4) W 0000

Not used

$03F

$00A Timer read register B lower (TRBL) R Timer write register B lower (TWBL) W
$00B Timer read register B upper (TRBU) R Timer write register B upper (TWBU) W

$00E Timer read register C lower (TRCL) R Timer write register C lower (TWCL) W
$00F Timer read register C upper (TRCU) R Timer write register C upper (TWCU) W

Figure 2 RAM Memory Map and Initial Values

9
HD404318 Series
Table 1 Initial Values of Flags after MCU Reset

Item Initial Value

Interrupt flags/mask Interrupt enable flag (IE) 0
Interrupt request flag (IF) 0
Interrupt mask (IM) 1
Bit registers Watchdog timer on flag (WDON) 0
A/D start flag (ADSF) 0
Input capture status flag (ICSF) 0
Input capture error flag (ICEF) 0
I AD off flag (IAOF) 0
RAM enable flag (RAME) 0

RAM Address Bit 3 Bit 2 Bit 1 Bit 0

IM0 IF0 RSP IE

$0000 (IM of INT0) (IF of INT0) (Reset SP bit) (Interrupt
enable flag)

$0001 IMTA IFTA IM1 IF1

(IM of timer A) (IF of timer A) (IM of INT1) (IF of INT1)

IMTC IFTC IMTB IFTB

$0002
(IM of timer C) (IF of timer C) (IM of timer B) (IF of timer B)

IMS IFS IMAD IFAD

$0003
(IM of serial) (IF of serial) (IM of A/D) (IF of A/D)

Interrupt control bits area

Bit 3 Bit 2 Bit 1 Bit 0

ADSF WDON
$020 Not used (Watchdog Not used
(A/D start flag)
on flag)
RAME ICEF ICSF
(RAM enable IAOF
$021 (Input capture (Input capture
flag) (IAD off flag)
IF: Interrupt error flag) status flag)
request flag
IM: Interrupt $022
mask Not used
IE: Interrupt
enable flag $023
SP: Stack pointer
Register flag area

Figure 3 Interrupt Control Bits and Register Flag Areas Configuration

10
 HD404318 Series

SEM/SEMD REM/REMD TM/TMD

IE
IM Allowed Allowed Allowed
IAOF
IF
ICSF
Not executed Allowed Allowed
ICEF
RAME
RSP Not executed Allowed Inhibited
WDON Allowed Not executed Inhibited
ADSF Allowed Inhibited Allowed
Not used Not executed Not executed Inhibited
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. The REM or REMD
instruction must not be executed for ADSF during A/D conversion. If the TM or TMD instruction is
executed for the inhibited bits or non-existing bits, the value in ST becomes invalid.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

Memory registers Stack area

$040 MR(0) $3C0 Level 16
$041 MR(1) Level 15
$042 MR(2) Level 14
$043 MR(3) Level 13
$044 MR(4) Level 12
$045 MR(5) Level 11
$046 MR(6) Level 10
$047 MR(7) Level 9 Bit 3 Bit 2 Bit 1 Bit 0
$048 MR(8) Level 8
$3FC ST PC 13 PC 12 PC 11
$049 MR(9) Level 7
$04A MR(10) Level 6
$3FD PC 10 PC 9 PC 8 PC 7
$04B MR(11) Level 5
$04C MR(12) Level 4
CA PC 6 PC 5 PC 4
$3FE
$04D MR(13) Level 3
$04E MR(14) Level 2
$3FF PC 3 PC2 PC 1 PC0
$04F MR(15) $3FF Level 1

PC13 –PC0 : Program counter

ST: Status flag
CA: Carry flag

Figure 5 Configuration of Memory Registers and Stack Area, and Stack Position

11
HD404318 Series
Registers and Flags

3 0
Accumulator Initial value: Undefined, R/W (A)

3 0
B register Initial value: Undefined, R/W (B)

1 0
W register Initial value: Undefined, R/W (W)

3 0
X register Initial value: Undefined, R/W (X)

3 0
Y register Initial value: Undefined, R/W (Y)

3 0
SPX register Initial value: Undefined, R/W (SPX)

3 0
SPY register Initial value: Undefined, R/W (SPY)

0
Carry Initial value: Undefined, R/W (CA)

0
Status Initial value: 1, no R/W (ST)

13 0
Program counter
Initial value: 0, (PC)
no R/W
9 5 0
Stack pointer
1 1 1 1 (SP)
Initial value: $3FF, no R/W

Figure 6 Registers and Flags

12
 HD404318 Series

Addressing Modes

RAM Addressing Modes

Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits total) are used as
a RAM address.

Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.

Memory Register Addressing Mode (LAMR, XMRA): The memory registers (MR), which are located
in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions.

1 0 3 0 3 0 3 0

W X Y Instruction Opcode

9 7 3 0 9 0

RAM address RAM address 0 0 0 1 0 0

Register Indirect Addressing Memory Register Addressing

1st instruction 2nd instruction

9 word 0 9 word 0

Instruction Opcode

9 0

RAM address

Direct Addressing

Figure 7 RAM Addressing Modes

13
HD404318 Series

ROM Addressing Modes

Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the
JMPL, BRL, or CALL instruction.

Current Page Addressing Mode: A program can branch to any address in the current page (256 words
per page) by executing the BR instruction.

Zero-Page Addressing Mode: A program can branch to any subroutine located in the zero-page
subroutine area ($0000–$003F) by executing the CAL instruction.

Table Data Addressing Mode: A program can branch to an address determined by the contents of 4-bit
immediate data, the accumulator, and the B register by executing the TBR instruction.

1st 2nd
instruction word instruction word
9 3 09 0 9 5 0
Opcode
Opcode Operand Operand

13 0 13 0

Program counter Program counter 0 0 0 0 0 0 0 0

Direct Addressing Zero-Page Addressing

Operand
9 7 0 9 3 0 7 3 0
Opcode
Operand Opcode B A

13 0 13 0

Program counter * * * * * * Program counter 0 0

Current Page Addressing Table Data Addressing

Figure 8 ROM Addressing Modes

14
 HD404318 Series
Table 2 Instruction Set Classification

Number of
Instruction Type Function Instructions
Immediate Transferring constants to the accumulator, B register, and RAM. 4
Register-to-register Transferring contents of the B, Y, SPX, SPY, or memory registers to 8
the accumulator
RAM addressing Available when accessing RAM in register indirect addressing mode 13
RAM register Transferring data between the accumulator and memory. 10
Arithmetic Performing arithmetic operations with the contents of the accumulator, 25
B register, or memory.
Compare Comparing contents of the accumulator or memory with a constant 12
RAM bit manipulation Bit set, bit reset, and bit test. 6
ROM addressing Branching and jump instructions based on the status condition. 8
Input/output Controlling the input/output of the R and D ports; ROM data reference 11
with the P instruction
Control Controlling the serial communication interface and low-power 4
dissipation modes.
Total: 101
instructions

15
HD404318 Series
Interrupts

$000,0
IE Interrupt
request
(RESET, STOPC)

Priority Controller
$000,2
Priority Order Vector Address
INT0 interrupt IF0 $0000
$000,3 1 $0002
IM0 2 $0004
3 $0006
$001,0 4 $0008
INT1 interrupt IF1 5 $000A
$001,1 6 $000C
7 $000E
IM1
$001,2
Timer A interrupt IFTA
$001,3
IMTA
$002,0
Timer B interrupt IFTB
$002,1
IMTB
$002,2
Timer C interrupt IFTC
$002,3
IMTC
$003,0
A/D interrupt IFAD
$003,1
IMAD
$003,2
Serial interrupt IFS
$003,3
IMS

Figure 9 Interrupt Control Circuit

16
 HD404318 Series
Instruction cycles
1 2 3 4 5 6

Instruction
execution*

Stacking
Interrupt
acceptance Vector address
IE reset
generation

Execution of JMPL
instruction at vector address

Execution of
instruction at
start address
of interrupt
Note: * The stack is accessed and the IE reset after the instruction routine
is executed, even if it is a two-cycle instruction.

Figure 10 Interrupt Processing Sequence

17
HD404318 Series

Operating Modes

The MCU has three operating modes as shown in table 3. Transitions between operating modes are shown
in figure 11.

Table 3 Operations in Each Operating Mode

Function Active Mode Standby Mode Stop Mode

System oscillator OP OP Stopped
CPU OP Retained Reset
RAM OP Retained Retained
Timer A OP OP Reset
Timers B, C OP OP Reset
Serial interface OP OP Reset
A/D OP OP Reset
I/O OP Retained Reset
Note: OP implies in operation

18
 









,


 
,
HD404318 Series

Reset by
RESET input or
by watchdog timer

RAME = 0 RAME = 1


RESET 1 RESET 2

Active STOPC
Standby mode mode Stop mode

SBY
fOSC: Oscillate instruction fOSC: Oscillate STOP fOSC: Stop
instruction
øCPU: Stop øCPU: fcyc øCPU: Stop
Interrupt
øPER: fcyc øPER: fcyc øPER: Stop

fOSC: Main oscillation frequency

fcyc: fOSC/4
øCPU: System clock
øPER: Clock for other peripheral
functions

Figure 11 MCU Status Transitions

In stop mode, the system oscillator is stopped. To ensure a proper oscillation stabilization period of at least
tRC when clearing stop mode, execute the cancellation according to the timing chart in figure12.

Stop mode

Oscillator

Internal
clock

RESET
or
STOPC tres
STOP instruction execution tres ≥ tRC (stabilization period)

Figure 12 Timing of Stop Mode Cancellation

19
HD404318 Series
MCU Operation Sequence: The MCU operates in the sequence shown in figure 13 and figure 14.
The low-power mode operation sequence is shown in figure 14. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.

Power ON

No
RESET = 0?

Yes

MCU operation cycle

RAME = 0

Yes
IF = 1?
Reset MCU

No
No IM = 0
IE = 1

Yes
Instruction
RAME = 1
execution

Reset input IE ← 0
Stack ← (PC),
SBY/STOP
(CA), (ST)
instruction

No

PC ← vector
Low-power mode PC ← (PC)+1
operation cycle address
(figure 15)

Figure 13 MCU Operating Sequence (Power ON)

20
 HD404318 Series

Low-power mode
operation cycle

IF = 1 and No
IM = 0?

Yes
Standby mode Stop mode

No IF = 1 and No
STOPC = 0?
IM = 0?

Yes Yes

Hardware NOP Hardware NOP RAME = 1

execution execution

PC ← Next PC ← Next Reset MCU

Iocation Iocation

Instruction
execution

MCU operation
cycle

Figure 14 MCU Operating Sequence (Low-Power Mode Operation)

21
HD404318 Series

Oscillator Circuit

Figure 15 shows a block diagram of the clock generation circuit.

CPU with ROM,

OSC2 System fOSC 1/4 fcyc Timing øCPU
RAM, registers,
oscillator division generator
tcyc flags, and I/O
circuit circuit
OSC1

øPER Peripheral
function
interrupt

Figure 15 Clock Generation Circuit

TEST

RESET

OSC1

OSC2

GND

AVSS

Figure 16 Typical Layout of Crystal and Ceramic Oscillator

22
 HD404318 Series
Table 4 Oscillator Circuit Examples

Circuit Configuration Circuit Constants

External clock
operation External
OSC 1
oscillator

Open OSC 2

Ceramic oscillator C1 Ceramic oscillator: CSA4.00MG (Murata)

(OSC1, OSC 2) Rf = 1 MΩ ±20%
OSC1

Ceramic
C1 = C2 = 30 pF ±20%
Rf

OSC2
C2
GND

Crystal oscillator C1 Rf = 1 MΩ ±20%

(OSC1, OSC 2) C1 = C2 = 10 to 22 pF ±20%
OSC1
Crystal: Equivalent to circuit shown below
Crystal Rf
C0 = 7 pF max.
OSC2
RS = 100 Ω max.
C2
GND
L CS RS

OSC1 OSC2

CO

Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray
capacitance of the board, the user should consult with the crystal or ceramic oscillator
manufacturer to determine the circuit parameters.
2. Wiring among OSC1, OSC 2, and elements should be as short as possible, and must not cross
other wiring (see figure 16).

23
HD404318 Series

I/O Ports

The MCU has 33 input/output pins (D0–D 8, R0–R4, R8) and one input-only pin (RA1). The following
describes the features of the I/O ports.

• The 21 pins consisting of D0–D8, R1, R2, and R8 are all high-voltage I/O pins. RA1 is a high-voltage
input-only pin. These high-voltage pins can be equipped with or without pull-down resistance, as
selected by the mask option.
• All standard output pins are CMOS output pins. However, the R02/SO pin can be programmed for
NMOS open-drain output.
• In stop mode, input/output pins go to the high-impedance state
• All standard input/output pins have pull-up MOS built in, which can be individually turned on or off by
software

Table 5 Control of Standard I/O Pins by Program

MIS3 (bit 3 of MIS) 0 1

DCR 0 1 0 1
PDR 0 1 0 1 0 1 0 1
CMOS buffer PMOS — — — On — — — On
NMOS — — On — — — On —
Pull-up MOS — — — — — On — On
Note: — indicates off.

Data control register (DCR0: $030, DCR3: $033, DCR4: $034)

DCR0, DCR3,
DCR4
Bit 3 2 1 0
Initial value 0 0 0 0
Read/Write W W W W Bits 0 to 3 CMOS Buffer Control

Bit name DCR03, DCR02, DCR01, DCR00, 0 CMOS buffer off

DCR33, DCR32, DCR31, DCR30, (high impedance)
DCR43, DCR42, DCR41, DCR40
1 CMOS buffer on

Correspondence between ports and DCR bits

Register Bit 3 Bit 2 Bit 1 Bit 0
DCR0 R03 R02 R01 R00
DCR3 R33 R32 R31 R30
DCR4 R43 R42 R41 R40

Figure 17 Data Control Register (DCR)

24
 HD404318 Series
Table 6 Circuit Configurations of Standard I/O Pins

I/O Pin Type Circuit Pins

Input/output pins HLT R0 0, R0 1, R0 3
VCC Pull-up control signal
VCC MIS3 R3 0–R3 3,
Buffer control
signal R4 0–R4 3
DCR
Output data
PDR

Input data
Input control signal

HLT R0 2
VCC Pull-up control signal
VCC MIS3
Buffer control
signal
DCR
MIS2
PDR
Output data
Input data
Input control signal

Peripheral Input/ output HLT SCK

function pins pins VCC Pull-up control signal
VCC MIS3

Output data
SCK
Input data
SCK

Output pins HLT SO

VCC Pull-up control signal
VCC MIS3

PMOS control
signal
MIS2
SO
Output data

HLT TOC
VCC Pull-up control signal
VCC MIS3

Output data
TOC

Notes on next page.

25
HD404318 Series
I/O Pin Type Circuit Pins
Peripheral Input/ pins VCC SI
function pins
HLT
MIS3
PDR
Input data
SI

VCC AN 0–AN 7
HLT
MIS3
PDR

A/D input

Input control
Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT
signal goes low, and input/output pins the enter high-impedance state.
2. The HLT signal is 1 in active and standby modes.

26
 HD404318 Series
Table 7 Circuit Configurations for High-Voltage Input/Output Pins

I/O Pin Type With Pull-Down Resistance Without Pull-Down Resistance Pins
Input/output VCC VCC D0–D 8,
pins HLT HLT
R1 0–R1 3,
Output Output
data data R2 0–R2 3,
Pull-down Input data
resistance
R8 0–R8 3
Input control
Vdisp signal
Input data
Input control
signal

Input pins Input data RA 1

Input control
signal

Peripheral Output VCC VCC BUZZ

function pins pins HLT HLT
Output Output
data data
Pull-down
resistance
Vdisp

Input Input data Input data INT0,

pins INT1,
Pull-down
resistance EVNB,
Vdisp STOPC
Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT
signal goes low, and input/output pins the enter high-impedance state.
2. The HLT signal is 1 in active and standby modes.
3. The circuits of HD4074318 are without pull-down resistance.

27
HD404318 Series

Port mode register A (PMRA: $004)

Bit 3 2 1 0
Initial value 0 0 0 0
Read/Write W W W W
Bit name PMRA3 PMRA2 PMRA1 PMRA0

PMRA0 R02/SO Mode Selection

0 R02
PMRA2 R03/TOC Mode Selection
1 SO
0 R03
1 TOC PMRA1 R01/SI Mode Selection
0 R01
PMRA3 D3/BUZZ Mode Selection
1 SI
0 D3
1 BUZZ

Figure 18 Port Mode Register A (PMRA)

Port mode register B (PMRB: $024)

Bit 3 2 1 0
Initial value 0 0 0 0
Read/Write W W W W
Bit name *
PMRB3 PMRB2 PMRB1 PMRB0

PMRB0 D0/INT0 Mode Selection

0 D0
PMRB2 D2/EVNB Mode Selection
0
1 INT0
D2
1 EVNB PMRB1 D1/INT1 Mode Selection
0 D1
PMRB3 D4/STOPC Mode Selection
0
1 INT1
D4
1 STOPC

Note: * PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode,
PMRB3 is not reset but retains its value.

Figure 19 Port Mode Register B (PMRB)

28
 HD404318 Series

Miscellaneous register (MIS: $00C)

Bit 3 2 1 0
Initial value 0 0 — —
Read/Write W W — —
Bit name MIS3 MIS2 Not used Not used

Pull-Up MOS CMOS Buffer

MIS3 On/Off Selection On/Off Selection
MIS2 for Pin R02/SO
0 Pull-up MOS off
0 CMOS on
1 Pull-up MOS on
1 CMOS off
(refer to table 5)

Note: The on/off status of each transistor and the peripheral function mode of each
pin can be set independently.

Figure 20 Miscellaneous Register (MIS)

29
HD404318 Series

Prescaler

The MCU has a built-in prescaler labeled as prescaler S (PSS), which divides the system clock and then
outputs divided clock signals to the peripheral function modules, as shown in figure21.

Timer A

Timer B
System Clock
Prescaler S
clock selector
Timer C

Serial

Figure 21 Prescaler Output Supply

30
 HD404318 Series

Timers

The MCU has three built-in timers: A, B, and C. The functions of each timer are listed in table 7.

Timer A

Timer A is an 8-bit free-running timer that has the following features:

• One of eight internal clocks can be selected from prescaler S according to the setting of timer mode
register A (TMA: $008)
• An interrupt request can be generated when timer counter A (TCA) overflows
• Input clock frequency must not be modified during timer A operation

Table 7 Timer Functions

Functions Timer A Timer B Timer C

Clock source Prescaler S Available Available Available
External event — Available —
Timer functions Free-running Available Available Available
Event counter — Available —
Reload — Available Available
Watchdog — — Available
Input capture — Available —
Timer output PWM — — Available

31
HD404318 Series

Timer A interrupt
request flag
(IFTA)

Internal data bus

Timer
counter A
(TCA) Overflow

Selector

÷ 1024
÷ 2048
÷ 128
÷ 512
÷ 32
÷2
÷4
÷8

System øPER
clock Prescaler S (PSS) 3

Timer mode
register A
(TMA)

Figure 22 Timer A Block Diagram

Timer mode register A (TMA: $008)

Bit 3 2 1 0
Initial value — 0 0 0
Read/Write — W W W
Bit name Not used TMA2 TMA1 TMA0

Source Input clock

TMA2 TMA1 TMA0 Prescaler frequency

0 0 0 PSS 2048tcyc
1 PSS 1024tcyc
1 0 PSS 512tcyc
1 PSS 128tcyc

1 0 0 PSS 32tcyc
1 PSS 8tcyc
1 0 PSS 4tcyc
1 PSS 2tcyc

Figure 23 Timer Mode Register A (TMA)

32
 HD404318 Series
Timer B

Timer B is an 8-bit multifunction timer that includes free-running, reload, and input capture timer features.
These are described as follows.

• By setting timer mode register B1 (TMB1: $009), one of seven internal clocks supplied from prescaler
S can be selected, or timer B can be used as an external event counter
• By setting timer mode register B2 (TMB2: $026), detection edge type of EVNB can be selected
• By setting timer write register BL, BU (TWBL, BU: $00A, $00B), timer counter B (TCB) can be
written to during reload timer operation
• By setting timer read register BL, BU (TRBL, BU: $00A, $00B), the contents of timer counter B can
be read out
• Timer B can be used as an input capture timer to count the clock cycles between trigger edges input as
an external event
• An interrupt can be requested when timer counter B overflows or when a trigger input edge is received
during input capture operation

33
HD404318 Series

Interrupt request
flag of timer B
(IFTB)

Timer read
register BU
(TRBU) Timer read
register B lower
(TRBL)

Clock
Timer counter B
(TCB) Overflow
Free-running

Internal data bus

timer control
signal
Timer write
register B upper
(TWBU)

Timer write
Selector register B lower
EVNB
(TWBL)
Edge
÷ 2048

detector
÷ 128
÷ 512
÷ 32

3
÷2
÷4
÷8

Timer mode
System øPER register B1
Prescaler S (PSS) (TMB1)
clock

2 Edge detection control signal

Timer mode
register B2
(TMB2)

Figure 24 Timer B Free-Running and Reload Operation Block Diagram

34
 HD404318 Series

Input capture Input capture Interrupt request

status flag error flag flag of timer B
(ICSF) (ICEF) (IFTB)

Error
controller

Timer read
register BU
(TRBU)

Timer read
register B lower
(TRBL)

EVNB Read Clock

Edge signal Timer counter B

Internal data bus

detector (TCB)
Overflow
Input capture
timer control
signal

Selector
3
÷ 2048

Timer mode
÷ 128
÷ 512
÷ 32

register B1
÷2
÷4
÷8

(TMB1)
System øPER
Prescaler S (PSS)
clock

2 Edge detection control signal

Timer mode
register B2
(TMB2)

Figure 25 Timer B Input Capture Operation Block Diagram

35
HD404318 Series

Timer mode register B1 (TMB1: $009)

Bit 3 2 1 0
Initial value 0 0 0 0
Read/Write W W W W
Bit name TMB13 TMB12 TMB11 TMB10

Free-Running/Reload Input Clock Period and Input

TMB13 Timer Selection TMB12 TMB11 TMB10 Clock Source

0 Free-running timer 0 0 0 2048tcyc

1 Reload timer 1 512tcyc
1 0 128tcyc
1 32tcyc
1 0 0 8tcyc
1 4tcyc
1 0 2tcyc
1 D2/EVNB (external event input)

Figure 26 Timer Mode Register B1 (TMB1)

Timer mode register B2 (TMB2: $026)

Bit 3 2 1 0
Initial value — 0 0 0
Read/Write — W W W
Bit name Not used TMB22 TMB21 TMB20

TMB21 TMB20 EVNB Edge Detection Selection

0 0 No detection
1 Falling edge detection
1 0 Rising edge detection
1 Rising and falling edge detection

TMB22 Free-Running/Reload and Input Capture Selection

0 Free-Running/Reload
1 Input capture

Figure 27 Timer Mode Register B2 (TMB2)

36
 HD404318 Series
Timer C

Timer C is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features,
which are described as follows.

• By setting timer mode register C (TMC: $00D), one of eight internal clocks supplied from prescaler S
can be selected
• By selecting pin TOC with bit 2 (PMRA2) of port mode register A (PMRA: $004), timer C output
(PWM output) is enabled
• By setting timer write register CL, CU (TWCL, CU: $00E, $00F), timer counter C (TCC) can be
written to
• By setting timer read register CL, CU (TRCL, CU: $00E, $00F), the contents of timer counter C can be
read out
• An interrupt can be requested when timer counter C overflows
• Timer counter C can be used as a watchdog timer for detecting runaway program

37
HD404318 Series

System reset signal

Interrupt request
Watchdog on Watchdog timer
flag of timer C
flag (WDON) controller
(IFTC)

Timer read register CU (TRCU)

TOC
Timer output Timer read
control logic register C lower
(TRCL)

Clock
Timer counter C
(TCC) Overflow

Internal data bus

Timer
output
control Timer write
signal register C upper
(TWCU)

Timer write
Selector Free-running register C lower
timer control (TWCL)
signal
÷ 1024
÷ 2048
÷ 128
÷ 512
÷ 32

3
÷2
÷4
÷8

System øPER Timer mode

Prescaler S (PSS) register C (TMC)
clock

Port mode
register A (PMRA)

Figure 28 Timer C Block Diagram

38
 HD404318 Series

Timer mode register C (TMC: $00D)

Bit 3 2 1 0
Initial value 0 0 0 0
Read/Write W W W W
Bit name TMC3 TMC2 TMC1 TMC0

Free-Running/Reload TMC2 TMC1 TMC0 Input Clock Period

TMC3 Timer Selection
0 0 0 2048tcyc
0 Free-running timer 1024tcyc
1
1 Reload timer
1 0 512tcyc
1 128tcyc

1 0 0 32tcyc

1 8tcyc
1 0 4tcyc

1 2tcyc

Figure 29 Timer Mode Register C (TMC)

T × (N + 1)

TMC3 = 0
(Free-running
timer)

T × 256
T

TMC3 = 1
(Reload timer)

T × (256 – N)
Notes: T: Input clock period supplied to counter. (The clock source and system clock division ratio are
determined by timer mode register C.)
N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.)

Figure 30 PWM Output Waveform

39
HD404318 Series
$FF + 1

Overflow
Timer C
count value

$00
Time

CPU Normal Timer C Normal Timer C Program Normal

Reset
operation operation clear operation clear runaway operation

Figure 31 Watchdog Timer Operation Flowchart

Notes on Use

When using the timer output as PWM output, note the following point. From the update of the timer write
register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 8. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.

Table 8 PWM Output Following Update of Timer Write Register

PWM Output
Timer Write Register is Updated during Timer Write Register is Updated during
Mode High PWM Output Low PWM Output
Free running Timer write Timer write
register register
updated to Interrupt updated to Interrupt
value N request value N request

T × (255 – N) T × (N + 1) T × (N' + 1)
T × (255 – N) T × (N + 1)

Reload Timer write Timer write

register register
updated to Interrupt updated to Interrupt
value N request value N request

T T × (255 – N) T T

T × (255 – N) T

40
 HD404318 Series
Alarm Output Function

The MCU has an alarm output function built in. By setting port mode register C (PMRC: $025), one of
four alarm frequencies supplied from the PSS can be selected.

Table 9 Port Mode Register C

PMRC
Bit 3 Bit 2 System Clock Divisor
0 0 ÷ 2048
1 ÷ 1024
1 0 ÷ 512
1 ÷ 256

BUZZ Alarm output

Alarm output control signal Port mode
controller register A
(PMRA)

Internal data bus

Selector
2
Port mode
÷ 1024

÷ 2048
÷ 256

÷ 512

register C
(PMRC)

System øPER
Prescaler S (PSS)
clock

Figure 32 Alarm Output Function Block Diagram

41
HD404318 Series

Serial Interface

The MCU has a one-channel serial interface built in with the following features.

• One of 13 different internal clocks or an external clock can be selected as the transmit clock. The
internal clocks include the six prescaler outputs divided by two and by four, and the system clock.
• During idle states, the serial output pin can be controlled to be high or low output
• Transmit clock errors can be detected
• An interrupt request can be generated after transfer has completed when an error occurs

Table 10 Serial Interface Operating Modes

SMR PMRA
Bit 3 Bit 1 Bit 0 Operating Mode
1 0 0 Continuous clock output mode
1 Transmit mode
1 0 Receive mode
1 Transmit/receive mode

42
 HD404318 Series

Serial interrupt
Octal
request flag
SO counter (OC)
(IFS)
Idle
controller
SCK
I/O Serial data
controller register (SR)
SI Clock

Internal data bus

Transfer
1/2 1/2 control

Selector
signal

Selector
3
Serial mode
÷ 2048

register
÷ 128
÷ 512
÷ 32

(SMR)
÷2
÷8

System øPER
Prescaler S (PSS)
clock Port mode
register C
(PMRC)

Figure 33 Serial Interface Block Diagram

43
HD404318 Series

STS wait state MCU reset

(Octal counter = 000,
transmit clock disabled)

SMR write SMR write (IFS ← 1)

STS instruction

Transmit clock
Transmit clock wait state Transfer state
(Octal counter = 000) (Octal counter = 000)
8 transmit clocks or STS instruction (IFS ← 1)

External clock mode

STS wait state MCU reset

(Octal counter = 000,
SMR write transmit clock disabled)

Continuous clock output state

SMR write 8 transmit clocks or
(PMRA 0, 1 = 0, 0)
STS instruction SMR write (IFS ←1)

Transmit clock
Transmit clock
Transmit clock wait state Transfer state
(Octal counter = 000) (Octal counter = 000)
STS instruction (IFS ← 1)

Internal clock mode

Figure 34 Serial Interface State Transitions

Transmit clock
1 2 3 4 5 6 7 8

Serial output
LSB MSB
data

Serial input
data latch
timing

Figure 35 Serial Interface Timing

44

,
State

MCU reset
STS wait state

Port selection
Transmit clock
wait state
Transfer state
HD404318 Series
Transmit clock
wait state
STS wait state

!"
PMRA write
External clock selection Dummy write for
state transition
SMR write
Output level control in Output level control in
idle states idle states
PMRC write
Data write for transmission
SRL, SRU
write

STS
instruction
SCK pin
(input)

SO pin Undefined LSB MSB

IFS

External clock mode Flag reset at transfer completion

Transmit clock
wait state
State STS wait state Transfer state STS wait state

MCU reset
Port selection

PMRA write
Internal clock selection

SMR write
Output level control in Output level control in
idle states idle states
PMRC write
Data write for transmission
SRL, SRU
write

STS
instruction
SCK pin
(output)

SO pin Undefined LSB MSB

IFS

Flag reset at transfer completion

Internal clock mode

Figure 36 Example of Serial Interface Operation Sequence

45


HD404318 Series
Transmit clock erors are detected as illustrated in figure 37.

Transfer completion
(IFS ← 1)

Interrupts inhibited

IFS ← 0

SMR write

Yes Transmit clock

IFS = 1 error processing

No

Normal
termination

Transmit clock error detection flowchart

Transmit clock Transmit clock wait state

wait state Transfer state Transfer state
State

SCK pin (input)

Noise

1 2 3 4 5 6 7 8
Transfer state has been
entered by the transmit
clock error. When SMR
is written, IFS is set.
SMR write

IFS
Flag set because octal
counter reaches 000. Flag reset at
transfer completion.
Transmit clock error detection procedure

Figure 37 Transmit Clock Error Detection

46
 HD404318 Series
Table 11 Transmit Clock Selection

PMRC SMR
Bit 0 Bit 2 Bit 1 Bit 0 System Clock Divisor Transmit Clock Frequency
0 0 0 0 ÷ 2048 4096t cyc
1 ÷ 512 1024t cyc
1 0 ÷ 128 256t cyc
1 ÷ 32 64t cyc
1 0 0 ÷8 16t cyc
1 ÷2 4t cyc
1 0 0 0 ÷ 4096 8192t cyc
1 ÷ 1024 2048t cyc
1 0 ÷ 256 512t cyc
1 ÷ 64 128t cyc
1 0 0 ÷ 16 32t cyc
1 ÷4 8t cyc

Serial mode register (SMR: $005)

Bit 3 2 1 0
Initial value 0 0 0 0
Read/Write W W W W
Bit name SMR3 SMR2 SMR1 SMR0

R00/SCK Prescaler
SMR3 Mode Selection SMR2 SMR1 SMR0 SCK Clock Source Division Ratio
0 R00 0 0 0 Output Prescaler Refer to
table 11
1 SCK 1

1 0
1
1 0 0
1

1 0 Output System clock —

1 Input External clock —

Figure 38 Serial Mode Register (SMR)

47
HD404318 Series

Port mode register C (PMRC: $025)

Bit 3 2 1 0
Initial value 0 0 Undefined 0
Read/Write W W W W
Bit name PMRC3 PMRC2 PMRC1 PMRC0

PMRC0 Serial Clock Division Ratio

Alarm output function.
Refer to table 9. 0 Prescaler output divided by 2
1 Prescaler output divided by 4

PMRC1 Output Level Control in Idle States

0 Low level
1 High level

Figure 39 Port Mode Register C (PMRC)

48
 HD404318 Series

A/D Converter

The MCU also contains a built-in A/D converter that uses a sequential comparison method with a
resistance ladder. It can perform digital conversion of eight analog inputs with 8-bit resolution. The
following describes the A/D converter.

• A/D mode register 1 (AMR1: $019) is used to select digital or analog ports
• A/D mode register 2 (AMR2: $01A) is used to set the A/D conversion speed and to select digital or
analog ports
• The A/D channel register (ACR: $016) is used to select an analog input channel
• A/D conversion is started by setting the A/D start flag (ADSF: $020, 2) to 1. After the conversion is
completed, converted data is stored in the A/D data register, and at the same time, the A/D start flag is
cleared to 0
• By setting the IAD off flag (IAOF: $021, 2) to 1, the current flowing through the resistance ladder can be
cut off even while operating in standby or active mode

4
A/D interrupt A/D mode
request flag register 1
(IFAD) (AMR1)

3 A/D mode
register 2
(AMR2)
AN0
AN1

Internal data bus

AN2 A/D data
Selector

AN3 Encoder register

AN4 (ADRU, L)
AN5
AN6
AN7 +
Comp
– A/D A/D channel
controller Control signal register (ACR)
for conversion
time
AVCC
A/D start flag IAD off flag
(ADSF) (IAOF)
AVSS
D/A
Operating mode signal (1 in stop mode)

Figure 40 A/D Converter Block Diagram

49
HD404318 Series
Notes on Usage

• Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF)
• Do not write to the A/D start flag during A/D conversion
• Data in the A/D data register during A/D conversion is undefined
• Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D
converter does not operate in stop mode. In addition, to save power while in stop mode, all current
flowing through the converter’s resistance ladder is cut off.
• If the power supply for the A/D converter is to be different from VCC, connect a 0.1-µF bypass capacitor
between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly
connected to the VCC pin.)
• The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected
as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC. When using a
shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by
MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode register as an analog pin will remain
pulled up.

A/D mode register 1 (AMR1: $019)

Bit 3 2 1 0
Initial value 0 0 0 0
Read/Write W W W W
Bit name AMR13 AMR12 AMR11 AMR10

AMR10 R30/AN0 Mode Selection

0 R30
AMR12 R32/AN2 Mode Selection
1 AN0
0 R32
1 AN2 AMR11 R31/AN1 Mode Selection
0 R31
AMR13 R33/AN3 Mode Selection
1 AN1
0 R33
1 AN3

Figure 41 A/D Mode Register 1 (AMR1)

50
 HD404318 Series

A/D mode register 2 (AMR2: $01A)

Bit 3 2 1 0
Initial value — — 0 0
Read/Write — — W W
Bit name Not used Not used AMR21 AMR20

AMR20 Conversion Time

0 34tcyc
1 67tcyc

AMR21 R4/AN4–AN7 Pin Selection

0 R4
1 AN4–AN7

Figure 42 A/D Mode Register (AMR2)

A/D channel register (ACR: $016)

Bit 3 2 1 0
Initial value — 0 0 0
Read/Write — W W W
Bit name Not used ACR2 ACR1 ACR0

ACR2 ACR1 ACR0 Analog Input Selection

0 0 0 AN0
1 AN1
1 0 AN2
1 AN3
1 0 0 AN4
1 AN5
1 0 AN6
1 AN7

Figure 43 A/D Channel Register (ACR)

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HD404318 Series

A/D start flag (ADSF: $020, bit 2)

Bit 3 2 1 0
Initial value — 0 0 —
Read/Write — R/W W —
Bit name Not used ADSF WDON Not used

A/D Start Flag (ADSF) WDON

0 A/D conversion completed Refer to the description of timers

1 A/D conversion started

Figure 44 A/D Start Flag (ADSF)

IAD off flag (IAOF: $021, bit 2)

Bit 3 2 1 0
Initial value 0 0 0 0
Read/Write R/W R/W R/W R/W
Bit name RAME IAOF ICEF ICSF

IAD Off Flag (IAOF) ICSF

0 IAD current flows Refer to the description of timers

1 IAD current is cut off

ICEF
RAME
Refer to the description of timers
Refer to the description of operating
modes

Figure 45 IAD Off Flag (IAOF)

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 HD404318 Series

ADRU: $018 ADRL: $017

3 2 1 0 3 2 1 0

MSB LSB RESULT

bit 7 bit 0

Figure 46 A/D Data Registers

A/D data register (lower digit) (ADRL: $017)

Bit 3 2 1 0
Initial value 0 0 0 0
Read/Write R R R R
Bit name ADRL3 ADRL2 ADRL1 ADRL0

Figure 47 A/D Data Register Lower Digit (ADRL)

A/D data register (upper digit) (ADRU: $018)

Bit 3 2 1 0
Initial value 1 0 0 0
Read/Write R R R R
Bit name ADRU3 ADRU2 ADRU1 ADRU0

Figure 48 A/D Data Register Upper Digit (ADRU)

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HD404318 Series

Notes on Mounting

Assemble all parts including the HD404318 Series on a board, noting the points described below.

1. Connect layered ceramic type capacitors (about 0.1 µF) between AVCC and AVSS , between VCC and
GND, and between used analog pins and AVSS .
2. Connect unused analog pins to AVSS .

1. When not using an A/D converter.

VCC AVCC
AN 0
AN 1
0.1 µF
to
AN 7
GND AVSS

2. When using pins AN 0 and AN 1 but not using AN 2 to AN 7 .

VCC AVCC
AN 0
AN 1
AN 2 to
AN 7
GND AVSS

0.1 µF × 3

3. When using all analog pins.

VCC AVCC
AN 0
AN 1
AN 2 to
AN 7

GND AVSS

0.1 µF × 9

Figure 49 Example of Connections (1)

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 HD404318 Series
Between the VCC and GND lines, connect capacitors designed for use in ordinary power supply circuits.
An example connection is described in figure 50.

No resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in
parallel. The capacitors are a large capacitance C1 and a small capacitance C2.

VCC VCC

C1 C2

GND GND

Figure 50 Example of Connections (2)

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HD404318 Series
Absolute Maximum Ratings
Item Symbol Value Unit Notes
Supply voltage VCC –0.3 to +7.0 V
Programming voltage VPP –0.3 to +14.0 V 1
Pin voltage VT –0.3 to VCC + 0.3 V 2
VCC – 45 to V 3
VCC + 0.3
Total permissible input current ∑IO 70 mA 4
Total permissible output current –∑IO 150 mA 5
Maximum input current IO 4 mA 6, 7
20 mA 6, 8
Maximum output current –I O 4 mA 9, 10
30 mA 10, 11
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +125 °C
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation
must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.
1. Applies to pin TEST (VPP ) of HD4074318.
2. Applies to all standard voltage pins.
3. Applies to high-voltage pins.
4. The total permissible input current is the total of input currents simultaneously flowing in from all
the I/O pins to GND.
5. The total permissible output current is the total of output currents simultaneously flowing out from
VCC to all I/O pins.
6. The maximum input current is the maximum current flowing from each I/O pin to GND.
7. Applies to ports R3 and R4.
8. Applies to port R0.
9. Applies to ports R0, R3, and R4.
10. The maximum output current is the maximum current flowing from V CC to each I/O pin.
11. Applies to ports D0–D 8, R1, R2, and R8.

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 HD404318 Series
Electrical Characteristics

DC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VC C, T a = –20 to +75°C,

unless otherwise specified)

Item Symbol Pins Min Typ Max Unit Test Condition Notes
Input high VIH RESET, SCK, 0.8V CC — VCC + 0.3 V
voltage SI, INT0, INT1,
STOPC, EVNB
OSC 1 VCC – 0.5 — VCC + 0.3 V
Input low voltage VIL RESET, SCK, –0.3 — 0.2V CC V
SI
INT0, INT1, VCC – 40 — 0.2V CC V
STOPC, EVNB
OSC 1 –0.3 — 0.5 V
Output high VOH SCK, SO, TOC VCC – 0.5 — — V –I OH = 0.5 mA
voltage
Output low VOL SCK, SO, TOC — — 0.4 V I OL = 0.4 mA
voltage
I/O leakage |IIL| RESET, SCK, — — 1 µA Vin = 0 V to VCC 1
current SI, SO, TOC,
OSC 1
INT0, INT1, — — 20 µA Vin = VCC – 40 to VCC 1
STOPC, EVNB
Current I CC VCC — — 5.0 mA VCC = 5 V, 2, 5
dissipation in f OSC = 4 MHz
active mode
— — 8.0 mA 2, 6
Current I SBY VCC — — 2.0 mA VCC = 5 V, 3
dissipation in f OSC = 4 MHz
standby mode
Current I STOP VCC — — 10 µA VCC = 5 V 4, 5
dissipation in
stop mode
— — 20 µA 4, 6
Stop mode VSTOP VCC 2 — — V
retaining voltage
Notes: 1. Excludes current flowing through pull-up MOS and output buffers.
2. I CC is the source current when no I/O current is flowing while the MCU is in reset state.
Test conditions: MCU: Reset
Pins: RESET, TEST at GND
R0, R3, R4 at VCC
D0–D 8, R1, R2, R8, RA1 at V disp

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HD404318 Series
3. I SBY is the source current when no I/O current is flowing while the MCU timer is operating.
Test conditions: MCU: I/O reset
Standby mode
Pins: RESET at V CC
TEST at GND
R0, R3, R4 at VCC
D0–D 8, R1, R2, R8, RA1 at V disp
4. This is the source current when no I/O current is flowing.
Test conditions: Pins: R0, R3, R4 at VCC
D0–D 8, R1, R2, R8, RA1 at GND
5. Applies to the HD404314, HD404316 and HD404318.
6. Applies to the HD4074318.

I/O Characteristics for Standard Pins (V CC = 4.0 to 5.5 V, GND = 0 V, V disp = V CC – 40 V to VCC, Ta =
–20 to +75°C, unless otherwise specified)

Item Symbol Pins Min Typ Max Unit Test Condition Note
Input high VIH R0, R3, R4 0.7V CC — VCC + 0.3 V
voltage
Input low voltage VIL R0, R3, R4 –0.3 — 0.3V CC V
Output high VOH R0, R3, R4 VCC – 0.5 — — V –I OH = 0.5 mA
voltage
Output low VOL R3, R4 — — 0.4 V I OL = 1.6 mA
voltage
R0 — — 2.0 V I OL = 10 mA
Input leakage |IIL| R0, R3, R4 — — 1 µA Vin = 0 V to VCC 1
current
Pull-up MOS –I PU R0, R3, R4 30 150 300 µA VCC = 5 V, Vin = 0 V 2
30 80 180 µA 3
Notes: 1. Output buffer current is excluded.
2. Applies to the HD404314, HD404316, and HD404318.
3. Applies to the HD4074318.

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 HD404318 Series
I/O Characteristics for High-Voltage Pins (V CC = 4.0 to 5.5 V, GND = 0 V, Vdisp = V CC – 40 V to VCC,
T a = –20 to +75°C, unless otherwise specified)

Item Symbol Pins Min Typ Max Unit Test Condition Note
Input high VIH D0–D 8, R1, 0.7V CC — VCC + 0.3 V
voltage R2, R8, RA 1
Input low VIL D0–D 8, R1, VCC – 40 — 0.3V CC V
voltage R2, R8, RA 1
Output high VOH D0–D 8, R1, VCC – 3.0 — — V –I OH = 15 mA
voltage R2, R8, BUZZ
VCC – 2.0 — — V –I OH = 10 mA
VCC – 1.0 — — V –I OH = 4 mA
Output low VOL D0–D 8, R1, — — VCC – 37 V Vdisp = VCC – 40 V 1
voltage R2, R8, BUZZ
— — VCC – 37 V 150 kΩ at VCC – 40 V 2
I/O leakage |IIL| D0–D 8, R1, R2, — — 20 µA Vin = VCC – 40 V to VCC 3
current R8, RA1, BUZZ
Pull-down I PD D0–D 8, R1, 200 600 1000 µA Vdisp = VCC – 35 V, 1
MOS current R2, R8, BUZZ Vin = VCC
Notes: 1. Applies to pins with pull-down MOS as selected by the mask option .
2. Applies to pins without pull-down MOS as selected by the mask option.
3. Excludes output buffer current.

A/D Converter Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = V CC – 40 V to VCC, Ta = –20 to
+75°C, unless otherwise specified)

Item Symbol Pins Min Typ Max Unit Test Condition Note
Analog supply voltage AVCC AVCC VCC – 0.3 VCC VCC + 0.3 V 1
Analog input voltage AVin AN 0–AN 7 AVSS — AVCC V
Current flowing I AD — — 200 µA VCC = AVCC = 5.0 V
between AV CC and AVSS
Analog input CA in AN 0–AN 7 — — 30 pF
capacitance
Resolution 8 8 8 Bit
Number of input 0 — 8 Chan
channels nel
Absolute accuracy — — ±2.0 LSB
Conversion time 34 — 67 t cyc
Input impedance AN 0–AN 7 1 — — MΩ
Note: 1. Connect this to V CC if the A/D converter is not used.

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HD404318 Series
AC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, V disp = VCC – 40 V to VCC, T a = –20 to +75°C)

Item Symbol Pins Min Typ Max Unit Test Condition Note
Clock oscillation f OSC OSC 1, OSC 2 0.4 4 4.5 MHz System clock
frequency divided by 4
Instruction cycle time t cyc 0.89 1 10 µs
Oscillation stabilization t RC OSC 1, OSC 2 — — 7.5 ms 1
time (ceramic oscillator)
Oscillation stabilization t RC OSC 1, OSC 2 — — 40 ms 1
time (crystal oscillator)
External clock high width t CPH OSC 1 92 — — ns 2
External clock low width t CPL OSC 1 92 — — ns 2
External clock rise time t CPr OSC 1 — — 20 ns 2
External clock fall time t CPf OSC 1 — — 20 ns 2
INT0, INT1, EVNB high t IH INT0, INT1, 2 — — t cyc 3
widths EVNB
INT0, INT1, EVNB low t IL INT0, INT1, 2 — — t cyc 3
widths EVNB
RESET low width t RSTL RESET 2 — — t cyc 4
STOPC low width t STPL STOPC 1 — — t RC 5
RESET rise time t RSTr RESET — — 20 ms 4
STOPC rise time t STPr STOPC — — 20 ms 5
Input capacitance Cin All input pins — — 30 pF f = 1 MHz, Vin = 0 V
except TEST
TEST — — 30 pF 6
— — 180 pF 7
Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the
following situations:
a. After V CC reaches 4.0 V at power-on.
b. After RESET input goes low when stop mode is cancelled.
c. After STOPC input goes low when stop mode is cancelled.
To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET
or STOPC must be input for at least a duration of t RC.
When using a crystal or ceramic oscillator, consult with the manufacturer to determine what
stabilization time is required, since it will depend on the circuit constants and stray capacitance.
2. Refer to figure 51.
3. Refer to figure 52.
4. Refer to figure 53.
5. Refer to figure 54.
6. Applies to the HD404314, HD404316, and HD404318.
7. Applies to the HD4074318.

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 HD404318 Series
Serial Interface Timing Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, V disp = VCC – 40 V to VCC, T a =
–20 to +75°C, unless otherwise specified)

During Transmit Clock Output

Item Symbol Pins Min Typ Max Unit Test Condition Note
Transmit clock cycle time t Scyc SCK 1 — — t cyc Load shown in figure 56 1
Transmit clock high width t SCKH SCK 0.4 — — t Scyc Load shown in figure 56 1
Transmit clock low width t SCKL SCK 0.4 — — t Scyc Load shown in figure 56 1
Transmit clock rise time t SCKr SCK — — 80 ns Load shown in figure 56 1
Transmit clock fall time t SCKf SCK — — 80 ns Load shown in figure 56 1
Serial output data delay t DSO SO — — 300 ns Load shown in figure 56 1
time
Serial input data setup t SSI SI 100 — — ns 1
time
Serial input data hold time t HSI SI 200 — — ns 1

During Transmit Clock Input

Item Symbol Pins Min Typ Max Unit Test Condition Note
Transmit clock cycle time t Scyc SCK 1 — — t cyc 1
Transmit clock high width t SCKH SCK 0.4 — — t Scyc 1
Transmit clock low width t SCKL SCK 0.4 — — t Scyc 1
Transmit clock rise time t SCKr SCK — — 80 ns 1
Transmit clock fall time t SCKf SCK — — 80 ns 1
Serial output data delay t DSO SO — — 300 ns Load shown in figure 56 1
time
Serial input data setup t SSI SI 100 — — ns 1
time
Serial input data hold time t HSI SI 200 — — ns 1
Note: 1. Refer to figure 55.

OSC1
1/fCP

VCC – 0.5 V
tCPH tCPL
0.5 V

tCPr tCPf

Figure 51 External Clock Timing

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HD404318 Series

INT0, INT1, EVNB

0.8VCC
tIH tIL
0.2VCC

Figure 52 Interrupt Timing

RESET

0.8VCC
tRSTL
0.2VCC

tRSTr

Figure 53 RESET Timing

STOPC

0.8VCC
tSTPL
0.2VCC

tSTPr

Figure 54 STOPC Timing

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 HD404318 Series

t Scyc

t SCKf t SCKr
SCK VCC – 2.0 V (0.8VCC )* t SCKL
0.8 V (0.2VCC)* t SCKH
t DSO
VCC – 2.0 V
SO
0.8 V
t SSI t HSI

0.8V CC
SI 0.2VCC

Note: *VCC-2.0V and 0.8V are the threshold voltages for transmit clock output.
0.8V CC and 0.2VCC are the threshold voltages for transmit clock input.

Figure 55 Serial Interface Timing

VCC

RL = 2.6 kΩ
Test
point
C= R= Hitachi
30 pF 12 kΩ 1S2074
or equivalent

Figure 56 Timing Load Circuit

63
HD404318 Series

Notes on ROM Out

Please pay attention to the following items regarding ROM out.

On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404314 and
HD404316 as an 8-kword version

(HD404318). An 8-kword data size is required to change ROM data to mask manufacturing data since the
program used is for an 8-kword version.

This limitation applies when using an EPROM or a data base.

ROM 4-kword version: ROM 6-kword version:

HD404314 HD404316
Address $1000–$1FFF Address $1800–$1FFF

$0000 $0000

Vector address Vector address

$000F $000F
$0010 $0010
Zero-page subroutine Zero-page subroutine
(64 words) (64 words)

$003F $003F
$0040 $0040
Pattern & program Pattern & program
(4,096 words) (6,144 words)
$0FFF $17FF
$1000 $1800

Not used Not used

$1FFF $1FFF

Fill this area with 1s

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 HD404318 Series

HD404314/HD404316/HD404318 Option List

Please check off the appropriate applications and enter the necessary information.

Date of order
Customer
1. ROM Size Department
HD404314 4-kword Name
HD404316 6-kword ROM code name
HD404318 8-kword LSI number
2. I/O Options
D: Without pull-down resistance E: With pull-down resistance
I/O option I/O option
Pin name I/O Pin name I/O
D E D E
D0/INT0 I/O R1 R10 I/O
D1/INT1 I/O R11 I/O
D2/EVNB I/O R12 I/O
D3/BUZZ I/O R13 I/O
D4/STOPC I/O R2 R20 I/O
D5 I/O R21 I/O
D6 I/O R22 I/O
D7 I/O R23 I/O
D8 I/O R8 R80 I/O
R81 I/O
R82 I/O
R83 I/O
3. RA1/Vdisp RA RA1 I Selected in option (3)

RA1 without pull-down resistance

Vdisp
Note: If even only one pin is selected with I/O option
E, pin RA1/Vdisp must be selected to function
as Vdisp.
4. ROM Code Media
Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTAT™ version).

EPROM: The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
programmed to different EPROMS.

5. System Oscillator for OSC1 and OSC2 6. Stop mode 7. Package

Ceramic oscillator f= MHz Used DP-42S

Crystal oscillator f= MHz Not used FP-44A
External clock f= MHz

65
HD404318 Series

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.

Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.

66