German University in Cairo

Media Engineering and Technology

Assoc. Prof. Dr. Hassan Soubra

Computer System Architecture, Spring Semester 2021

Practice Assignment 1
Discussion: 27/03/2021 - 01/04/2021

Exercise 1-1
The number of embedded processors sold every year greatly outnumbers the number of PC and even
PostPC processors. Can you confirm or deny this insight based on your own experience? Try to count
the number of embedded processors in your home. How does it compare with the number of conventional
computers in your home?

Solution:
Debate. No correct answer.

Exercise 1-2
Explain the “Power Wall” in the context of microprocessors. What is the main cause of it?

Solution:
The “Power Wall” refers to the difficulty of scaling the performance of computing chips and systems at
historical levels, because of fundamental constraints imposed by affordable power delivery and dissipation.
The main cause that led to it is high processor frequencies!

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Exercise 1-3
For CMOS chips, the traditional primary energy consumption has been in switching transistors, also
called dynamic energy. The energy required per transistor is proportional to the product of the capacitive
load driven by the transistor and the square of the voltage. The following equation represents the energy
of pulse of the ‘double’ logic transition of 0→1→0 or 1→0→1:

Energy ∝ Capacitive load * Voltage2

∝: This symbol means that the terms on each side are proportional to each other.

a) What do you think the energy of a single transition (0→1 or 1→0) would be?
b) Deduce the formula of the power required per transistor?
c) For a fixed task, slowing clock rate reduces power, energy or both? Explain.
d) Name the one element that would greatly reduce power and energy if lowered?
e) Some microprocessors today are designed to have adjustable voltage, so a 15% reduction in voltage
may result in a 15% reduction in frequency. What would be the impact on dynamic energy and on
dynamic power?

Solution:

a) 0.5 * (Capacitive load * Voltage2 )

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 b) Power ∝ 0.5 * (Capacitive load * Voltage2 ) * Frequency
c) Slowing clock rate reduces power, but not energy.
d) Voltage.
e) Because the capacitance is unchanged, the answer for energy is the ratio of the voltages:

Energy(new) (V oltage∗0.85)2
Energy(old) = V oltage2 = 0.852 = 0.72

P ower(new)
P ower(old) = 0.72 * F requency∗0.85
F requency = 0.61

So this shrinks power to about 61% of the original.

Exercise 1-4
Voltages have dropped from 5V to just under 1V in 20 years. Could we make it drop lower? Why or why
not? What is at stake?

Solution:
In digital systems we come across only binary values either 1 or 0. Historically we have values not far
from 5V to represent a ‘1’ and values not far from 0V to represent ‘0’. For example:

So with with 5V the threshold was clear and there’s a good decision gap between the two logical values.
However, digital pulses need not have only 5V and 0V to represent logic 1 and logic 0. Because of the
obvious power reduction issue.
Recent technologies have chosen 0.7V to 0.9V for logic ‘1’ and 0V to 0.1V for logic ‘0’. Only problem is
signal integrity. As long as it is met, no problem in absolute values. If we shrink voltage more, discerning
the logical values will be very hard if not impossible and it will be prone to errors. A logical ‘0’ might
get mistaken for a ‘1’ and vice versa.

Exercise 1-5
Do the following changes to a computer system increase throughput, decrease response time, or both?

• Replacing the processor in a computer with a faster version

• Adding additional processors to a system that uses multiple processors for separate tasks for exam-
ple, searching the web

Solution:
Decreasing the response time almost always improves throughput. Hence, in case 1, both response time
and throughput are improved. In case 2, no one task gets work done faster, so only throughput increases.

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Exercise 1-6
If computer A runs a program in 10 seconds and computer B runs the same program in 15 seconds, how
much faster is A than B?

Solution:
A is 1.5 times as fast as B.

Exercise 1-7
Our favorite program runs in 10 seconds on computer A, which has a 2 GHz clock. We are trying to help
a computer designer build a computer, B, which will run this program in 6 seconds. The designer has
determined that a substantial increase in the clock rate is possible, but this increase will affect the rest
of the CPU design, causing computer B to require 1.2 times as many clock cycles as computer A for this
program. What clock rate should we tell the designer to target?

Solution:
Let’s first find the number of clock cycles required for the program on A:
CPU time A = CPU Clock cycles A * ( 1 / Clock Rate A).
10 seconds = CPU clock cycles A * 1 / (2*109 cycles per second)
CPU clock cycles A = 10 seconds * (2*109 cycles per second) = 20*109 cycles
CPU time for B = (1.2 * CPU clock cycles A ) / Clock Rate B.
Clock Rate B= 4 GHz.

Exercise 1-8
Comparing Code Segments A compiler designer is trying to decide between two code sequences for a
particular computer. The hardware designers have supplied the following facts: CPI for each instruction
class
A B C
CPI 1 2 3
For a particular high-level language statement, the compiler writer is considering two code sequences that
require the following instruction counts: Instruction counts for each instruction class
Code sequence A B C
1 2 1 2
2 4 1 1
Which code sequence executes the most instructions? Which will be faster? What is the CPI for each
sequence?

Solution:
Sequence 1 executes 2 + 1 + 2 = 5 instructions.
Sequence 2 executes 4 + 1+1 = 6 instructions.
Therefore, sequence 1 executes fewer instructions.

We can use the equation for CPU clock cycles based on instruction count and CPI to find the total
number of clock cycles for each sequence:

CPU clock cycles =

P
(CP Ii ∗ Ci)

This yields:
CPU clock cycles1 = 10 cycles
CPU clock cycles2 = 9 cycles

So code sequence 2 is faster, even though it executes one extra instruction. Since code sequence 2 takes
fewer overall clock cycles but has more instructions, it must have a lower CPI.

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The CPI values can be computed by:

CPI = CPU clock cycles / Instruction count

CPI1 = 2
CPI2 =1.5

Exercise 1-9
A given application written in Java runs 15 seconds on a desktop processor. A new Java compiler is
released that requires only 0.6 as many instructions as the old compiler. Unfortunately, it increases the
CPI by 1.1. How fast can we expect the application to run using this new compiler?

Solution:
15 * 0.6 * 1.1 = 9.9 seconds