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Ejercicio 3 Sumador Con Signo VHDL
Ejercicio 3 Sumador Con Signo VHDL
entity adder is
generic(N: natural:=8);
port(
x0 : in std_logic_vector(N-1 downto 0);
x1 : in std_logic_vector(N-1 downto 0);
y : out std_logic_vector(N-1 downto 0);
);
end adder;
architecture arq_sum of adder is
begin
y<= std_logic_vector(unsigned(x0)+unsigned(x1));
end arq_sum;