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  • Ejercicio Sumador Con Signo VHDL

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    Alex Santana
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    This document describes a generic N-bit signed adder. It defines an adder entity with generic bit width N and input ports for two N-bit operands. The architecture performs an unsigned addition of the two operands and assigns the result to the output port.

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    Ejercicio Sumador Con Signo Vhdl

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    This document describes a generic N-bit signed adder. It defines an adder entity with generic bit width N and input ports for two N-bit operands. The architecture performs an unsigned addition of the two operands and assigns the result to the output port.

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    © All Rights Reserved
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    10 views1 page

    Ejercicio Sumador Con Signo VHDL

    Uploaded by

    Alex Santana
    This document describes a generic N-bit signed adder. It defines an adder entity with generic bit width N and input ports for two N-bit operands. The architecture performs an unsigned addition of the two operands and assigns the result to the output port.

    Copyright:

    © All Rights Reserved
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    \outl0\strokewidth0 \strokec2 SUMADOR CON SIGNO:\
    --UN SUMADOR CON SIGNO GENERICO DE N-BITS\
    library ieee;\
    use ieee.std_logic_1164.all;\
    use ieee.numeric_std.all;\
    \
    \
    entity adder is\
    generic(N: natural:=8);\
    port(\
    x0 : in std_logic_vector(N-1 downto 0);\
    x1 : in std_logic_vector(N-1 downto 0);\
    y : out std_logic_vector(N-1 downto 0);\
    );\
    end adder;\
    architecture arq_sum of adder is\
    begin\
    y<= std_logic_vector(unsigned(x0)+unsigned(x1));\
    end arq_sum;}

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