l2 22.07

+--------------------------------------------------------------------+
� � MobaXterm 20.5 � �
� (SSH client, X-server and networking tools) �
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� ? SSH session to root@192.168.1.100 �
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+--------------------------------------------------------------------+
root@oct3032:~# cd kannan/Config_FDD
root@oct3032:~/kannan/Config_FDD# cd /home/root/sumanth/Config_FDD/
root@oct3032:~/sumanth/Config_FDD# ./init.sh
kernel.core_pattern = /home/root/%e_core_dump_sumanth.%p
./l2pid 1508's current affinity mask: f
pid 1508's new affinity mask: 8
root@oct3032:~/sumanth/Config_FDD# ./l2x86
_INIT_ Command echo 0xff > /proc/1658/coredump_filter executed
sh: /proc/irq/32/smp_affinity: No such file or directory
chrt: failed to get pid 99's policy: No such process
pid 8's current affinity mask: 1
[14:42:39:855382] [Warning] Could not read initialization file 'l2.ini'. Using
default values
READING SHARED_MEM_PTR = 29da6000
----------FX-SHARED-MEMORY-BASE_ADDRESS = 0x29da6000 -----------------
[14:42:39:856228] [Info] Using system memory
[14:42:39:857872] [Init]
SBPRINTER_Create................................................................
[OK]
[SBQUEUE_OpenAndReset] opening port name: /config_path_l3_to_l2
[14:42:39:858366] [Debug] [SBHA_RegisterQueue] Registered queue descriptor 4 of
type 2
[SBQUEUE_OpenAndReset] opening port name: /data_path_l3_to_l2_up
[14:42:39:858412] [Debug] [__CreateMailbox] Creating Posix
queue[/config_path_l3_to_l2] at port 0 with 512 buckets of size 8 bytes
type 2
[SBQUEUE_OpenAndReset] opening port name: /data_path_l3_to_l2_cp
queue[/data_path_l3_to_l2_up] at port 1 with 500 buckets of size 8 bytes
[SBQUEUE_OpenAndReset] opening port name: /config_path_l2_to_l3
type 2
queue[/data_path_l3_to_l2_cp] at port 2 with 10 buckets of size 8 bytes
type 2
queue[/config_path_l2_to_l3] at port 3 with 10 buckets of size 8 bytes
[SBQUEUE_OpenAndReset] opening port name: /events_l2_to_l3
[SBQUEUE_OpenAndReset] opening port name: /data_path_l2_to_l3_up
type 2
queue[/events_l2_to_l3] at port 4 with 10 buckets of size 8 bytes
[SBQUEUE_OpenAndReset] opening port name: /data_path_l2_to_l3_cp
type 2
queue[/data_path_l2_to_l3_up] at port 5 with 500 buckets of size 8 bytes
type 2
queue[/data_path_l2_to_l3_cp] at port 6 with 10 buckets of size 8 bytes
[SBQUEUE_OpenAndReset] opening port name: /events_from_kpia_to_l2
[SBQUEUE_OpenAndReset] opening port name: /data_from_l2_to_kpia
type 2
queue[/events_from_kpia_to_l2] at port 7 with 10 buckets of size 8 bytes
[SBQUEUE_OpenAndReset] opening port name: /rrc2s1ap_cp
type 2
queue[/data_from_l2_to_kpia] at port 8 with 10 buckets of size 8 bytes
type 2
[SBQUEUE_OpenAndReset] opening port name: /rrc2x2ap_cp
[14:42:39:860273] [Debug] [__CreateMailbox] Creating Posix Queue[/rrc2s1ap_cp]
at port 11 with size 2600 bytes
type 2
[SBQUEUE_OpenAndReset] opening port name: /s1ap2x2ap_cp
[14:42:39:860504] [Debug] [__CreateMailbox] Creating Posix Queue[/rrc2x2ap_cp]
[SBQUEUE_OpenAndReset] opening port name: /x2ap2s1ap_cp
type 2
[14:42:39:860730] [Debug] [__CreateMailbox] Creating Posix Queue[/s1ap2x2ap_cp]
type 2
[SBQUEUE_OpenAndReset] opening port name: /x2ap2rrc_cp
[14:42:39:860905] [Debug] [__CreateMailbox] Creating Posix Queue[/x2ap2s1ap_cp]
[SBQUEUE_OpenAndReset] opening port name: /s1ap2rrc_cp
type 2
[14:42:39:861113] [Debug] [__CreateMailbox] Creating Posix Queue[/x2ap2rrc_cp]
[SBQUEUE_OpenAndReset] opening port name: /events_from_kpia_to_l3
type 2
[14:42:39:861315] [Debug] [__CreateMailbox] Creating Posix Queue[/s1ap2rrc_cp]
type 2
[SBQUEUE_OpenAndReset] opening port name: /data_from_l3_to_kpia
Queue[/events_from_kpia_to_l3] at port 17 with size 2600 bytes
[SBQUEUE_OpenAndReset] opening port name: /son_to_l3
type 2
Queue[/data_from_l3_to_kpia] at port 18 with size 2600 bytes
[SBQUEUE_OpenAndReset] opening port name: /l3_to_son
type 2
[14:42:39:862057] [Debug] [__CreateMailbox] Creating Posix Queue[/son_to_l3] at
port 19 with size 4096 bytes
type 2
[14:42:39:862288] [Debug] [__CreateMailbox] Creating Posix Queue[/l3_to_son] at
port 20 with size 4096 bytes
[14:42:39:862420] [OK] L2 KPI Module
[14:42:39:862469] [OK] L2 KPI Module Job System Utilization
[14:42:39:862546] [Init] L2 KPI Module Alarms
Data.......................................................[OK]
[14:42:39:862491] [OK] L2 KPI Module Job Integrity
[14:42:39:862498] [OK] L2 KPI Module Job Low Latency
[14:42:39:863120] [OK] RNTI Manager Created
[14:42:39:868320] [Init] [RLC] Entity Manager
created....................................................[OK]
[14:42:39:868404] [Init] [RLC] Buffers Manager
created...................................................[OK]
[14:42:39:868603] [Init] RLC Timer handler thread
started................................................[OK]
[14:42:39:870190] [OK] [MAC] Disassembler start
[14:42:39:870602] [OK] SubFrame Manager Component
[14:42:39:874530] [OK] Spectrum Allocation Manager
type 2
[14:42:39:874748] [OK] [L2] L2 Manager
[14:42:39:874970] [OK] [L2] incoming_l2_from_l3_thread
type 2
[14:42:39:875332] [OK] incoming_l2_from_kpi_agent_thread
[14:42:45:889617] [Warning] MAC_ConfigureCell MsgType = 26
rbg_map_init_mask[0]
[14:42:45:889661] [OK] MAC_Cell_Manager: default_OFDM_symbol=1
rbg_map_init_mask[0]
[14:42:45:889964] [OK] Configured per UE: max_rb_ul=50, max_rb_dl=50,
max_tbsi=25
[14:42:45:890036] [OK] Allowed per UE: max_rb_ul=50, max_rb_dl=50,
max_tbsi=25
Socket opened for port = 50002 , Socket-FD = 29
Socket opened for port = 50004 , Socket-FD = 30
[14:42:45:891809] [Init] [PDCP] Layer
started............................................................[OK]
[14:42:45:892102] [Init] [RLC] Layer
started.............................................................[OK]
[14:42:45:892874] [Info] [MAC]MAC_SubframeManager_Start ....
[14:42:45:893072] [OK] [MAC] Layer started
[14:42:45:893094] [OK] HAL_InitPhy called
[14:42:45:893102] [OK] HAL_RegisterCbRach called
[14:42:45:893125] [OK] HAL_RegisterCbHarqCrc called
[14:42:45:893131] [OK] HAL_RegisterCbUlsch called
[14:42:45:893144] [OK] HAL_ConfigurePHY called
[14:42:46:893213] [OK] HAL_StartPhy called
[14:42:46:893680] [OK] ====:OCT: ipLocalAddress(192.168.1.100)
[14:42:46:893747] [OK] [L1] Host MAC Address = 0x0:0xc:0x90:0xa0:0x1b:0x5c
[14:42:46:893759] [OK] [L1] Board MAC Address = 0xc:0x0:0x0:0x1:0xff:0xff
[14:42:46:893801] [OK] [L1] Tx Power/Rx Gain are: 0dbm, 56db,ADI Radio Reg
are: 0x0,0x38
[14:42:46:893815] [OK] [L1] BOARD DSP TYPE = 0 , Index i = 5
sh: /proc/irq/32/smp_affinity: No such file or directory
pid 8's current affinity mask: 1
[14:42:47:152364] [OK] buildAndSendPhyParamReq DL-ARFCN = 3100 & Bandwidth
= 3
[14:42:47:152430] [OK] Tx Attenuation = 0, Rx Gain = 56
HW RF Port{0} Antenna{0}: [TX Gain:0 dB]
HW RF Port{0} Antenna{0}: [TX Gain:0 dB]
HW RF Port{0} Antenna{0}: [RX Gain:56 dB]
HW RF Port{0} Antenna{0}: [RX Gain:56 dB]
[14:42:47:583262] [OK] lteEnodebConfig successful...
[14:42:47:583355] [OK] buildAndSendPhyParamReq sent...
[14:42:47:583662] [OK] ltePhyParamResponseHandler Error Code = 0 ,
NumofTlv = 6
[14:42:47:583706] [OK] ltePhyParamResponseHandler eFAPI_PHY_STATE = 0
[14:42:47:583714] [OK] ltePhyParamResponseHandler
eFAPI_DL_BANDWIDTH_SUPPORT = 63
eFAPI_UL_BANDWIDTH_SUPPORT = 63
eFAPI_DL_MODULATION_SUPPORT = 7
eFAPI_UL_MODULATION_SUPPORT = 7
eFAPI_PHY_ANTENNA_CAPABILITY = 1
[14:42:47:583793] [OK] buildAndSendPhyCellConfigReq sent...
[14:42:47:584137] [OK] ltePhyCellConfigResponseHandler Error Code = 0
[14:42:47:584147] [OK] ltePhyCellConfigResponseHandler
NumOfInvalidOrUnsupportedTLV = 0, NumOfMissingTLV = 0
[14:42:47:584180] [OK] [L1 ITF] buildAndSendPhyStartReq sent....
[14:42:47:584658] [Info] [MAC](SfManager) PHY has been started
GOOD_cqi[8]
GOOD_cqi[9]
GOOD_cqi[12]
GOOD_cqi[13]
GOOD_cqi[12]
GOOD_cqi[15]
GOOD_cqi[14]
GOOD_cqi[15]
Dl_Process RACH riv[450] rnti[61]
setting subband_bitmap in Rar Alloc [3]

best_cqi[15]
best_cqi[14]
best_cqi[15]
best_cqi[14]
best_cqi[15]
best_cqi[12]
best_cqi[13]
best_cqi[14]

avg_cqi[12]
avg_cqi[10]
avg_cqi[11]
avg_cqi[9]
avg_cqi[7]
avg_cqi[8]
avg_cqi[7]
avg_cqi[9]

better avg cqi[10]
better avg cqi[7]
better avg cqi[11]
better avg cqi[8]
better avg cqi[6]
better avg cqi[12]
better avg cqi[8]
better avg cqi[10]

GOOD_cqi[8]
GOOD_cqi[9]
GOOD_cqi[12]
GOOD_cqi[13]
GOOD_cqi[12]
GOOD_cqi[15]
GOOD_cqi[14]
GOOD_cqi[15]

best_cqi[15]
best_cqi[14]
best_cqi[15]
best_cqi[14]
best_cqi[15]
best_cqi[12]
best_cqi[13]
best_cqi[14]
for() cur_bit_idx [4] ,first_rb_index[24] last_rb_index[32] free_rbs[18]

required_rbs allocated rbs [0] < 0 sub_bitmap[48],no_rb[8],index[3]
error; gCntr[12861] max_req_rbs_ue < 1 , cntr[4],max_data_in_ue[586] num_rntis[4]

freerbs[18],sub_bitmap[7]
subband_bitmap_arr[0]=0,subband_bitmap_arr[1]=[4],subband_bitmap_arr[2]=0,subband_b
itmap_arr[3]=3
start_Alloc_idx[0],no_alloc_rbs[0],sub_bitmap[0]
start_sub_idx[0] allocation_status[0]

subband_bitmap_arr[0]=3,subband_bitmap_arr[1]=[224],subband_bitmap_arr[2]=0,subband
_bitmap_arr[3]=0
error; gCntr[14387] num_rntis[3], max_req_rbs_ue < 1

subband_bitmap_arr[0]=96,subband_bitmap_arr[1]=[3],subband_bitmap_arr[2]=0,subband_
bitmap_arr[3]=0
error; gCntr[15251] max_req_rbs_ue < 1 , cntr[2],max_data_in_ue[65205]

num_rntis[2] freerbs[23],sub_bitmap[103]
itmap_arr[3]=0


_bitmap_arr[3]=0

_bitmap_arr[3]=0
start_sub_idx[3] allocation_status[0]avg_cqi[12]
avg_cqi[10]
avg_cqi[11]
avg_cqi[9]
avg_cqi[7]
avg_cqi[8]
avg_cqi[7]
avg_cqi[9]
MAX SCHEDULABLE REACHED: Discarding TIME n_schedulable_ues =1


_bitmap_arr[3]=0

itmap_arr[3]=3

itmap_arr[3]=0
error; gCntr[21245] num_rntis[2], max_req_rbs_ue < 1 better avg cqi[10]
better avg cqi[7]
better avg cqi[11]
better avg cqi[8]
better avg cqi[6]
better avg cqi[12]
better avg cqi[8]
better avg cqi[10]
error; gCntr[21725] num_rntis[1], max_req_rbs_ue < 1 GOOD_cqi[8]

GOOD_cqi[9]
GOOD_cqi[12]
GOOD_cqi[13]
GOOD_cqi[12]
GOOD_cqi[15]
GOOD_cqi[14]
GOOD_cqi[15]
error; gCntr[22845] num_rntis[1], max_req_rbs_ue < 1 best_cqi[15]

best_cqi[14]
best_cqi[15]
best_cqi[14]
best_cqi[15]
best_cqi[12]
best_cqi[13]
best_cqi[14]

avg_cqi[12]
avg_cqi[10]
avg_cqi[11]
avg_cqi[9]
avg_cqi[7]
avg_cqi[8]
avg_cqi[7]
avg_cqi[9]

better avg cqi[7]
better avg cqi[11]
better avg cqi[8]
better avg cqi[6]
better avg cqi[12]
better avg cqi[8]
better avg cqi[10]

GOOD_cqi[9]
GOOD_cqi[12]
GOOD_cqi[13]
GOOD_cqi[12]
GOOD_cqi[15]
GOOD_cqi[14]
GOOD_cqi[15]

best_cqi[14]
best_cqi[15]
best_cqi[14]
best_cqi[15]
best_cqi[12]
best_cqi[13]
best_cqi[14]

avg_cqi[12]
avg_cqi[10]
avg_cqi[11]
avg_cqi[9]
avg_cqi[7]
avg_cqi[8]
avg_cqi[7]
avg_cqi[9]

better avg cqi[7]
better avg cqi[11]
better avg cqi[8]
better avg cqi[6]
better avg cqi[12]
better avg cqi[8]
better avg cqi[10]

GOOD_cqi[9]
GOOD_cqi[12]
GOOD_cqi[13]
GOOD_cqi[12]
GOOD_cqi[15]
GOOD_cqi[14]
GOOD_cqi[15]

best_cqi[14]
best_cqi[15]
best_cqi[14]
best_cqi[15]
best_cqi[12]
best_cqi[13]
best_cqi[14]

error; gCntr[48927] num_rntis[2], max_req_rbs_ue < 1 avg_cqi[12]
avg_cqi[10]
avg_cqi[11]
avg_cqi[9]
avg_cqi[7]
avg_cqi[8]
avg_cqi[7]
avg_cqi[9]

better avg cqi[7]
better avg cqi[11]
better avg cqi[8]
better avg cqi[6]
better avg cqi[12]
better avg cqi[8]
better avg cqi[10]

GOOD_cqi[9]
GOOD_cqi[12]
GOOD_cqi[13]
GOOD_cqi[12]
GOOD_cqi[15]
GOOD_cqi[14]
GOOD_cqi[15]

best_cqi[15]
best_cqi[14]
best_cqi[15]
best_cqi[14]
best_cqi[15]
best_cqi[12]
best_cqi[13]
best_cqi[14]

avg_cqi[10]
avg_cqi[11]
avg_cqi[9]
avg_cqi[7]
avg_cqi[8]
avg_cqi[7]
avg_cqi[9]

better avg cqi[7]
better avg cqi[11]
better avg cqi[8]
better avg cqi[6]
better avg cqi[12]
better avg cqi[8]
better avg cqi[10]

GOOD_cqi[9]
GOOD_cqi[12]
GOOD_cqi[13]
GOOD_cqi[12]
GOOD_cqi[15]
GOOD_cqi[14]
GOOD_cqi[15]

best_cqi[15]
best_cqi[14]
best_cqi[15]
best_cqi[14]
best_cqi[15]
best_cqi[12]
best_cqi[13]
best_cqi[14]

avg_cqi[10]
avg_cqi[11]
avg_cqi[9]
avg_cqi[7]
avg_cqi[8]
avg_cqi[7]
avg_cqi[9]

better avg cqi[7]
better avg cqi[11]
better avg cqi[8]
better avg cqi[6]
better avg cqi[12]
better avg cqi[8]
better avg cqi[10]



l2 22.07

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+--------------------------------------------------------------------+

Dl_Process RACH riv[450] rnti[61]

setting subband_bitmap in Rar Alloc [3]

Dl_Process RACH riv[50] rnti[62]

Dl_Process RACH riv[450] rnti[63]

setting subband_bitmap in Rar Alloc [3]

Dl_Process RACH riv[450] rnti[64]

setting subband_bitmap in Rar Alloc [3]

Dl_Process RACH riv[50] rnti[65]

setting subband_bitmap in Rar Alloc [1]

Dl_Process RACH riv[450] rnti[66]

setting subband_bitmap in Rar Alloc [3]

for() cur_bit_idx [4] ,first_rb_index[24] last_rb_index[32] free_rbs[18]

for() cur_bit_idx [4] ,first_rb_index[24] last_rb_index[32] free_rbs[18]

for() cur_bit_idx [4] ,first_rb_index[24] last_rb_index[32] free_rbs[18]

for() cur_bit_idx [4] ,first_rb_index[24] last_rb_index[32] free_rbs[18]

for() cur_bit_idx [4] ,first_rb_index[24] last_rb_index[32] free_rbs[18]

for() cur_bit_idx [4] ,first_rb_index[24] last_rb_index[32] free_rbs[18]

for() cur_bit_idx [4] ,first_rb_index[24] last_rb_index[32] free_rbs[18]

for() cur_bit_idx [4] ,first_rb_index[24] last_rb_index[32] free_rbs[18]

required_rbs allocated rbs [0] < 0 sub_bitmap[48],no_rb[8],index[3]

error; gCntr[12861] max_req_rbs_ue < 1 , cntr[4],max_data_in_ue[586] num_rntis[4]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[17]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[17]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[17]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[17]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[17]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[17]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[17]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[17]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[17]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[17]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[17]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[17]

required_rbs allocated rbs [0] < 0 sub_bitmap[24],no_rb[12],index[2]

error; gCntr[12923] max_req_rbs_ue < 1 , cntr[3],max_data_in_ue[8076] num_rntis[3]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[24]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[24]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[24]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[24]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[24]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[24]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[24]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[24]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[24]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[24]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[24]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[24]

required_rbs allocated rbs [0] < 0 sub_bitmap[24],no_rb[12],index[2]

error; gCntr[15235] max_req_rbs_ue < 1 , cntr[3],max_data_in_ue[2046] num_rntis[3]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[23]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[23]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[23]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[23]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[23]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[23]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[23]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[23]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[23]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[23]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[23]

for() cur_bit_idx [3] ,first_rb_index[18] last_rb_index[30] free_rbs[23]

required_rbs allocated rbs [0] < 0 sub_bitmap[24],no_rb[12],index[1]