Oh yy VE 2019 RVUs Ae cle y- Electronics Engineering Objective Practice Sets icroprocessors & Computer Organiza‘ Contents SI. Topic Page No. 1, _ Introduction to 8085 and its Functional Organization 2 2, Machine Cycle, Instruction Cycle & Interfacing in Microprocessors 3 3, Instructions Set and Data Formats 4 4, Memory Accessing and Addressing Modes 10 5. Worked Out Examples " 6. Data Representation 2 7. Basic Computer Organization % 8, Central Processing Unit (CPU) z 9. Memory Organization and VO organiza 2 Volatr are lab to be leg prvectedMicroprocessors and Computer Organization Instructions Set and Tras a4 a2 Qs a4 Cd obese Practice set ‘The 8086 arithmetic instructions work on 1. Signed and unsigned numbers, 2. ASCII data, 3. unpacked BCD data Select the correct answer using the codes given below (a) tand2 (c) tand3 (b) 2and3 (d) 1,2and3 In an 8085 microprocessor, the instruction CMP B has been executed while the content of the accumulator is less than that of register 8. As a result (a) Camy flag will be set but Zero flag will be reset (©) Carry tlag will be reset but Zero fiag will be set () Both Carry tlag and Zero flag will be reset (a) Both Carry flag and Zero flag will be set ‘A microprocessor, on arrival of RESET signal returns, from HALT state to (@) Execute (b) Fetch (@) Interrupt (@) None of the above The following sequence of instructions are executed by an 8085 microprocessor: 1000 LxISP, a7 FE 1000 CALL 1006 1006 POPH The contents of the stack pointer (SP) and the HL, register pair on completion of execution of these instructions are (a) SP =27 FF,HL = 1003 (b) SP =27 FD, HL = 1003 (c) SP =27 FFHL = 1006 (@) SP =27 FD, HL = 1006 as as a7 as ag Data Formats In the 8085 microprocessor, the RST6.5 instruction transfers the program execution to the following location: (@) 34H (©) 48H () 24H (@ 60H If instruction RST § is written in a program the problem will jump to location (@) 0020 (b) 002441 (c) 0028 H (d) o02cH Asingle instruction to clear the lower four bits of the accumulator in 8085 assembly language is (@) XRIOFH () ANIFOH () XRIFOH (d) ANIOFH With a clock frequency of 3 MHz, the execution time for the instruction, "STA addr’ of 8085 will be (a) 4333 ns (6) 3975 ns (©) 3115s (d) 3960ns If 8085 adds 87 H and 79H, specily the contents, ofthe accumulator and the status of the S, Zand CY flags (a) 100H)S 0, CY=1,Z= (b) 00H, S=0,CY=1,Z=1 (c)) 100 HS = 1, CY (d) 1004, 8 =0,CY¥=0,Z=1 Q.10 Specify the status of Z and CY when the instruction XRA A is performed? (@) CY=0,2=0 (b) CY¥=0,Z=1 (©) C¥=1,2=0 (d) CY¥=1,2=1 www.madeeasypublications.org )MADE EASY Q.24 Consider the following segment of program for 8085 up. XRAA Lx1B, 0007H Loop : DOXB NZ Loop The number of times the loop executed is (@) Infinite (0) zero ©1 (7 Q.25 Consider the following assembly language program of an 8085 yp Postal Study Package BQIE] Microprocessors & Computer Org. | 7 In the value of port 1 is 30 H, then the value of x is (@) o1H (©) 03H (©) FH (@) 06H Q.26 If the time required to execute JMP 1284 H instruction is 25 useconds. Then the crystal frequency of 8085 uP is (@) AmHz (0) 8mHz (©) 16mHz (a) 32mHz. Q.27 The number of memory IC's of 4 k x 2 capacity required to construct a memory of 22 k x 8 Vt A, XH capacity is Be @n (b) 22 Ble (© 3 (a) 44 RLC OUTPORT1 HLT EEEEEEE structions set and Data Formats © 2@ 36) 40 §5S@ 66) 7) 8 8 6) 10. (b) 14. ©) 12. @) 18.) 14.) 15.) 16.) 17. (@) 18. (e) 18.B (c) 19. (d) 20. (c) 21. (d) 22. (0) 2B. (c)_ 2H. (c) 2B. (@)— 2B. (0) 27. (a) EXE Instructions Set and Data Formats 2 (a) 4 (¢) CMP B, compose A with B, SP © 2YFF WWA FLAG 2 Q.14 (A)|I'the last operation performed on a computer with an 8 bit word was an addition in which the operands were 2.and 3. The values of cary and zero flags are @ 90.0 () 04 © 1,0 (@ 1,1 Q.14 (B) The values of even and odd parity flags are (@)1,0 (b) 0, 1 () 0,0 qd) 11 Q.15 Asynchronous sequential circuits are seldom designed to operate in the pulse mode, because (@) the amplitude of input pulses in a pulse modells very critical (b) the duration of the input pulses in a pulse mode is very critical (©) fundamental made asynchronous circuit is cheaper than pulse mode asynchronous circuit (@) fundamental mode asynchronous circuit has a higher speed of operation than the pulse mode asynchronous circuit Q.16 Aninterruptin which the external device supplies its address as well as the interrupt request, is known as (@) non-vectored interrupt (b) maskable interrupt (6) polled interrupt (d)_none maskable interrupt Objective Practice Sets www.madeeasypublications.org )MADE EASY ESET 2079] —icroprocessors & Computer Org. | 19 Worked Out Examples 1 @ A: 23H B: FFH (as all 1's one) B= 00H AND operation of Aand B, willbe A: 00100044 B: 00000000 A: 00000000 Ac AB 2 (a) RS-282 Is a standard for serial communication transmission of data. If formally defines the signals connecting between a DTE (data terminal equipment) such as computer terminal, and a DCE (data-circuil terminating equipment, or data communication equipment). 3. (c) 80286, was the first 2086 baed CPU with seperate, non-multiplexed, address and data buses and also the first with memory management and wide protection abilities. 4. (c) IR (Instruction register) is a part of a CPU's control unit that holds the instruction currently being executed/decoded. 5. (d) (FE 35),6O (CB 15,5 (111141100011010%), __ (1190101100010101), _ © (0011010100100000), (35 20h6 6. (d) In minimum mode, 8086 itself generates all bus control signals. In maximum mode the three status signals are to be decoded to generate all the bus control signals 7. (b) 8086 has eight more or less general 16-bit registers (including the stack pointer but excluding the instruction pointer, flag register and 10. 1. 14, 14, 22. segment registers). Four of them, AX, BX, CX, PX can also the accessed as twice as many 8-bit reigsters. (a) Statement (I) is false as correct statement is the integrating type AID converter is a high accuracy converter, (d) 1111 1110 0111 0101 1100 1011 0001 0101 4100 1010 0001 0101 = (CA15) (b) The frequency input is twice that of clock frequency, (9) As per flow chart, If X>Y¥,X>Z, print x Y>X,Y>Z, print 'Y Z>X,Z>Y. print 2" Thus largest value is printed A. (a) Result of Adcition is 5. ie00000104 # Carty = 0 also zero flag = 0 B. (a) ‘Addition produced two 1's and hence contents of even parity flag is ‘1 (ce) ‘8000 oF 3001 FA (ow. .deeasypublications.org MADE EASY