Inverter Delays

Cont….
2.CMOS Inverter:

• Let 2 𝑐𝑔 be the capacitance. That acts as load to the inverter. This capacitances
due to the gate of next inverter.
❖Case(i).𝑉𝑖 =0v
• Pull-down transistor is OFF. pull-up transistor is ON.
• Pull-up transistor is initially in saturation region and Finally reaches linear region.
 Cont….
• τ𝑐ℎ𝑎𝑟𝑔𝑒 = 𝑅𝑃.𝑈 × 2 𝑐𝑔
𝐿
= 𝑅𝑠 × 2 𝑐𝑔
𝑊
41
=(2.5× 10 ) ×2*(0.01PF)=0.5 ns=5 τ (τ=0.1ns)
1
❖Case(ii) 𝑉𝑖 =5v
• Pull-up transistor is OFF and pull-down transistor is in linear Region.
• The capacitor discharges through 𝑅𝑃.𝑑
• τ𝑑𝑖𝑠𝑐ℎ𝑎𝑟𝑔𝑒 = 𝑅𝑃.𝑑 × 2 𝑐𝑔
𝐿
= 𝑅𝑠 × 2 𝑐𝑔
𝑊
1
=(10kΩ × ) ×2*(0.01PF)=0.2 ns=2 τ
1
∴the operation of this inverter is Highley asymmetric.
 Cont….
❖Let us consider the inverter pair as shown in figure

❖Case(i) 𝑉𝑖 =0v
Consider inverter-1
• τ𝑐ℎ𝑎𝑟𝑔𝑒 = 𝑅𝑃.𝑈 × 2 𝑐𝑔
𝐿
= 𝑅𝑠 × 2 𝑐𝑔
𝑊
1
=(2.5× 104 × ) ×2*(0.01PF)=0.5 ns=5 τ (τ=0.1ns)
1
 Cont….
Consider inverter-2
• τ𝑑𝑖𝑠𝑐ℎ𝑎𝑟𝑔𝑒 = 𝑅𝑃.𝑑 × 2 𝑐𝑔
𝐿
= 𝑅𝑠 × 2 𝑐𝑔
𝑊
1
=(10kΩ × ) ×2*(0.01PF)=0.2 ns=2 τ
1
Total delay between input of first inverter and output of second inverter
τ𝑐ℎ𝑎𝑟𝑔𝑒 +τ𝑑𝑖𝑠𝑐ℎ𝑎𝑟𝑔𝑒 = 5 τ +2 τ=7 τ
❖Case(ii) 𝑉𝑖 =5v
Consider inverter-1
• τ𝑑𝑖𝑠𝑐ℎ𝑎𝑟𝑔𝑒 = 𝑅𝑃.𝑑 × 2 𝑐𝑔
𝐿
= 𝑅𝑠 × 2 𝑐𝑔
𝑊
1
=(10kΩ × ) ×2*(0.01PF)=0.2 ns=2 τ
1
 Cont….
Consider inverter-2
• τ𝑐ℎ𝑎𝑟𝑔𝑒 = 𝑅𝑃.𝑈 × 2 𝑐𝑔
𝐿
= 𝑅𝑠 × 2 𝑐𝑔
𝑊
1
=(2.5× 104 × ) × 2 ∗(0.01PF)=0.5 ns=5 τ
1
Total delay between input of first inverter and output of second inverter
τ𝑐ℎ𝑎𝑟𝑔𝑒 +τ𝑑𝑖𝑠𝑐ℎ𝑎𝑟𝑔𝑒 = 5 τ +2 τ=7τ