Ipad4 579ca1458-Schematic

820-3249-TOP MLB
R8297 R8296
R5991
C5991
R5990
C1621 C1652 C1635 C1632 C1623
C8114
C8113
R1020
C1611 C1615 C1612 C1613 C1408 C5931
C1023
C1335
C1631 C1651 C1650 C1625 C1622 C1633
C1406
R5929
C1307
C1427
C1424 C1425 R10234 C1324 C1334 C5935
U5900
C1311
C1192
D8100
C5940 R5930
C1433
C5930
C1327
C1022
C1308
C1301
C1412
C1363
R1355
J5900
R5931
R1083 R1055
L8111
C1432
C5934
C1462
C1431
R1453
C1420 C1085 C1058
C1320
R1356
C1356
C1197
C1144
C1423
C5942
C5932
C1304 C1323
C1312
C1326
C5933
C1313
C1333
C1434
C1405
C1413
C1084 R1056
C5943
C1419
C5944
C1454
R1454
J7500
C1422 C1407 R1084 R1420 C1056 C1306 C1330 C1322
R2205
C5941
L8107
C3009
R3009
C1321
R3012
C3001 C8195
C3008 C3002
C1401
L8112
C3112
C1318
C8107
C1402
C8118
C8166
C1426
C8124
C1302
C1435
C1362
R1353
R9002
R3171
C1463
C1456
LED9000
R3180
C1331
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C3060
U3060
C3110 C1409
C1354 R1354 C1309
L3000
C1411
U3000
R1455
R1456
C3106 C3108 C8125 C8126
C1421
L8106
C1021
U1600
R3173 R3190 C1314
R3025
C3191
C3192
R3060 C8117 C8163
C3105
C3107
R1022
C1054
R1054
C1057
R1053
C8164
R0760
C1325
C8237
C8154
C1096
R1096
R1095
C1095
C8131
R3160
C8165
C8108
C8119
C1100
D3000
C3615
C3602
R3610
R3613
R3611
C3000
C1403
L8229
R3640
U3009
U3010
L8105
C3041
C3050
C3691 C1319 C1305
C1404 C1430 R1021
R3612
R3066
C1303 C1020
C3616
C1414 C3784 C3786 C3759
J2200
C8194
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C3758
C3787
U8100
C3618 D8258 R3751
R3032
C3617
R8222
R3755
C1105 C8152 FL3750
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C3756
C3751
C3752
C3753
C8100 C8101 R3754
C3788
C3610 C3601 C1104
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U3750
C8149
R3030
C3603
C1102 C8262 C3723
FL3751
C3614
C1101 C8147
C3605
C3757
C3030
J6050
C8226
L8255
R0642 R0643
R3101
C3031
C8263 R0721 C3783 C3750
C1634
L8100 L8101
C3053
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C1614
R0608
C3630 R8281 C1630
C1610 R0622
C3781
C3103
C3007
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C3749 C3766
C3101
C3005
C1624
C1103
C8292
R0640 R0620 R0621
C8148 C3748
L3750
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R3614
C3631
R3741
C3608
R3752
C3607
C3606
C3764
R0652
R3033
C3620
R3631 C3102
L3620
C3104 C3722
C3721 C3780 FL3740
R3155
C8265
C8264
R0718 C8144
C3741
C3742
C3743
C3632 R3181
C1179 R3753
C3744
C3746
U3740
C3713
R0715
C8121
C3755
C3720
FL3741
C3761
C8120
C8155
C8103
C8143
Y8138
R1208
J6051
C3767
CA185
C3747
R1209
R3745 C3740 C3763
C8122
C8142
R1203 D8228 R3744
C3768
R1220
C3070
L3740 R3742
L8104
R0717
J5950
C3712
C3711 C3760
C6109
L8110
C8232
R6111_RF
L8103
R3743
L8225
R3070
L8102
R3740
C3745
C3710
L6111_RF
C8233
L8109
R3071
J5400 J5401 J3010 J3011 R9000
C8104
C8105
R0714 R0651 R0650
R1204
R1205
R1206
R0702
R0701
C8123
R0713
R0709
R0710
R0708
R0716
R0720
R0711
R0700
R6112_RF
C8102
C6101_RF
C6102_RF
C8234
C8235
C8111
C8112
U6102_RF
R0703
R0704
C6110_RF
R1201
R1202
R1200
Y0602
C0651
R0730
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C0650 R6113_RF
C5936 C8109 C8110 C8256

R5935
J6190_RF
R6108_RF
R6109_RF
U5903
R5934
C6104_RF
R5962
R6114_RF
R6105_RF
R6107_RF
R5961
R5960
C5960
C6103_RF
R5933
R5932
820-3249-BOT MLB
DZ5792
DZ5791
L5701
L5700
C1329
C1429
C5920
C5910
C1328
C1428
DZ5903
DZ5902
DZ5900
DZ5901
R8216
L5931 L5930
C1317
C1416
R1655
DZ8120
DZ5750 DZ5990
R8130
C1608
C5783
C5765
L5757
DZ5760
C5750
C5766
Q8123
C5900
C1360 R1451
C1606
C1609
R9031 C1605
FL5750 R1305 C1461
U1300 U1400
Q9030 C1602
R8116
R9030
R1306 R1452
C1601 C7527
C5721
R5790
C7525
C5722
C3111
R9021
C1350 C1452 R1690 C1691
C3109
U3101
Q9020 R9020
C7524
C1142
C1194
C1143
R0832
C1690 R1691 R0831
C5990
R8170 FL7500 C7523
R3107
FL5990
C7526
R8196
C1193
C1196
C1195
R8219 C7522
C8196
R2242
U2200
C8193
C8162
C8220
C1109
C2241
C1607
C2202
D8230
C1125
C8206
C2232
C2206
R2290
C2230
C2203
C2240
C2239
C8267 C1600 L2201
L2210
L2200
C8236
C8130
C3773
R3120
C1111
C1119
C8192
C8251
C8161
C1604
C8209
R8270
C8290
R8227
R8265
R8232
R8239
R8261
Q8104
R1654
C3772
C8169 C8210 C8266 R8290
C3609
C2233 C2253
J6000
C2281 C2280
C8168 C2287 C2286 C2285 C2283 C2282
C1108
C2284
C1129
R8173 R2287 R2286 R2285 R2284 R2283 R2282 R2281 R2280
R8292
C8201
C8191
C8160
C1460 C3690
R1351 C3604
C0636
C11A1
C1139
C11A0
R1320
C1316
C1136
C1115
C1113
C1114
C2220
C1418
C2270
C1310
C1332
C1417
C1128
C1410
C8239 C8138
C8217
C1315 C1191 C1107 C1155 C1190 C1415 C3006
C3612
C1361 R1405
R8218
C1124 L2202 L2232 L2222 L2212
C8172
R8172
C1138
C8238 R1352 R1406
C2221 C2271
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C3613
C8134
C8223
R1321
C8171
C8173
C8174
C8170
R8231
R8235
R8240
R8257
R8262
R8269
C1122
C1198 C1126 R0604 C0607 C1162 C0631
R1421
CA186
C1352
C0637
C1450
C1156
R1260
R1210
C8212
C0606
C1120
C8190
C8159
C8214
CA190 R1211 C1158 C0635
C1123
C1117 C1164 R3601
C2249
C2248
C2245
C2244
C0935
C2247
C2246
C2243
C2242
C8132
CA191
C1110
C1137
C8145 C1134 C1159
C11C0
CA189 C1131 C0960
C1152
CA152
C1163
C11C1
C3611
C0924
C1135 C1151
C1165
C1166
C0927
C0982
C8215
R8100
U3100
C8133 C1132
Q8200
C1140
C1157 C1160
FL0910
C0903
C3771 CA151 C0908
C0955
C1121
C1178
R2240
C8221 C1130
C8146 CA196 C1106 C1150 C2250
L2242
C1116
C8189
C8158
C1172
C0981
C1154
C1161
C1181
C8281
R0920
C0950
C8136 C1133
U3003
C2251
R2241
C0623 C1182 C0904
C1170
C0953
C1177
C1169
C1175
C8135 C1141
C0980
C8157
C8139
C3770 C0961
C1171
CA193 C1118
R8282
C0910
C8204
R8203
C1149
C8153 C0952 FL0911 C0810
C1153
C0907
C1173
C8282
C8207
C8137
FL5740
C5741
C0613
C0612
C1148 C1147
R0950
C0956 C1184
C1174
C8187
C8188
C8156
C0932 CA188
CA194
CA192
C1185
C0633
C0634
C8151
CA198
C5711 C1176
C0951
C1183
C5551
C5581
C1199
C8141
C0812
C8167
R8291
R9001
C5740 FL5710 C0614 C1180

C8140
C5661
C5561
C0928
C0632 C0820
CA197
C1145
CA153
CA195
C5571
C8291
CA199 L5580
C11B0
C11B1
C5710
R0930
DZ5740 C0821
C0934 R0921
CA187
R0931
D5990 CA150
C11E0
C11E1
R8293
L5560
Q8203
C0930
C11F0
R1207
DZ5710 C0957
C5730
C0630
C0931 C0811 C5580 C5550

R0613
R0911
R0842
C0842
C5660
C0843
R0843
R0941
C0933
R9010
R0933
R9011
R8280
C5732
U5660
R0942
C5570 C5562
U5650
C0929 C5582 L5550
C0621 C1167 L5570
C11D1
C11D0
L5730
R0610
C0909 C5572 C5583 C5552
C5563
C5560
C5640
R0940
R0900
C5731 C0609
C1168
C5733 Q9010 C5573
Q8201
C5584 C5553
C6107_RF
C5671
C0608
C5670
L5500
L5510
R5641 R5640
R0932
C0605
U5640
L5530
L5540
L5520
U5600
U5670
U6104_RF
L6192_RF
RF
R5630 R5631
2_
19
U6101_RF
C6
R0706
U5630
U5620
R0705
L6191_RF
C5630
R0719
U5610
C6108_RF
J6191_RF
RF
1_
L6190_RF
11
C6
RF
C6191_RF
0_
19
C6
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
iPad 4th Gen

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
A 0001554595 PRODUCTION RELEASED 2012-07-26
LAST_MODIFIED=Thu Jul 26 10:29:36 2012

D D
PDF CSA CONTENTS SYNC MASTER DATE (SYSTEM DRI)
TABLE_TABLEOFCONTENTS_HEAD
PDF CSA CONTENTS SYNC MASTER DATE (SYSTEM DRI)
1 1 Table of Contents N/A N/A

(AMANDA) TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
31 83 PMU: ADRIANA PAGE 3 MADHAVI 12/06/2011 (MADHAVI)
2 2 BLOCK DIAGRAM: SYSTEM N/A N/A

(AMANDA) TABLE_TABLEOFCONTENTS_ITEM
32 90 DEBUG/MISC. MLB 11/09/2011 (AMANDA)
3 4 BOM TABLES N/A N/A (AMANDA)

33 93 TEST/HOLES/FIDUCUALS N/A N/A (AMANDA)

4 6 AP: MAIN N/A N/A
(TERRY) TABLE_TABLEOFCONTENTS_ITEM
34 121 POWER ALIASES N/A N/A (MADHAVI)

5 7 AP: I/Os N/A N/A
(AMANDA) TABLE_TABLEOFCONTENTS_ITEM
35 150 CONSTRAINTS: MLB RULES MIKE 11/30/2011 (AMANDA)

6 8 AP: NAND N/A N/A (TERRY)
36 151 CONSTRAINTS: LOW SPEED BUS MIKE 11/30/2011 (AMANDA)

7 9 AP: TV,DP,MIPI N/A N/A
37 152 CONSTRAINTS: DISPLAY/AUDIO MIKE 11/30/2011 (AMANDA)

8 10 AP: DDR N/A N/A (TERRY)
(TERRY)
38 153 CONSTRAINTS: DDR/FMI MIKE 11/30/2011 (AMANDA)
9 11 AP: POWER N/A N/A
39 154 CONSTRAINTS: POWER / GND MIKE 11/30/2011 (AMANDA)

C 10
12 AP: MISC & ALIASES N/A N/A
C
(TERRY)
11
13 DDR 0 AND 1 N/A N/A
(TERRY)
12
14 DDR 2 AND 3 N/A N/A
13
16 NAND N/A N/A
(AMANDA)
(AMANDA)
14
21 ALIASES N/A N/A
(JOE)
15 22 VIDEO: EDP CONNECTOR N/A N/A
16 30 GRAPE: GROUNDHOG,CONN,BOOST N/A N/A

(AMANDA)
(AMANDA)
17
31 GRAPE: Z1, Z2 N/A N/A
18 36 AUDIO: L81 CODEC N/A N/A

(TERRY)
19
37 AUDIO: SPEAKER AMP N/A N/A
(TERRY)
(MARK)
20 54 SENSOR FLEX CONN N/A N/A
B TABLE_TABLEOFCONTENTS_ITEM
(MARK) B
21 55 SENSOR CONN FILTERS 1 N/A N/A
(MARK)
22
56 SENSOR CONN FILTERS 2 N/A N/A
(JOE)
23 57 E75 DOCK SUPPORT N/A N/A
(JOE)
24
58 IO FLEX CONN N/A N/A
25 59 TRISTAR N/A N/A

(JOE)
(AMANDA)
26
60 CONNECTOR: CELLULAR N/A N/A
27
61 WIFI/BT N/A N/A
(MATT)
28 75 POWER: BATTERY CONNECTOR MADHAVI 12/06/2011 (MADHAVI)

29
81 PMU: ADRIANA PAGE 1 MADHAVI 12/06/2011 (MADHAVI)
30 82 PMU: ADRIANA PAGE 2 MADHAVI 12/06/2011 (MADHAVI)
A
DRAWING TITLE
A
X140 MLB
DRAWING NUMBER SIZE
Apple Inc. 051-9385 D

REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH
DRAWING
THE INFORMATION CONTAINED HEREIN IS THE
MLB PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
DRAWING I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 154
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 1 OF 39
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ISP_I2C1 FF CAMERA
Z2 SPI3
MIPI1C VGA FLEX
CSA 31 ISP_I2C0 REAR CAMERA

MIPI0C VA5 FLEX
D HSIC1_1
D
GROUNDHOG Z1 WIFI/BT ANT
UART3
WIFI/BT
CSA 30 CSA 31 UART4
LPDDR2 I2S2 BT_I2S
CSA 61
CSA 13-14
BALI NOT ON
DISPLAY/ WIFI-ONLY CONFIG
TOUCH PANEL CELLULAR/
EDP
HSIC3 HSIC1
GPS
PRIMARY CELLULAR ANT
IPC DIVERSITY CELLULAR ANT
C UART1 USART GPS ANT
C
BACKLIGHT USART SIM CARD
CSA 60
UART5
HALL EFF 1
PMU BATTERY
BUTTON FLEX
ADRIANA USB11 TRISTAR
CSA 75 USB2.0
HALL EFF 2
DWI UART2
I2C0 UART6
HOME BUTTON CSA 81,82
B I2S1 CSA 59 B
I2C1 AUDIO CODEC
L81
PROX SENSOR COMPASS
SPI1 MBUS
SPI
SENSOR BOARD SENSOR BOARD I2S0 ASP
AMP
I2S3 XSP SPEAKER
I2C2 FMI0 FMI1 I2S4 NC AMP
GYRO ACCELEROMETER ALS HP

CSA 36
A SENSOR BOARD SENSOR BOARD VGA FLEX SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
NAND FLASH BLOCK DIAGRAM: SYSTEM

MIC1 MIC2 DRAWING NUMBER SIZE

REVISION
R
A.0.0
PROPRIETARY PROPERTY OF APPLE INC.
CSA 16 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

2 OF 154
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SCH AND BOARD P/N

Page Notes
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_ITEM
051-9385 1 SCH,MLB,X140 SCH1 CRITICAL

Power aliases required by this page: TABLE_5_ITEM
(NONE) 820-3249 1 PCBF,MLB,X140 PCB1 CRITICAL
Signal aliases required by this page:

(NONE)
BOM options provided by this page:
D SOC
D
BOM OPTIONS
COMMON
TABLE_5_HEAD
ALTERNATE PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
16GB_PROD: 16GB CONFIG

TABLE_5_ITEM
32GB_PROD: 32GB CONFIG 343S0598 1 IC,SOC,H5G,FCBGA1089,0.5MM U0600 CRITICAL

64GB_PROD: 64 GB CONFIG
DEV: DEV BOARD ONLY
MLB: MLB BOARD ONLY
MLB_A: WIFI ONLY CONFIG
MLB_B: CELLULAR CONFIG
MLB_C: CELLULAR CONFIG
MLB_D: LEGACY CELLULAR CONFIG
MLB_E: LEGACY CELLULAR CONFIG PMU
TABLE_5_HEAD

TABLE_5_ITEM
343S0622 1 IC,PMU,ADRIANA,D2018A1,FCBGA U8100 CRITICAL
SDRAM
TABLE_5_HEAD

TABLE_5_ITEM
333S0636 2 LPDDR2,533MHZ,512MB,SAMSUNG,35NM U1300,U1400 CRITICAL
TABLE_BOMGROUP_HEAD
BOM GROUP BOM OPTIONS

TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

TABLE_BOMGROUP_ITEM PART NUMBER
BASIC COMMON,ALTERNATE TABLE_ALT_ITEM
C
333S0637
333S0638
333S0636
333S0636
U1300,U1400 LPDDR2,533MHZ,HYNIX,38NM
TABLE_ALT_ITEM
U1400,U1400 LPDDR2,533MHZ,ELPIDA,38NM
C
NAND
16GB FLASH CONFIGURATIONS
TABLE_5_HEAD

TABLE_5_ITEM
335S0878 1 TOSHIBA PPN1.5 16GB U1600 CRITICAL 16GB_PROD

MECHANICAL PARTS
TABLE_5_HEAD

TABLE_5_ITEM
TABLE_5_HEAD 335S0879 1 TOSHIBA PPN1.5 32GB U1600 CRITICAL 32GB_PROD

B NAND 806-4195 1 FENCE,NAND,TOP,MLB,X140 PD_FENCE_NAND CRITICAL

TABLE_5_ITEM
TABLE_5_ITEM
B
SOC/PMU 806-3493 1 FENCE,LARGE,TOP,MLB,X140 PD_FENCE_LARGE CRITICAL
TABLE_5_ITEM
AUDIO 806-3956 1 FENCE,AMP,MLB,X140 PD_FENCE_AMP CRITICAL

TABLE_5_ITEM
GRAPE 806-4196 1 FENCE,1,BTM,MLB,X140 PD_FENCE_BTM1 CRITICAL

TABLE_5_ITEM
MEMORY 806-3492 1 FENCE,2,BTM,MLB,X140 PD_FENCE_BTM2 CRITICAL

TABLE_5_HEAD
BARCODE LABEL/EEEE CODES 335S0880 1 TOSHIBA PPN1.5 64GB U1600 CRITICAL 64GB_PROD
TABLE_5_ITEM
TABLE_5_HEAD

TABLE_5_ITEM
825-7838 1 EEEE FOR 639-3736 (MLB A 16G) EEEE_F1WD CRITICAL EEEE_MLB_A_16G

TABLE_5_ITEM
825-7838 1 EEEE FOR 639-3737 (MLB A 32G) EEEE_F1WH CRITICAL EEEE_MLB_A_32G

TABLE_5_ITEM
825-7838 1 EEEE FOR 639-3738 (MLB A 64G) EEEE_F1W8 CRITICAL EEEE_MLB_A_64G

TABLE_5_ITEM
825-7838 1 EEEE FOR 639-4176 (MLB A 128G) EEEE_F80Q CRITICAL EEEE_MLB_A_128G

TABLE_5_ITEM 128GB FLASH CONFIGURATIONS
825-7838 1 EEEE FOR 639-3263 (MLB B 16G) EEEE_DWKG CRITICAL EEEE_MLB_B_16G TABLE_5_HEAD
TABLE_5_ITEM PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

825-7838 1 EEEE FOR 639-3739 (MLB B 32G) EEEE_F1W7 CRITICAL EEEE_MLB_B_32G TABLE_5_ITEM
TABLE_5_ITEM 335S0912 1 TOSHIBA PPN1.5 128GB U1600 CRITICAL 128GB_PROD

825-7838 1 EEEE FOR 639-3740 (MLB B 64G) EEEE_F1WC CRITICAL EEEE_MLB_B_64G
A
TABLE_5_ITEM
825-7838
825-7838
1
1
EEEE FOR 639-4177 (MLB B 128G)
EEEE FOR 639-3741 (MLB C 16G)

EEEE_F80P
EEEE_F1WG
CRITICAL
CRITICAL
EEEE_MLB_B_128G
EEEE_MLB_C_16G
TABLE_5_ITEM
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A A
825-7838 1 EEEE FOR 639-3742 (MLB C 32G) EEEE_F1WF CRITICAL EEEE_MLB_C_32G
TABLE_5_ITEM
BOM TABLES
TABLE_5_ITEM
DRAWING NUMBER SIZE

825-7838 1 EEEE FOR 639-3743 (MLB C 64G) EEEE_F1W9 CRITICAL EEEE_MLB_C_64G
TABLE_5_ITEM

825-7838 1 EEEE FOR 639-4178 (MLB C 128G) EEEE_F80R CRITICAL EEEE_MLB_C_128G REVISION
R
A.0.0
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
4 OF 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
A1 M28 R0604
0.00 2
A2 U0600 N3 34 =PP1V8_PLL_H5 1 39 PP1V8_PL0_F
VOLTAGE=1.8V
C33 BALI-H5G N9 0% MIN_LINE_WIDTH=0.2MM
1 C0605 1/32W 1 C0606 1 C0607 MIN_NECK_WIDTH=0.1MM
F1 BGA N11 MF NET_SPACING_TYPE=PWR
SYM 11 OF 12 0.1UF 01005 0.1UF 8.2PF MAX_NECK_LENGTH=3MM
A11 N13 20% 20% +/-0.5PF
A14 N15 2 4V
X5R 2 4V
X5R
16V
2 NP0-C0G-CERM
OMIT_TABLE 01005 01005 01005
A17 N17
A32 N19
A33 N21
D B1 N23
=PP1V0_USB_H5 34
D
B2 P1 34 =PP1V0_HSIC_H5
B4 P8 1 C0621 1 C0608 1 C0609
B9 P10 1 C0630 1 C0631 1 C0637 8.2PF 0.01UF 0.01UF
0.01UF 0.01UF 8.2PF +/-0.5PF 10% 10%
B12 P12 10% 10% +/-0.5PF 16V
2 NP0-C0G-CERM 2 6.3V 2 6.3V
6.3V X5R X5R
B15 P14 2 X5R 2 6.3V
X5R 2 16V
NP0-C0G-CERM 01005 01005 01005
B32 P16 01005 01005 01005
B33 P18 =PP3V3_USB_H5 34
C7 P20 34 =PP1V2_HSIC_H5
CHANGE TO USB 3.3V TO AVOID
C10 P22 1 C0632 1 C0633 1 C0634 1 C0635 1 C0636 1 C0612 1 C0614 ISSUE FOUND IN H5P:
C13 P30 0.1UF 0.1UF 0.1UF 0.01UF 8.2PF 8.2PF 1UF FAILURE IN CHARGE DETECT CIRCUIT AT 3.0V-5%
20% 20% 20% 10% +/-0.5PF +/-0.5PF 10%
C16 P33 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R 2 16V
NP0-C0G-CERM 2 16V 6.3V
NP0-C0G-CERM 2 CERM
A3 R2 01005 01005 01005 01005 01005 01005 402
D3 R6
D5 R9 =PP1V8_VDDIO18_H5 6 7 9 34
D8 R11
HSIC_VDD123 AF19
HSIC3_DVDD103 AF18
HSIC_VDD121 R27
HSIC_VDD122 R26
HSIC2_DVDD102 T28
VDD_ANA_PLL U18
5.4MA USB_DVDD R30

30MA USB_VDD330 P26
USB_ASW_VDD18 N26
D11 R13 1 C0623 1 C0613
D14 R15 8.2PF 0.1UF
+/-0.5PF 20%
D17 R17 2 16V 4V
NP0-C0G-CERM2 X5R
U19 R19 01005 01005
E10 R21
E22 R23 MLB MLB OPTION USED FOR FF
<1MA
E24 R32
BCM4330 11.9MA
8MA R0652
E25 T5
PER PIN 1
0.00 2
F2 T6 WLAN 2.7MA AP_WDOG AP_WDOG_RESET_IN OUT 25
PER PIN
F5 T8 36 14 BI HSIC1_WLAN_DATA R33 HSIC1_DATA U0600 WDOG C18 0%
1/32W
HSIC1_WLAN_STB T33 HSIC1_STB BALI-H5G MF
C C
F22 T10 36 14 BI 01005
BGA XI0 J33 36 XTAL_AP_24M_I
F24 T12 SYM 1 OF 12
NC_HSIC2_DATA R31 HSIC2_DATA XO0 K33 36 XTAL_AP_24M_O
F25 T14 OMIT_TABLE 1
NO_TEST=TRUE
NC_HSIC2_STB T31 HSIC2_STB R0650
F30 T16 NOSTUFF MDM9615 NO_TEST=TRUE 1.00M CRITICAL
=PP1V8_H5 USB11_DP E32 USB11_AP_BBMUX_P BI
A31 T22
34 10 7 5 4
R0608 BB USB 1.1 BASEBAND/TRISTAR 25 36 1%
1/32W Y0602
100K HSIC3_BB_DATA AN17 HSIC3_DATA NEEDED IF WE GO TO 9600 USB11_DM D32 USB11_AP_BBMUX_N BI SM-2
G3 T24 1 2
36 26 BI 25 36 MF R0651 24.000MHZ-16PF-60PPM
5% MF HSIC3_BB_STB AM17 HSIC3_STB 2 01005 22
G18 T32 1/32W 01005
36 26 BI 1 2 AP_24M_O 1 3
34 10 7 5 4 =PP1V8_H5 USB_DP M33 USB_AP_P 25 36
36
G21 U1 BI 5%
R0620 H17 JTAG_SEL TRISTAR CRITICAL CRITICAL
10 JTAG_AP_SEL USB_DM N33 USB_AP_N 1/32W 2 4
G22 U2
1
100K 2 BI 25 36
MF
01005
1 C0650 1 C0651
G26 U4 22PF 22PF
5% NC_JTAG_AP_TRTCK J16 JTAG_TRTCK USB_ANALOGTEST R25 NC_USB_ANALOGTEST 5% 5%
V18 U9 1/32W 01005 NO_TEST=TRUE
K16
NO_TEST=TRUE
2 16V
CERM 2 16V
CERM
H4 U11 39 36 10 IN JTAG_AP_TRST_L JTAG_TRST* 01005 01005
VSS VSS R0621 TP_JTAG_AP_TDO H16 JTAG_TDO USB_VBUS P28 USB_AP_VBUS0
H9 U13 100K 2 36
F16
1 36 JTAG_AP_TDI JTAG_TDI
H10 U15
5% 36 25 JTAG_AP_TMS F17 JTAG_TMS USB_ID P27 NC_USB_ID
H11 U17 1/32W 01005 NO_TEST=TRUE
36 25 JTAG_AP_TCK J17 JTAG_TCK USB_BRICKID P31 NC_USB_BRICKID PPVBUS_USB 29
H12 U21
R0622 NO_TEST=TRUE
1
H13 U23 100K 2 D18 TESTMODE R0610
H14 U33
1 10 IN AP_TESTMODE USB_REXT T30 USB_REXT0 68.1K
5% 1%
H21 V8 1/32W 01005 1/20W
L31 FUSE1_FSRC N32 CPU0_SWITCH MF
H22 V10 NEW TO BALI CPU0_SWITCH OUT 30
2 201
H28 V12 CPU_VDD CONTROL CPU1_SWITCH N24 CPU1_SWITCH OUT 30
10 OUT AP_TST_STPCLK A19 TST_STPCLK

H33 V14 34 10 7 5 4 =PP1V8_H5 C19 TST_CLKOUT
J2 V16 PP0600 PP
1 TP_AP_TST_CLKOUT USB_BRICKID_DM_MON P29 NC_USB_BRICKID_DM_MON
NO_TEST=TRUE
SM P4MM 1
J9 V19 1
R0640 R0613
J11 V21 7.5K 10 OUT AP_FAST_SCAN_CLK N27 FAST_SCAN_CLK 43.2
5% 1%
J13 V23 1/32W 1/20W
MF G16 HOLD_RESET MF
10 IN AP_HOLD_RESET 2 201
J15 V30 2 01005
B J21
T18
W3
W9 39 30 26 25 IN RST_AP_L G17 RESET*
B
P32 USB_ASW_VSS18
K3 W11
1 C0640 R06421 A18 CFSB
HSIC_VSS121
HSIC_VSS122
HSIC_VSS123
K8 W13
1000PF 100K
T25 HSIC2_DVSS
AG19 HSIC3_DVSS
L6 DDR0_CKEIN
R29 USB_VSSA0
K10 W15 10% 1%
K12 W17 2 16V
X7R-CERM
1/32W
MF
F9 DDR1_CKEIN
0201 01005 2 AG10 DDR2_CKEIN
K14 W20
AP_DDR1_CKEIN_1V2 AD5 DDR3_CKEIN
K22 W22
K26 W24
1
R28
T29
AG18
K30 Y1 R0643
L1 Y10 221K
1%
L4 Y12 1/32W
MF
L9 Y14 01005 2
L11 Y16
L13 Y18
L15 Y19
L17 Y21
L19 Y23
L21 Y25
L33 Y28
M2 Y32
M3 AA2
M8 AA9
M10 AA11
M12 AA13
A M14
M16
AA15
AA17 SYNC_MASTER=N/A SYNC_DATE=N/A A
M18 AA20 PAGE TITLE
M20
M22
AA22
AA24
AP: MAIN
DRAWING NUMBER SIZE

REVISION
R
A.0.0
6 OF 154
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
R0700
33.2
1%
1/32W
MF
01005 TO:
I2S0_CODEC_ASP_MCK_R 1 2 36 I2S0_CODEC_ASP_MCK M27 I2S0_MCK I2C0_SCL Y33 I2C0_SCL_1V8 TRISTAR 0011010X
36 18 OUT BI 5 19 25 30 36
ADRIANA PMU 0111100X OMIT_TABLE
36 18 OUT I2S0_CODEC_ASP_BCLK M29 I2S0_BCLK U0600 I2C0_SDA U29 I2C0_SDA_1V8 OUT 5 19 25 30 36 L19 LEFT 1000000X
L19 RIGHT 1000001X U0600
L81 CODEC ASP 36 18 I2S0_CODEC_ASP_LRCK N31 I2S0_LRCK BALI-H5G
OUT
1.8V R0730 M32 BGA BALI-H5G
I2S0_CODEC_ASP_DIN I2C1_SCL W27 I2C1_SCL_1V8
D 33.2
1%
1/32W
36 18
36 18
IN
OUT I2S0_CODEC_ASP_DOUT M26
I2S0_DIN
I2S0_DOUT
SYM 3 OF 12
OMIT_TABLE
I2C1_SDA W29 I2C1_SDA_1V8
BI
OUT
5 22 36
5 22 36
TO SENSOR BOARD:
AD7149 PROX 0101100X
AKM8975B COMPASS 0001110X
30 23 5 IN GPIO_BTN_HOME_L AK20 GPIO0
BGA
SYM 2 OF 12
EHCI_PORT_PWR0 AK28 GPIO_BRD_REV0 IN 10
D
MF
01005 30 20 5 IN GPIO_BTN_ONOFF_L AJ19 GPIO1 EHCI_PORT_PWR1 AJ25 GPIO_BRD_REV1 IN 10
I2S1_SPKAMP_MCK_R 1 2 I2S1_SPKAMP_MCK H30 I2S1_MCK I2C2_SCL H20 I2C2_SCL_3V0 TO SENSOR BOARD:
19 OUT BI 5 22 36
CT809 ALS 0111001X GPIO_BB_HSIC_DEV_RDY AK22 AK26 GPIO_BRD_REV2
L24 LIS331DLH ACCEL 0011001X 36 26 IN GPIO2 EHCI_PORT_PWR2 IN 10
19 OUT I2S1_SPKAMP_BCLK I2S1_BCLK I2C2_SDA B19 I2C2_SDA_3V0 OUT 5 22 36
AP3GDL8 GYRO 1101000X AK19 AK27
L19 AMPLIFIERS L23 20 IN GPIO_BTN_VOL_UP_L GPIO3 EHCI_PORT_PWR3 NC_EHCI_PORT_PWR3_AP
19 OUT I2S1_SPKAMP_LRCK I2S1_LRCK NO_TEST=TRUE
1.8V 22 IN GPIO_ALS_IRQ_L AK21 GPIO4
I2S1_SPKAMP_DIN M24 I2S1_DIN SWI_DATA AB27 NO_TEST=TRUE
NC_SWI_AP
19 IN AK24
N30 14 OUT GPIO_BT_WAKE GPIO5 TMR32_PWM0 V33 GPIO_GYRO_IRQ2 IN 22
19 OUT I2S1_SPKAMP_DOUT I2S1_DOUT
26 IN GPIO_AP_MODEM_WAKE AJ21 GPIO6 TMR32_PWM1 W31 GPIO_ACCEL_IRQ1_L IN 22
DWI_CLK T26 DWI_AP_CLK OUT 30 36
AK18
J29 26 OUT BB_JTAG_TMS_RF GPIO7 TMR32_PWM2 V27 NC_TMR32_PWM2_AP
NC_I2S2_MCK NO_TEST=TRUE
I2S2_MCK DWI_DI W32 DWI_AP_DI IN 30 36
AL26
NO_TEST=TRUE
39 26 OUT GPIO_BB_RST_L GPIO8
36 14 I2S2_BT_BCLK L29 I2S2_BCLK DWI_DO W28 DWI_AP_DO 30 36
OUT OUT AH25
L28 26 5 OUT GPIO_BB_RADIO_ON_L GPIO9 UART0_RXD K18 NC_UART0_RXD
BT 36 14 OUT I2S2_BT_LRCK I2S2_LRCK NO_TEST=TRUE
26 IN GPIO_BB_RESET_DET_L AJ18 GPIO10 UART0_TXD K19 NC_UART0_TXD
1.8V 36 14 IN I2S2_BT_DIN L26 I2S2_DIN NO_TEST=TRUE
22 IN GPIO_ACCEL_IRQ2_L AJ23 GPIO11
36 14 I2S2_BT_DOUT L25 I2S2_DOUT
OUT GPIO_BB_HSIC_RESUME AK23 AM27 UART1_BB_CTS_L
36 26 IN GPIO12 UART1_CTSN IN 26 36
36 14 5 OUT GPIO_WLAN_HSIC_HOST_RDY AJ20 GPIO13 UART1_RTSN AM28 UART1_BB_RTS_L OUT 26 36

NC_I2S3_MCK NO_TEST=TRUE L32 I2S3_MCK TO BB UART
20 IN GPIO_BTN_VOL_DOWN_L AJ22 GPIO14 UART1_RXD AN27 UART1_BB_RXD IN 25 26 36
36 18 I2S3_CODEC_XSP_BCLK E29 I2S3_BCLK MDM9600
OUT GPIO_BB_GSM_TXBURST AJ24 AN28 UART1_BB_TXD
K32 26 IN GPIO15 UART1_TXD OUT 25 26 36
36 18 OUT I2S3_CODEC_XSP_LRCK I2S3_LRCK
L81 CODEC XSP 10 IN GPIO_BOARD_ID_3 AL25 GPIO16
36 18 I2S3_CODEC_XSP_DIN J25 I2S3_DIN
1.8V IN PMU_GPIO_TS_INT AM26 Y30 BB_JTAG_TCK_RF
M30 30 25 IN GPIO17 UART2_CTSN OUT 26
36 18 OUT I2S3_CODEC_XSP_DOUT I2S3_DOUT
10 IN GPIO_BOOT_CONFIG_0 AK25 GPIO18 UART2_RTSN AC27 NC_UART2_RTSN
NO_TEST=TRUE
26 OUT GPIO_BB_GPS_SYNC AN26 GPIO19 UART2_RXD AC33 UART2_TS_ACC_RXD IN 25 36
NC_I2S4_MCK NO_TEST=TRUE F31 I2S4_MCK TO TRISTAR
22 IN GPIO_PROX_IRQ_L F26 GPIO20 UART2_TXD AD33 UART2_TS_ACC_TXD OUT 25 36
NC_I2S4_BCLK NO_TEST=TRUE H25 I2S4_BCLK 1.8V
22 IN GPIO_GYRO_IRQ1 E26 GPIO21
NOT USED NC_I2S4_LRCK NO_TEST=TRUE K28 I2S4_LRCK
GPIO_PMU_KEEPACT J31 GPIO22 UART3_CTSN AB32 UART3_BT_CTS_L
NC_I2S4_DIN NO_TEST=TRUE K31 30 5 OUT IN 14 36
I2S4_DIN F29 AC30
J32 30 IN GPIO_PMU_IRQ_L GPIO23 UART3_RTSN UART3_BT_RTS_L OUT 14 36
NC_I2S4_DOUT NO_TEST=TRUE
I2S4_DOUT TO BT UART
36 14 IN GPIO_WLAN_HSIC_DEV_RDY E30 GPIO24 UART3_RXD AC32 UART3_BT_RXD IN 14 36
H31 AD32 BCM4330
GPIO_BOOT_CONFIG_1 GPIO25 UART3_TXD UART3_BT_TXD
C C
NC_AP_GPIO216 NO_TEST=TRUE K29 SPDIF 10 IN OUT 14 36
32 5 IN GPIO_FORCE_DFU J30 GPIO26 NO_TEST=TRUE

5 OUT GPIO_DFU_STATUS H32 GPIO27 UART4_CTSN Y27 NC_UART4_CTS_L
10 GPIO_BOARD_ID_2 Y31 SPI0_MISO NO_TEST=TRUE
IN GPIO_BOOT_CONFIG_2 G27 AA29 NC_UART4_RTC_L
V28 10 IN GPIO28 UART4_RTSN
10 IN GPIO_BOARD_ID_1 SPI0_MOSI
10 IN GPIO_BOOT_CONFIG_3 E27 GPIO29 UART4_RXD AB31 UART4_WLAN_RXD IN 14 36
GPIO_BOARD_ID_0 V32 SPI0_SCLK WIFI DEBUG
10 IN GPIO_BTN_SRL_L F32 AC31 UART4_WLAN_TXD
V29 30 20 5 IN GPIO30 UART4_TXD OUT 14 36
TP_SPI0_SSIN SPI0_SSIN
16 5 IN GPIO_GRAPE_IRQ_L J28 GPIO31
14 IN GPIO_WL_HSIC_RESUME G31 GPIO32 UART5_RXD J18 UART5_BATTERY_TRXD OUT 28 30
36 18 IN SPI1_CODEC_MISO AB29 SPI1_MISO
19 5 OUT GPIO_SPKAMP_RST_L G32 GPIO33 UART5_TXD K17 NC_UART5_TXD 35
36 18 OUT SPI1_CODEC_MOSI Y29 SPI1_MOSI NO_TEST=TRUE
19 5 OUT GPIO_SPKAMP_KEEPALIVE G28 GPIO34
36 18 OUT SPI1_CODEC_SCLK AA28 SPI1_SCLK
19 GPIO_SPKAMP_RIGHT_IRQ_L G33 GPIO35 UART6_CTSN AC28 NC_UART6_CTSN
SPI1_CODEC_CS_L AA32 IN NO_TEST=TRUE
36 18 OUT SPI1_SSIN J26 W30
15 OUT PM_LCDVDD_PWREN GPIO36 UART6_RTSN NC_UART6_RTSN
NO_TEST=TRUE
19 IN GPIO_SPKAMP_LEFT_IRQ_L G30 GPIO37 UART6_RXD AA30 UART6_AP_RXD IN 25 36
USED FOR DEBUG BB_JTAG_TRST_RF_L AB28 SPI2_MISO TO TRISTAR
AND SW UPDATE 26 IN SPK_ID G29 AA31 UART6_AP_TXD
AB33 SPI2_MOSI 19 IN GPIO38 UART6_TXD OUT 25 36
1.8V
OS CURRENTLY SUPPORTS 26 OUT BB_JTAG_TDI_RF
USB1.1 FOR DEBUG. 18 IN GPIO_CODEC_IRQ_L F27 GPIO39
26 IN BB_JTAG_TDO_RF AC29 SPI2_SCLK
TO BB GPIO_SVSEL18_FMI H27 =PP1V8_H5
1.8V IO 36 26 OUT GPIO_BB_HSIC_HOST_RDY W33 SPI2_SSIN H19
4 5 7 10 34
16 OUT GPIO_GRAPE_FW_DNLD_EN_L GPIO_3V0 GPIO_SVSEL25_FMI G25
GPIO_GRAPE_RST_L J19 1 1
1 SPI3_GRAPE_MISO D19 16 OUT GPIO_3V1 R0716 R0717
R0720 36 16 IN SPI3_MISO
GRAPE GPIO_VSEL25_I2C2 E31 100K 100K
100K 36 16 OUT SPI3_GRAPE_MOSI G20 SPI3_MOSI 3.0V 5% 5%
5% E19 GPIO_VSEL25_SPI3 H29 1/20W 1/20W
1/20W 36 16 OUT SPI3_GRAPE_SCLK SPI3_SCLK MF MF
MF F19 2 201 2 201
201 2 36 16 OUT SPI3_GRAPE_CS_L SPI3_SSIN
GPIO_VSEL25_I2C2
GPIO_VSEL25_SPI3
VSEL18_FMI AND VSEL25_FMI LOW => FMI CHANNEL AT 1.8V

VSEL25_I2C2 HIGH => I2C2 3.0V
VSEL25_SPI3 HIGH => SPI3 3.0V
B B
34 10 7 5 4 =PP1V8_H5
NOSTUFF
1
R0760
100K
5%
1/20W
MF
2 201
16 5 GPIO_GRAPE_IRQ_L
BUTTON PULLUPS
I2C PULL-UPS
R0708
220K 2 NEED TO CHARACTERIZE RISE TIME
34 32 5 =PP1V8_S2R_MISC 1 GPIO_PMU_KEEPACT
5%
5 30
AND SIZE THESE RESISTORS
1/20W GPIO_FORCE_DFU 5 32
MF GPIO_DFU_STATUS 21 20 PP3V0_SENSOR_FLT
201 5
30 23 5 GPIO_BTN_HOME_L GPIO_BB_RADIO_ON_L 5 26 34 10 7 5 4 =PP1V8_H5
R0709 GPIO_WLAN_HSIC_HOST_RDY 5 14 36
1 1 1 1 1 1
220K 2 GPIO_SPKAMP_RST_L 5 19
R0701 R0702 R0703 R0704 R0705 R0706
34 =PP1V8_ALWAYS 1 2.2K 2.2K 1.00K 1.00K 1.00K 1.00K
GPIO_SPKAMP_KEEPALIVE 5% 5% 5% 5% 5% 5%
5% 5 19
1/32W 1/32W 1/32W 1/32W 1/32W 1/32W
1/20W MF MF MF MF MF MF
MF 2 01005 2 01005 2 01005 2 01005 2 01005 2 01005
201
A 30 20 5 GPIO_BTN_ONOFF_L
R0710 NOSTUFF NOSTUFF
36 30 25 19 5 I2C0_SDA_1V8 SYNC_MASTER=N/A SYNC_DATE=N/A A
1 1 1 1 1 1 1 PAGE TITLE
220K 2 R0711 R0713 R0714 R0715 R0718 R0719 R0721
34 32 5 =PP1V8_S2R_MISC 1
5%
100K
5%
100K
5%
100K
5%
100K
5%
100K
5%
100K
5%
100K
5%
36 30 25 19 5 I2C0_SCL_1V8 AP: I/Os
1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 1/20W 36 22 5 I2C1_SDA_1V8 DRAWING NUMBER SIZE
MF MF MF MF MF MF MF
MF
201 2 201 2 201 2 201 2 201 2 201 2 201 2 201 I2C1_SCL_1V8 Apple Inc. 051-9385 D
30 20 5 GPIO_BTN_SRL_L 36 22 5
REVISION
36 22 5 I2C2_SDA_3V0 R
A.0.0
36 22 5 I2C2_SCL_3V0 NOTICE OF PROPRIETARY PROPERTY: BRANCH
7 OF 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
34 9 6 =PP1V8_NAND_H5
AB8 AH5
1
AB10 U0600 AH10 R0832 1
R0831
AB12 BALI-H5G AH15 100K 100K
5% 5%
AB14 BGA AH16 1/32W 1/32W
SYM 12 OF 12 MF MF
AB16 AH17 2 01005 2 01005
AB18 OMIT_TABLE AH30
38 13 6 FMI1_CE0_L
AB19 AH32
AB21 P24 FMI0_CE0_L
38 13 6
AB23 AJ17
AB25 AJ27
AB30 AK2
AC1 AK8
AC3 AK14
AC9 AK17
AC11 AH1
AC13 AL3
AC15 AL7
AC17 AL10
C AC20 AL13 C
AC22 AL16
AC24 AL17
VSS
AD8 AL18
38 13 6 OUT FMI0_CE0_L AN29 FMI0_CEN0 FMI1_CEN0 AF29 FMI1_CE0_L OUT 6 13 38
AD10 AL19
VSS NC_FMI0_CE1_L NO_TEST=TRUE AM30 FMI0_CEN1 U0600 FMI1_CEN1 AF30 NO_TEST=TRUE NC_FMI1_CE1_L
AD12 AL20
NC_FMI0_CE2_L NO_TEST=TRUE AL28 FMI0_CEN2 BALI-H5G FMI1_CEN2 AE29 NO_TEST=TRUE NC_FMI1_CE2_L
AD14 AL21
NC_FMI0_CE3_L NO_TEST=TRUE AL27 FMI0_CEN3 BGA FMI1_CEN3 AD30 NO_TEST=TRUE NC_FMI1_CE3_L
AD16 AL22 SYM 4 OF 12
NC_FMI0_CE4_L NO_TEST=TRUE AJ32 FMI0_CEN4 FMI1_CEN4 AF27 NO_TEST=TRUE NC_FMI1_CE4_L
AD18 AL23
NC_FMI0_CE5_L NO_TEST=TRUE AJ31 FMI0_CEN5 OMIT_TABLE FMI1_CEN5 AE27 NO_TEST=TRUE NC_FMI1_CE5_L
AD19 AL24
NC_FMI0_CE6_L NO_TEST=TRUE AM31 FMI0_CEN6 FMI1_CEN6 AF28 NO_TEST=TRUE NC_FMI1_CE6_L
AD21 AL1
NC_FMI0_CE7_L NO_TEST=TRUE AL30 FMI0_CEN7 FMI1_CEN7 AE28 NO_TEST=TRUE NC_FMI1_CE7_L
AD23 AL29
AD25 AM1
38 13 BI FMI0_AD<0> AM29 FMI0_IO0 FMI1_IO0 AE33 FMI1_AD<0> BI 13 38
AE4 AM2
38 13 BI FMI0_AD<1> AK33 FMI0_IO1 FMI1_IO1 AH33 FMI1_AD<1> BI 13 38
AE9 AM6
38 13 BI FMI0_AD<2> AJ30 FMI0_IO2 FMI1_IO2 AG33 FMI1_AD<2> BI 13 38
AE10 AM9
38 13 BI FMI0_AD<3> AK31 FMI0_IO3 FMI1_IO3 AG30 FMI1_AD<3> BI 13 38
AE11 AM12
FMI0_AD<4> AH28 FMI0_IO4 FMI1_IO4 AD31 FMI1_AD<4>
AE12 AM15 38 13 BI BI 13 38
FMI0_AD<5> AJ29 FMI0_IO5 FMI1_IO5 AE31 FMI1_AD<5>

AE13 AM32 38 13 BI BI 13 38
38 13 FMI0_AD<6> AN30 FMI0_IO6 FMI1_IO6 AG29 FMI1_AD<6> 13 38

AE14 AM33 BI BI
38 13 BI FMI0_AD<7> AH27 FMI0_IO7 FMI1_IO7 AD29 FMI1_AD<7> BI 13 38
AE15 AN1
AE17 AN2 CKPLUS_WAIVE=PDIFPR_BADTERM CKPLUS_WAIVE=PDIFPR_BADTERM
NC_FMI0_RE NO_TEST=TRUE AK29 FMI0_WENN FMI1_WENN AG31 NO_TEST=TRUE NC_FMI1_RE
AE22 AL33
38 13 OUT FMI0_ALE AJ28 FMI0_ALE FMI1_ALE AJ33 FMI1_ALE OUT 13 38
AE30 T20
FMI0_CLE AH29 FMI0_CLE FMI1_CLE AH31 FMI1_CLE
AE32 AN11 38 13 OUT OUT 13 38
38 13 FMI0_WE_L AK32 FMI0_WEN FMI1_WEN AG32 FMI1_WE_L 13 38

A6 AN14 OUT OUT
B AF3
AF16
AN32
AN33
38 13
38 13
OUT
OUT
FMI0_RE_L
FMI0_DQS
AK30
AL31
FMI0_REN
FMI0_DQS
FMI1_REN
FMI1_DQS
AF31
AF32
FMI1_RE_L
FMI1_DQS
OUT
OUT
13 38
13 38 =PP1V8_NAND_H5 6 9 34
B
NC_FMI0_DQSN NO_TEST=TRUE AL32 FMI0_DQSN FMI1_DQSN AF33 NO_TEST=TRUE NC_FMI1_DQSN
AG2 AN3
AG27 FMI0_DQVREF FMI1_DQVREF AD27
AG16 AN31
1
AG17 AN6 R0842 1 C0842
AG25 C1 34 9 6 =PP1V8_NAND_H5 AF26 PVDDP_GRP1 PVDDP_GRP3 P25 =PP1V8_VDDIO18_H5 4 6 7 9 34 51.1K 0.1UF
AB26 1% 20%
PVDDP_GRP2 PVDDP_GRP4 G19 1/32W 2 4V
MF X5R
PVDDP_GRP5 K24 2 01005 01005
6 FMI_DQVREF_H5 AG28 FMI0_VREF FMI1_VREF AD28 6 FMI_DQVREF_H5
1
R0843
51.1K 1 C0843
1% 0.1UF
1/32W 20%
MF 2 4V
X5R
2 01005 01005
34 9 6 =PP1V8_NAND_H5 34 9 7 6 4 =PP1V8_VDDIO18_H5
1 C0820 1 C0821 1 C0810 1 C0811 1 C0812
A 2 4V
0.1UF
20%
X5R 2 4V
0.1UF
20%
X5R
0.1UF
20%
4V
20%
4V
0.1UF 0.1UF
20%
4V
SYNC_MASTER=N/A SYNC_DATE=N/A A
01005 01005 2 X5R 2 X5R 2 X5R PAGE TITLE
01005 01005 01005
AP: NAND
DRAWING NUMBER SIZE

REVISION
R
A.0.0
8 OF 154
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
34 =PP1V0_DP_PAD_DVDD_H5
1 C0910
8.2PF
+/-0.1PF%
25V
2 CER
0201 =PP1V8_DP_H5 34
R0911 1 C0927 1 C0924

0
34 =PP1V8_EDP_H5 1 2 39 PP1V8_EDP_AVDD_AUX 0.1UF 56PF
20% 5%
5%
1 C0931 1/20W 1 C0928 1 C0929 1 C0930 1 C0932 1 C0933 1 C0934 2 4V
X5R 2 6.3V
NP0-C0G
MF 01005 01005
56PF 201 8.2PF 8.2PF 56PF 0.22UF 0.22UF 0.22UF
5% +/-0.5PF +/-0.5PF 5% 20% 20% 20%
D
2 6.3V
NP0-C0G
01005
2 16V
01005
2 16V
NP0-C0G-CERM
01005
2 6.3V
NP0-C0G-CERM NP0-C0G
01005
2 6.3V
X5R
402
2 6.3V
X5R
402
2 6.3V
X5R
402 =PP1V8_VDDIO18_H5 4 6 7 9 34 D
1 C0953
0.01UF
=PP1V0_EDP_PAD_DVDD_H5 10%
2 6.3V
34
X5R
01005
1 C0909
0.1UF
10% =PP1V8_VDDIO18_H5 4
2 6.3V
6 7 9 34
X5R VOLTAGE=1.8V
201 MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR 1 C0951 1 C0952
MAX_NECK_LENGTH=3MM 0.1UF 0.01UF
20% 10%
NOSTUFF 2 4V
X5R 2 6.3V
X5R
FL0911
15MA EDP_PAD_DVDD C31
EDP_PAD_AVDDX B31
EDP_PAD_AVDDP0 D29
D25
D26
C27
C28
16MA EDP_PAD_AVDD_AUX D30
15MA DP_PAD_DVDD C24
22MA DP_PAD_AVDDX C23
10MA DP_PAD_AVDDP0 D21
A20
B20
E20
E21
16MA DP_PAD_AVDD_AUX D22
15MA DAC_AVDD18D H23
15MA DAC_AVDD18A H24

01005 01005
240-OHM-0.2A-0.8-OHM
EDP_PAD_AVDD3
EDP_PAD_AVDD2
EDP_PAD_AVDD1
EDP_PAD_AVDD0
DP_PAD_AVDD3
DP_PAD_AVDD2
DP_PAD_AVDD1
DP_PAD_AVDD0
34 9 7 6 4 =PP1V8_VDDIO18_H5 1 2 DAC_AP_COMP_FTR
0201
NOSTUFF
TABLE_ALT_HEAD

PART NUMBER 1 C0956
TABLE_ALT_ITEM
0.1UF
155S0725 155S0359 ? FL0910 RDAR://PROBLEM/11104943 10% 65MA
2 6.3V 65MA PER PIN
22MA
X5R PER PIN
10MA
NOSTUFF NOSTUFF 201
1
1 C0955 R0950 39 DAC_AP_VREF J23 DAC_VREF U0600 DAC_OUT3 D33 NO_TEST=TRUE NC_DAC_AP_OUT3
0.1UF 6.34K BALI-H5G
10% 1%
1/20W DAC_AP_IREF J24 DAC_IREF BGA DAC_OUT2 E33 NC_DAC_AP_OUT2
2 6.3V
NO_TEST=TRUE
X5R MF SYM 6 OF 12
201 2 201
DAC_AP_COMP K23 DAC_COMP OMIT_TABLE DAC_OUT1 F33 NO_TEST=TRUE NC_DAC_AP_OUT1
C VOLTAGE=1.0V =PP1V8_MIPI_H5 34
37 15 IN EDP_HPD E18 EDP_HPD DP_HPD B18 NO_TEST=TRUE NC_DP_HPD C
MIN_LINE_WIDTH=0.2MM
FL0910 MIN_NECK_WIDTH=0.1MM
EDP_AUX_P C30 EDP_PAD_AUXP DP_PAD_AUXP A26 NC_DP_AUX_P
80-OHM-0.2A-0.4-OHM NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM
1 C0907 37 15 OUT
NO_TEST=TRUE
0.1UF 37 15 OUT EDP_AUX_N C29 EDP_PAD_AUXN DP_PAD_AUXN A25 NO_TEST=TRUE NC_DP_AUX_N

34 =PP1V0_MIPI_PLL_H5 1 2 39 PP1V0_MIPI_PLL_F 10%
6.3V
0201-1 2 X5R
201 37 15 OUT EDP_DATA_P<0> A30 EDP_PAD_TX0P DP_PAD_TX0P D24 NO_TEST=TRUE NC_DP_DATA_P<0>
1 C0980 1 C0981 1 C0982 VOLTAGE=0.4V
37 15 OUT EDP_DATA_N<0> A29 EDP_PAD_TX0N DP_PAD_TX0N D23 NO_TEST=TRUE NC_DP_DATA_N<0>
1UF 0.01UF 56PF MIN_NECK_WIDTH=0.1MM
10% 10% 5% PP0V4_MIPI0D NET_SPACING_TYPE=PWR
2 6.3V
CERM 2 6.3V
X5R 2 6.3V
NP0-C0G MAX_NECK_LENGTH=3MM 37 15 OUT EDP_DATA_P<1> D28 EDP_PAD_TX1P DP_PAD_TX1P B24 NO_TEST=TRUE NC_DP_DATA_P<1>
402 01005 01005 EDP_DATA_N<1> D27 EDP_PAD_TX1N DP_PAD_TX1N B23 NO_TEST=TRUE NC_DP_DATA_N<1>
1 C0960 37 15 OUT
2.2NF
10% EDP_DATA_P<2> B28 EDP_PAD_TX2P DP_PAD_TX2P C22 NO_TEST=TRUE NC_DP_DATA_P<2>
2 10V OUT
37 15
X5R-CERM EDP_DATA_N<2> B27 EDP_PAD_TX2N DP_PAD_TX2N C21 NO_TEST=TRUE NC_DP_DATA_N<2>
0201 37 15 OUT
34 =PP1V0_MIPI_H5 VOLTAGE=0.4V
MIN_LINE_WIDTH=0.2MM 37 15 OUT EDP_DATA_P<3> C26 EDP_PAD_TX3P DP_PAD_TX3P A22 NO_TEST=TRUE NC_DP_DATA_P<3>
MIN_NECK_WIDTH=0.1MM EDP_DATA_N<3> C25 EDP_PAD_TX3N DP_PAD_TX3N A21 NO_TEST=TRUE NC_DP_DATA_N<3>
1 C0935 1 C0908 1 C0903 1 C0904 PP0V4_MIPI1D NET_SPACING_TYPE=PWR 37 15 OUT
MAX_NECK_LENGTH=3MM NOTE: 0.6V ANALOG REF
1UF 0.1UF 0.1UF 8.2PF
10%
2 6.3V
10%
2 6.3V
10%
2 6.3V
+/-0.5PF
2 16V
1 C0961 AP_EDP_R_BIAS E28 EDP_PAD_R_BIAS DP_PAD_R_BIAS E23 DP_R_BIAS
CERM X5R X5R NP0-C0G-CERM 2.2NF NOSTUFF NOTE: 0.6V ANALOG REF NOSTUFF
402 201 201 01005 10% 1 1
2 10V 1 C0957 R0921 F28 EDP_PAD_DC_TP DP_PAD_DC_TP F23 TP_DP_AP_ANALOG_TEST R0920 1 C0950
AF20
AF21
AF22
AF23
AF24
MIPI0D_VDD10_PLL AH21
MIPI1D_VDD10_PLL AH22
MIPI0D_VDD18 AH19
MIPI1D_VDD18 AH24
MIPI0D_VREG_0P4V AH20
MIPI1D_VREG_0P4V AH23
X5R-CERM 4.99K 4.99K

0201 0.01UF 0.01UF
B30 EDP_PAD_AVSS_AUX
10% 1% 1% 10%
B22 DP_PAD_AVSS_AUX
1/32W 1/32W
2 6.3V 6.3V
B29 EDP_PAD_AVSSP0
X5R MF MF 2 X5R
EDP_PAD_AVSS3
EDP_PAD_AVSS2
EDP_PAD_AVSS1
EDP_PAD_AVSS0
C32 EDP_PAD_AVSSX
B21 DP_PAD_AVSSP0
01005 2 01005 2 01005 01005
D31 EDP_PAD_DVSS
A23 DP_PAD_AVSSX
DP_PAD_AVSS3
DP_PAD_AVSS1
DP_PAD_AVSS2
DP_PAD_AVSS0
40MA MIPI_VDD10
A24 DP_PAD_DVSS
G23 DAC_AVSS18D
G24 DAC_AVSS18A
=PP1V8_H5 4 5 7 10 34
1 1 1 1
R0930 R0931 R0932 R0933
B 1.00K
5%
1/32W
1.00K
5%
1/32W
1.00K
5%
1/32W
1.00K
5%
1/32W
TP_EDP_AP_ANALOG_TEST B
3.3MA
3.3MA
2MA MF MF MF MF
PER PIN 2 01005 2 01005 2 01005 2 01005
B25
B26
A27
A28
C20
F20
D20
F21
NC_MIPI_VSYNC_H5 NO_TEST=TRUE U27 MIPI_VSYNC U0600 ISP0_FLASH M25 ISP0_CAM_RF_RST_L OUT 22
BALI-H5G ISP0_PRE_FLASH M31 NO_TEST=TRUE NC_ISP0_CAM_RF_FLASH

MIPI0C_CAM_RF_DATA_P<0> AM22 MIPI0C_DPDATA0 BGA ISP0_SCL AA27 ISP0_CAM_RF_I2C_SCL OUT
37 21 IN 22 36
AN22 MIPI0C_DNDATA0 SYM 5 OF 12 U28
37 21 IN MIPI0C_CAM_RF_DATA_N<0> ISP0_SDA ISP0_CAM_RF_I2C_SDA BI 22 36
OMIT_TABLE REAR FACING CAM
MIPI0C_CAM_RF_DATA_P<1> AM21 MIPI0C_DPDATA1 ISP1_FLASH N25 SOCHOT1_L
37 21 IN 7 32
MIPI0C_CAM_RF_DATA_N<1> AN21 MIPI0C_DNDATA1 ISP1_PRE_FLASH L30 SOCHOT0_L

37 21 IN 7
FRONT FACING CAM
ISP1_SCL AA33 ISP1_CAM_FF_I2C_SCL 22 36
OUT
NC_MIPI0C_CAM_RF_DATA_P<2> NO_TEST=TRUE AM19 MIPI0C_DPDATA2 ISP1_SDA U30 ISP1_CAM_FF_I2C_SDA BI 22 36
NC_MIPI0C_CAM_RF_DATA_N<2> NO_TEST=TRUE AN19 MIPI0C_DNDATA2

0.00 2 R0900
36 V31 ISP0_CAM_RF_CLK_R
SENSOR0_CLK 1
0% MF ISP0_CAM_RF_CLK
1/32W 01005 OUT 22 36
NC_MIPI0C_CAM_RF_DATA_P<3> NO_TEST=TRUE AM18 MIPI0C_DPDATA3 SENSOR0_RST U32 ISP0_CAM_RF_SHUTDOWN OUT 22

SHUTDOWN IS ACTIVE HIGH
NC_MIPI0C_CAM_RF_DATA_N<3> NO_TEST=TRUE AN18 MIPI0C_DNDATA3
U31
0.00 2 R0940
SENSOR1_CLK
36 ISP1_CAM_FF_CLK_R 1
0% MF ISP1_CAM_FF_CLK OUT 22 36
1/32W 01005
MIPI0C_CAM_RF_CLK_P AM20 MIPI0C_DPCLK SENSOR1_RST T27 ISP1_CAM_FF_SHUTDOWN_L
37 21 IN OUT 22
SHUTDOWN IS ACTIVE LOW
MIPI0C_CAM_RF_CLK_N AN20 MIPI0C_DNCLK
37 21 IN =PP1V8_H5 4 5 7 10 34
MIPI1C_DPDATA0 AM23 MIPI1C_CAM_FF_DATA_P<0> IN 21 37
MIPI1C_DNDATA0 AN23 MIPI1C_CAM_FF_DATA_N<0> NOSTUFF

IN 21 37
1 1
R0942 R0941
MIPI1C_DPDATA1 AM25 NO_TEST=TRUE NC_MIPI1C_CAM_FF_DATA_P<1> 100K 100K
5% 5%
MIPI1C_DNDATA1 AN25 NO_TEST=TRUE NC_MIPI1C_CAM_FF_DATA_N<1> 1/32W 1/32W
MIPI_VSS
MF MF
2 01005 2 01005
A MIPI1C_DPCLK AM24 MIPI1C_CAM_FF_CLK_P IN 21 37
SOCHOT1_L PULL-UP ON CSA 90
MIPI1C_DNCLK AN24 MIPI1C_CAM_FF_CLK_N IN 21 37 32 7 SOCHOT1_L PAGE TITLE
7 SOCHOT0_L AP: TV,DP,MIPI

AG20
AG21
AG22
AG23
AG24
DRAWING NUMBER SIZE

REVISION
R
A.0.0
9 OF 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
38 11 BI DDR0_DQ<0> B14 DDR0_DQ0 U0600 DDR1_DQ0 H2 DDR1_DQ<0> BI 11 38 38 12 BI DDR2_DQ<0> AB2 DDR2_DQ0 DDR3_DQ0 AL8 DDR3_DQ<0> BI 12 38
38 11 BI DDR0_DQ<1> B13 DDR0_DQ1 BALI-H5G DDR1_DQ1 H3 DDR1_DQ<1> BI 11 38 38 12 BI DDR2_DQ<1> AB3 DDR2_DQ1 U0600 DDR3_DQ1 AL9 DDR3_DQ<1> BI 12 38
DDR0_DQ<2> D13 DDR0_DQ2 BGA DDR1_DQ2 J3 DDR1_DQ<2> DDR2_DQ<2> AC2 DDR2_DQ2 BALI-H5G DDR3_DQ2 AK9 DDR3_DQ<2>
38 11 BI BI 11 38 38 12 BI BI 12 38
C12 SYM 7 OF 12 J4 AC4 BGA AJ9
38 11 BI DDR0_DQ<3> DDR0_DQ3 DDR1_DQ3 DDR1_DQ<3> BI 11 38 38 12 BI DDR2_DQ<3> DDR2_DQ3 DDR3_DQ3 DDR3_DQ<3> BI 12 38
D12 OMIT_TABLE K2 AD2 SYM 8 OF 12 AM10
B11 L2 AD3 OMIT_TABLE AJ10
DDR0_DQ<5> DDR1_DQ<5> DDR2_DQ<5> DDR3_DQ<5>
D
38 11
38 11
BI
BI DDR0_DQ<6> C11
B10
DDR0_DQ5
DDR0_DQ6
DDR1_DQ5
DDR1_DQ6 K4
K5
DDR1_DQ<6>
BI
BI
11 38
11 38
38 12
38 12
BI
BI DDR2_DQ<6> AE2
AE3
DDR2_DQ5
DDR2_DQ6
DDR3_DQ5
DDR3_DQ6 AK10
AL11
DDR3_DQ<6>
BI
BI
12 38
12 38 D
38 11 BI DDR0_DQ<8> C9 DDR0_DQ8 DDR1_DQ8 N2 DDR1_DQ<8> BI 11 38 38 12 BI DDR2_DQ<8> AF2 DDR2_DQ8 DDR3_DQ8 AM11 DDR3_DQ<8> BI 12 38
38 11 BI DDR0_DQ<9> D9 DDR0_DQ9 DDR1_DQ9 P2 DDR1_DQ<9> BI 11 38 38 12 BI DDR2_DQ<9> AF4 DDR2_DQ9 DDR3_DQ9 AL12 DDR3_DQ<9> BI 12 38
38 11 DDR0_DQ<10> B8 DDR0_DQ10 DDR1_DQ10 P3 DDR1_DQ<10> 11 38 38 12 DDR2_DQ<10> AG5 DDR2_DQ10 DDR3_DQ10 AK12 DDR3_DQ<10> 12 38
BI BI BI BI
38 11 BI DDR0_DQ<11> C8 DDR0_DQ11 DDR1_DQ11 R3 DDR1_DQ<11> BI 11 38 38 12 BI DDR2_DQ<11> AH2 DDR2_DQ11 DDR3_DQ11 AJ12 DDR3_DQ<11> BI 12 38
38 11 BI DDR0_DQ<12> B7 DDR0_DQ12 DDR1_DQ12 T2 DDR1_DQ<12> BI 11 38 38 12 BI DDR2_DQ<12> AJ2 DDR2_DQ12 DDR3_DQ12 AM13 DDR3_DQ<12> BI 12 38
38 11 BI DDR0_DQ<13> B6 DDR0_DQ13 DDR1_DQ13 R4 DDR1_DQ<13> BI 11 38 38 12 BI DDR2_DQ<13> AG3 DDR2_DQ13 DDR3_DQ13 AK13 DDR3_DQ<13> BI 12 38
38 11 BI DDR0_DQ<14> C6 DDR0_DQ14 DDR1_DQ14 T3 DDR1_DQ<14> BI 11 38 38 12 BI DDR2_DQ<14> AH3 DDR2_DQ14 DDR3_DQ14 AJ13 DDR3_DQ<14> BI 12 38
38 11 BI DDR0_DQ<15> D7 DDR0_DQ15 DDR1_DQ15 T4 DDR1_DQ<15> BI 11 38 38 12 BI DDR2_DQ<15> AJ3 DDR2_DQ15 DDR3_DQ15 AJ14 DDR3_DQ<15> BI 12 38
38 11 BI DDR0_DQ<16> B17 DDR0_DQ16 DDR1_DQ16 C2 DDR1_DQ<16> BI 11 38 38 12 BI DDR2_DQ<16> W2 DDR2_DQ16 DDR3_DQ16 AM5 DDR3_DQ<16> BI 12 38
38 11 BI DDR0_DQ<17> C17 DDR0_DQ17 DDR1_DQ17 D2 DDR1_DQ<17> BI 11 38 38 12 BI DDR2_DQ<17> W4 DDR2_DQ17 DDR3_DQ17 AL6 DDR3_DQ<17> BI 12 38
38 11 DDR0_DQ<18> B16 DDR0_DQ18 DDR1_DQ18 E2 DDR1_DQ<18> 11 38 38 12 DDR2_DQ<18> Y2 DDR2_DQ18 DDR3_DQ18 AK6 DDR3_DQ<18> 12 38
BI BI BI BI
38 11 BI DDR0_DQ<19> E17 DDR0_DQ19 DDR1_DQ19 E4 DDR1_DQ<19> BI 11 38 38 12 BI DDR2_DQ<19> Y3 DDR2_DQ19 DDR3_DQ19 AJ6 DDR3_DQ<19> BI 12 38
38 11 BI DDR0_DQ<20> D16 DDR0_DQ20 DDR1_DQ20 E3 DDR1_DQ<20> BI 11 38 38 12 BI DDR2_DQ<20> Y4 DDR2_DQ20 DDR3_DQ20 AM7 DDR3_DQ<20> BI 12 38
38 11 DDR0_DQ<21> E16 DDR0_DQ21 DDR1_DQ21 F3 DDR1_DQ<21> 11 38 38 12 DDR2_DQ<21> AA3 DDR2_DQ21 DDR3_DQ21 AK7 DDR3_DQ<21> 12 38
BI BI BI BI
38 11 BI DDR0_DQ<22> C15 DDR0_DQ22 DDR1_DQ22 F4 DDR1_DQ<22> BI 11 38 38 12 BI DDR2_DQ<22> AA4 DDR2_DQ22 DDR3_DQ22 AJ7 DDR3_DQ<22> BI 12 38
38 11 BI DDR0_DQ<23> D15 DDR0_DQ23 DDR1_DQ23 G2 DDR1_DQ<23> BI 11 38 38 12 BI DDR2_DQ<23> AA5 DDR2_DQ23 DDR3_DQ23 AM8 DDR3_DQ<23> BI 12 38
38 11 BI DDR0_DQ<24> E6 DDR0_DQ24 DDR1_DQ24 U3 DDR1_DQ<24> BI 11 38 38 12 BI DDR2_DQ<24> AK3 DDR2_DQ24 DDR3_DQ24 AM14 DDR3_DQ<24> BI 12 38
DDR0_DQ<25> B5 DDR0_DQ25 DDR1_DQ25 V2 DDR1_DQ<25> DDR2_DQ<25> AL2 DDR2_DQ25 DDR3_DQ25 AL14 DDR3_DQ<25>
38 11 BI BI 11 38 38 12 BI BI 12 38
38 11 BI DDR0_DQ<26> C5 DDR0_DQ26 DDR1_DQ26 V3 DDR1_DQ<26> BI 11 38 38 12 BI DDR2_DQ<26> AM3 DDR2_DQ26 DDR3_DQ26 AJ15 DDR3_DQ<26> BI 12 38
38 11 BI DDR0_DQ<27> E5 DDR0_DQ27 DDR1_DQ27 U5 DDR1_DQ<27> BI 11 38 38 12 BI DDR2_DQ<27> AM4 DDR2_DQ27 DDR3_DQ27 AK15 DDR3_DQ<27> BI 12 38
38 11 BI DDR0_DQ<28> C4 DDR0_DQ28 DDR1_DQ28 V4 DDR1_DQ<28> BI 11 38 38 12 BI DDR2_DQ<28> AL4 DDR2_DQ28 DDR3_DQ28 AL15 DDR3_DQ<28> BI 12 38
38 11 BI DDR0_DQ<29> D4 DDR0_DQ29 DDR1_DQ29 V5 DDR1_DQ<29> BI 11 38 38 12 BI DDR2_DQ<29> AL5 DDR2_DQ29 DDR3_DQ29 AJ16 DDR3_DQ<29> BI 12 38
38 11 BI DDR0_DQ<30> B3 DDR0_DQ30 DDR1_DQ30 U6 DDR1_DQ<30> BI 11 38 38 12 BI DDR2_DQ<30> AK5 DDR2_DQ30 DDR3_DQ30 AK16 DDR3_DQ<30> BI 12 38
38 11 BI DDR0_DQ<31> C3 DDR0_DQ31 DDR1_DQ31 V6 DDR1_DQ<31> BI 11 38 38 12 BI DDR2_DQ<31> AJ5 DDR2_DQ31 DDR3_DQ31 AM16 DDR3_DQ<31> BI 12 38
C 38 11 OUT DDR0_CA<0> G5 DDR0_CA0 DDR1_CA0 E15 DDR1_CA<0> OUT 11 38 38 12 OUT DDR2_CA<0> AH6 DDR2_CA0 DDR3_CA0 W5 DDR3_CA<0> OUT 12 38
C
38 11 OUT DDR0_CA<1> G6 DDR0_CA1 DDR1_CA1 F15 DDR1_CA<1> OUT 11 38 38 12 OUT DDR2_CA<1> AG6 DDR2_CA1 DDR3_CA1 W6 DDR3_CA<1> OUT 12 38
38 11 OUT DDR0_CA<2> H5 DDR0_CA2 DDR1_CA2 F14 DDR1_CA<2> OUT 11 38 38 12 OUT DDR2_CA<2> AH7 DDR2_CA2 DDR3_CA2 Y5 DDR3_CA<2> OUT 12 38
38 11 OUT DDR0_CA<3> H6 DDR0_CA3 DDR1_CA3 E14 DDR1_CA<3> OUT 11 38 38 12 OUT DDR2_CA<3> AG7 DDR2_CA3 DDR3_CA3 Y6 DDR3_CA<3> OUT 12 38
38 11 OUT DDR0_CA<4> J5 DDR0_CA4 DDR1_CA4 F13 DDR1_CA<4> OUT 11 38 38 12 OUT DDR2_CA<4> AH8 DDR2_CA4 DDR3_CA4 AA6 DDR3_CA<4> OUT 12 38
38 11 OUT DDR0_CA<5> M5 DDR0_CA5 DDR1_CA5 E8 DDR1_CA<5> OUT 11 38 38 12 OUT DDR2_CA<5> AH11 DDR2_CA5 DDR3_CA5 AD6 DDR3_CA<5> OUT 12 38
38 11 OUT DDR0_CA<6> M6 DDR0_CA6 DDR1_CA6 F8 DDR1_CA<6> OUT 11 38 38 12 OUT DDR2_CA<6> AG11 DDR2_CA6 DDR3_CA6 AE5 DDR3_CA<6> OUT 12 38
38 11 OUT DDR0_CA<7> N6 DDR0_CA7 DDR1_CA7 F7 DDR1_CA<7> OUT 11 38 38 12 OUT DDR2_CA<7> AG12 DDR2_CA7 DDR3_CA7 AE6 DDR3_CA<7> OUT 12 38
38 11 OUT DDR0_CA<8> P5 DDR0_CA8 DDR1_CA8 E7 DDR1_CA<8> OUT 11 38 38 12 OUT DDR2_CA<8> AH12 DDR2_CA8 DDR3_CA8 AF6 DDR3_CA<8> OUT 12 38
38 11 OUT DDR0_CA<9> P6 DDR0_CA9 DDR1_CA9 F6 DDR1_CA<9> OUT 11 38 38 12 OUT DDR2_CA<9> AG13 DDR2_CA9 DDR3_CA9 AF5 DDR3_CA<9> OUT 12 38
38 11 OUT DDR0_DM<0> E12 DDR0_DM0 DDR1_DM0 L5 DDR1_DM<0> OUT 11 38 38 12 OUT DDR2_DM<0> AD4 DDR2_DM0 DDR3_DM0 AK11 DDR3_DM<0> OUT 12 38
38 11 DDR0_DM<1> E9 DDR0_DM1 DDR1_DM1 N5 DDR1_DM<1> 11 38 38 12 DDR2_DM<1> AG4 DDR2_DM1 DDR3_DM1 AG14 DDR3_DM<1> 12 38
OUT OUT OUT OUT
38 11 OUT DDR0_DM<2> C14 DDR0_DM2 DDR1_DM2 G4 DDR1_DM<2> OUT 11 38 38 12 OUT DDR2_DM<2> AB6 DDR2_DM2 DDR3_DM2 AJ8 DDR3_DM<2> OUT 12 38
38 11 OUT DDR0_DM<3> D6 DDR0_DM3 DDR1_DM3 R5 DDR1_DM<3> OUT 11 38 38 12 OUT DDR2_DM<3> AK4 DDR2_DM3 DDR3_DM3 AG15 DDR3_DM<3> OUT 12 38
38 11 BI DDR0_DQS_P<0> A13 DDR0_PDQS0 DDR1_PDQS0 G1 DDR1_DQS_P<0> BI 11 38 38 12 BI DDR2_DQS_P<0> AA1 DDR2_PDQS0 DDR3_PDQS0 AN7 DDR3_DQS_P<0> BI 12 38
38 11 BI DDR0_DQS_N<0> A12 DDR0_NDQS0 DDR1_NDQS0 H1 DDR1_DQS_N<0> BI 11 38 38 12 BI DDR2_DQS_N<0> AB1 DDR2_NDQS0 DDR3_NDQS0 AN8 DDR3_DQS_N<0> BI 12 38
38 11 DDR0_DQS_P<1> A7 DDR0_PDQS1 DDR1_PDQS1 N1 DDR1_DQS_P<1> 11 38 38 12 DDR2_DQS_P<1> AG1 DDR2_PDQS1 DDR3_PDQS1 AN13 DDR3_DQS_P<1> 12 38
BI BI BI BI
DDR0_DQS_N<1> A8 DDR0_NDQS1 DDR1_NDQS1 M1 DDR1_DQS_N<1> DDR2_DQS_N<1> AF1 DDR2_NDQS1 DDR3_NDQS1 AN12 DDR3_DQS_N<1>
38 11 BI BI 11 38 38 12 BI BI 12 38
DDR0_DQS_P<2> A16 DDR0_PDQS2 DDR1_PDQS2 D1 DDR1_DQS_P<2> DDR2_DQS_P<2> V1 DDR2_PDQS2 DDR3_PDQS2 AN4 DDR3_DQS_P<2>
38 11 BI BI 11 38 38 12 BI BI 12 38
38 11 DDR0_DQS_N<2> A15 DDR0_NDQS2 DDR1_NDQS2 E1 DDR1_DQS_N<2> 11 38 38 12 DDR2_DQS_N<2> W1 DDR2_NDQS2 DDR3_NDQS2 AN5 DDR3_DQS_N<2> 12 38
BI BI BI BI
38 11 BI DDR0_DQS_P<3> A4 DDR0_PDQS3 DDR1_PDQS3 T1 DDR1_DQS_P<3> BI 11 38 38 12 BI DDR2_DQS_P<3> AK1 DDR2_PDQS3 DDR3_PDQS3 AN16 DDR3_DQS_P<3> BI 12 38
38 11 BI DDR0_DQS_N<3> A5 DDR0_NDQS3 DDR1_NDQS3 R1 DDR1_DQS_N<3> BI 11 38 38 12 BI DDR2_DQS_N<3> AJ1 DDR2_NDQS3 DDR3_NDQS3 AN15 DDR3_DQS_N<3> BI 12 38
DDR0_CK_P P4 F11 DDR1_CK_P DDR2_CK_P AH14 AH4 DDR3_CK_P

B
38 11
38 11
OUT
OUT DDR0_CK_N N4
J1
DDR0_CK
DDR0_CKB
DDR1_CK
DDR1_CKB F12
A10
DDR1_CK_N
OUT
OUT
11 38
11 38
38 12
38 12
OUT
OUT DDR2_CK_N AH13
AN10
DDR2_CK
DDR2_CKB
DDR3_CK
DDR3_CKB AJ4
AD1
DDR3_CK_N
OUT
OUT
12 38
12 38 B
38 11 OUT DDR0_CKE<0> DDR0_CKE0 DDR1_CKE0 DDR1_CKE<0> OUT 11 38 38 12 OUT DDR2_CKE<0> DDR2_CKE0 DDR3_CKE0 DDR3_CKE<0> OUT 12 38
NC_DDR0_CKE<1>NO_TEST=TRUE K1 A9 NO_TEST=TRUE NC_DDR1_CKE<1> NC_DDR2_CKE<1> NO_TEST=TRUEAN9 AE1 NO_TEST=TRUE NC_DDR3_CKE<1>

DDR0_CKE1 DDR1_CKE1 DDR2_CKE1 DDR3_CKE1
H5G_DDR0_ZQ M4 DDR0_RREF DDR1_RREF E11 H5G_DDR1_ZQ H5G_DDR2_ZQ AH9 DDR2_RREF DDR3_RREF AB5 H5G_DDR3_ZQ
38 11 OUT DDR0_CSN<0> K6 DDR0_CSN0 DDR1_CSN0 F10 DDR1_CSN<0> OUT 11 38 38 12 OUT DDR2_CSN<0> AG9 DDR2_CSN0 DDR3_CSN0 AC6 DDR3_CSN<0> OUT 12 38
NC_DDR0_CSN<1>NO_TEST=TRUE J6 E13 NO_TEST=TRUE NC_DDR1_CSN<1> NC_DDR2_CSN<1> NO_TEST=TRUEAG8 AC5 NO_TEST=TRUE NC_DDR3_CSN<1>

DDR0_CSN1 DDR1_CSN1 DDR2_CSN1 DDR3_CSN1
8 PPVREF_DDR0_DQ_H5 D10 DDR0_VREF_DQ DDR1_VREF_DQ L3 PPVREF_DDR1_DQ_H5 8 8 PPVREF_DDR2_DQ_H5 AB4 DDR2_VREF_DQ DDR3_VREF_DQ AJ11 PPVREF_DDR3_DQ_H5 8
34 8 =PP1V2_S2R_H5 H15 DDR0_VDD_CKE DDR1_VDD_CKE H8 =PP1V2_S2R_H5 8 34 34 8 =PP1V2_S2R_H5 Y8 DDR2_VDD_CKE DDR3_VDD_CKE AE8 =PP1V2_S2R_H5 8 34
1
1 1 C1020 1 C1021 1
R1021 1
R1022 1 C1022 1 C1023 R10234
R1020 0.22UF 0.22UF 240 240 0.22UF 0.22UF 240
240 20% 20% 1% 1% 20% 20% 1%
1% 6.3V 6.3V 1/20W 1/20W 6.3V 6.3V 1/20W
1/20W 2 X5R 2 X5R MF MF 2 X5R 2 X5R MF
MF 0201 0201 2 201 2 201 0201 0201 2 201
2 201
=PP1V2_VDDIOD_H5 =PP1V2_VDDIOD_H5
=PP1V2_VDDIOD_H5 34 9 8 34 9 8
34 9 8
=PP1V2_VDDIOD_H5 34 9 8
1 1
1
R1055 R1083 R1095 1
1
R1053 1 C1058 4.7K 1 C1085 4.7K C1095
1 C1057 4.7K 1% 1% 0.01UF
A 4.7K
1%
1/32W 10%
0.01UF
1%
1/32W
MF
0.01UF
10%
2 6.3V
1/32W
MF
2 01005
0.01UF
10%
2 6.3V
1/32W
MF
2 01005
10%
2 6.3V
X5R SYNC_MASTER=N/A SYNC_DATE=N/A A
MF 2 6.3V
X5R 2 01005 X5R
01005
X5R
01005
01005 PAGE TITLE
2 01005 01005
AP: DDR
PPVREF_DDR2_DQ_H5 8 PPVREF_DDR3_DQ_H5 8 DRAWING NUMBER SIZE
PPVREF_DDR1_DQ_H5
PPVREF_DDR0_DQ_H5 8
8
1 VOLTAGE=0.6V 1 VOLTAGE=0.6V
1
R1056
VOLTAGE=0.6V R1084 1 C1084 MIN_NECK_WIDTH=0.2MM R1096 1 C1096 MIN_NECK_WIDTH=0.2MM
1
R1054 1
VOLTAGE=0.6V
1 C1056 MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM 4.7K 0.01UF
NET_SPACING_TYPE=PWR 4.7K 0.01UF
NET_SPACING_TYPE=PWR
REVISION
C1054 MIN_LINE_WIDTH=0.3MM 4.7K 0.01UF NET_SPACING_TYPE=PWR 1% 10% MAX_NECK_LENGTH=3 MM 1% 10% MAX_NECK_LENGTH=3 MM
R
A.0.0
4.7K 0.01UF NET_SPACING_TYPE=PWR 1% 10% MAX_NECK_LENGTH=3 MM 1/32W 2 6.3V 1/32W 2 6.3V
1% 10% MAX_NECK_LENGTH=3 MM 1/32W 6.3V
2 X5R MF X5R MF X5R NOTICE OF PROPRIETARY PROPERTY: BRANCH
1/32W 6.3V
2 X5R MF 2 01005 01005 2 01005 01005
MF 2 01005 01005 THE INFORMATION CONTAINED HEREIN IS THE
2 01005 01005 PROPRIETARY PROPERTY OF APPLE INC.
10 OF 154
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8 7 6 5 4 3 2 1
34 =PPVDD_CPUB_H5
C1147 1 C1148 1 C1149 1 C1150 1 C1151 1 C1152 1 C1153 1 C1154 1 C11B0 1 C11B1 1 U0600
4.3UF 4.3UF 1UF 1UF 0.47UF 0.47UF 0.1UF 0.1UF 8.2PF 8.2PF
20% 20% 20% 20% 20% 20% 20% 20% +/-0.5PF +/-0.5PF BALI-H5G
4V 4V 6.3V 2 6.3V 2 4V 4V 6.3V 6.3V 16V 16V
X5R-CERM 2 X5R-CERM 2 X5R X5R CERM-X5R-1 2 CERM-X5R-1 2 X5R-CERM 2 X5R-CERM 2NP0-C0G-CERM 2NP0-C0G-CERM 2 V20 BGA G7 =PP1V2_VDDIOD_H5
0610 0610 0201 0201 201 201 01005 01005 01005 01005 SYM 9 OF 12
8 34
V22 G8
V24 OMIT_TABLE G9
Y20 VDD_CPUB G10 C1193 1 C1190 1 C1191 1 C1192 1
=PPVDD_CPU0_H5 1.1A@1.1V 1UF 4.3UF 4.3UF 10UF
34 Y22 G11 20% 20% 20% 20%
6.3V 2 4V 4V 6.3V 2
Y24 G12 X5R X5R-CERM 2 X5R-CERM 2 X5R
C1155 1 C1156 1 C1157 1 C1158 1 C1159 1 C1160 1 0201 0610 0610 603
G13
=PPVDD_SOC_H5 4.3UF 4.3UF 1UF 1UF 1UF 1UF
D
34 9 20%
4V
X5R-CERM 2
0610
20%
4V
X5R-CERM 2
0610
20%
6.3V 2
X5R
0201
20%
6.3V 2
X5R
0201
20%
6.3V 2
X5R
0201
20%
6.3V 2
X5R
0201
AA21
AB20
G14
G15 D
AB22 H7
AC19 VDD_CPU0 J7
J8 U10 AC21 2.5A@1.1V K7 C1194 1 C1195 1 C1196 1 C1197 1 C1142 1
J10 U0600 U12 AD20 L7 1UF 0.47UF 0.47UF 0.22UF 0.22UF
C1161 1 C1162 1 C1163 1 C1164 1 C1165 1 C1166 1 C11C0 1 C11C1 1 20% 20% 20% 20% 20%
J12 BALI-H5G U14 6.3V 2 4V 4V 6.3V 2 6.3V 2
1UF 1UF 1UF 1UF 0.1UF 0.1UF 8.2PF 8.2PF AE19 M7 X5R
J14 BGA U16 20% 20% 20% 20% 20% 20% +/-0.5PF +/-0.5PF 0201 CERM-X5R-1 2 CERM-X5R-1 2 X5R X5R
6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V 16V 16V AE21 N7 201 201 0201 0201
J22 SYM 10 OF 12 U22 X5R X5R X5R X5R X5R-CERM 2 X5R-CERM 2NP0-C0G-CERM 2NP0-C0G-CERM 2
0201 0201 0201 0201 01005 01005 01005 01005 P7
K9 OMIT_TABLE U24 AA23 R7
K11 V9 AB24 T7
K13 V11 34 =PPVDD_CPU1_H5 AC23 VDDIOD U7
K15 V13 1000MA@1.2V
C1167 1 C1168 1 C1169 1 C1170 1 C1171 1 C1172 1
AC25 2.5A@1.1V V7 C1143 1 C1144 1
K21 V15 AD22 VDD_CPU1 W7 0.22UF 0.22UF
L8 V17 4.3UF 4.3UF 1UF 1UF 1UF 1UF 20% 20%
20% 20% 20% 20% 20% 20% AD24 Y7 6.3V 2 6.3V 2
4V 4V 6.3V 2 6.3V 2 6.3V 2 6.3V 2 X5R X5R
L10 V25 X5R-CERM 2 X5R-CERM 2 X5R X5R X5R X5R AE23 AA7 0201 0201
L12 W8 0610 0610 0201 0201 0201 0201
AE25 AB7
L14 W10 AC7
L16 W12 AA19 AD7
L18 W14 AA25 AE7
L20 W16 W19 AF7
550MA@1.1V
L22 T19 C1173 1 C1174 1 C1175 1 C1176 1 C1177 1 C1178 1 C11D0 1 C11D1 1 W21 VDD_SRAM AF8
M9 W26 1UF 1UF 1UF 1UF 0.1UF 0.1UF 8.2PF 8.2PF
20% 20% 20% 20% 20% 20% +/-0.5PF +/-0.5PF W23 AF9
6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V 16V 16V
M11 Y9 X5R X5R X5R X5R X5R-CERM 2 X5R-CERM 2NP0-C0G-CERM 2NP0-C0G-CERM 2 W25 AF10
M13 Y11 0201 0201 0201 0201 01005 01005 01005 01005
AF11
M15 Y13 52MA
N28 VDDIO30_GRP1 FAST SCAN CLK AF12
M17 Y15 F18 VDDIO30_GRP2 AF13
=PPVDD_SRAM_H5 GPIO_3V0
C C
34
M19 Y17 K25 VDDIO30_GRP3 AF14
USB11
M21 Y26
C1179 1 C1180 1 C1181 1 C1182 1 C1183 1 C1184 1 C1185 1 C11E0 1 C11E1 1 AF15
M23 AA8 10UF 4.3UF 4.3UF 1UF 1UF 0.47UF 0.47UF 8.2PF 8.2PF J20 VDDIOD0 SPI3
N8 9500MA MAX
AA10 20% 20% 20% 20% 20% 20% 20% +/-0.5PF +/-0.5PF 12MA
6.3V 2 4V 4V 6.3V 2 6.3V 2 4V 4V 16V 16V 2MA VDDIO18_GRP1 H18 =PP1V8_VDDIO18_H5
N10 VDD VDD AA12 X5R X5R-CERM 2 X5R-CERM 2 X5R X5R CERM-X5R-1 2 CERM-X5R-1 2NP0-C0G-CERM 2NP0-C0G-CERM 2 4 6 7 9 34
603 0610 0610 0201 0201 201 201 01005 01005 K20 VDDIOD1 I2C2
N12 AA14 2MA H26 1 C1198 1 C1199 1 C1145
N14 AA16 0.22UF 0.22UF 56PF
AG26 45MA J27 20% 20% 5%
N16 AA18 =PP3V0_VDDIO30_H5 AH26 VDDIO18_GRP2 K27 2 6.3V 2 6.3V
X5R 2 6.3V
34 9
VDDIOD2 FMI0-3 (1.8V) X5R 0201 NP0-C0G
N18 AA26 45MA 0201 01005
AJ26 L27
N20 AB9 CA185 1 CA186 1 CA187 1 CA188 1
N22 AB11 10UF 18MA
20% 0.22UF 0.22UF 0.22UF AC26 VDDIO18_GRP3 N29
P9 AB13 6.3V 2 20% 20% 20%
X5R 6.3V 2 6.3V 2 6.3V 2 AD26
P11 AB15 603 X5R X5R X5R VDDIOD3 FMI1-3 (1.8V)
0201 0201 0201 AE26 45MA U25
P15 AB17 35MA U26
P17 AC8 5MA VDDIO18_GRP4
=PP3V0_VDDIO30_H5 AE20 VDD_ANA0 TEMP SENSOR V26
34 9
P19 AC10 AE24 VDD_ANA1 ANALOG
P21 AC12 10MA
5MA VDDIO18_GRP5 AF25
P23 AC14 1 CA189 1 CA190 1 CA191 1 CA192 W18 VDD_ANA_TMPSADC0
R8 AC16 0.22UF 0.22UF 0.22UF 0.22UF P13 VDD_ANA_TMPSADC1 12MA
20% 20% 20% 20% VDDIO18_GRP6 AH18
R10 AC18 2 6.3V
X5R
6.3V
2 X5R 6.3V
2 X5R 2 6.3V
X5R
R12 AD9 0201 0201 0201 0201
R14 AD11
R16 AD13
R20 AD15 34 6 =PP1V8_NAND_H5
R22 AD17 CRITICAL
T9 AE16 1 CA193 1 CA194 1 CA195 1 CA196 1 CA197 1 CA198 1 CA199 1 C11F0
T11 AE18 10UF 4.3UF 1UF 10UF 10UF 1UF 0.47UF 8.2PF
B T13
T15
AF17
U20
20%
2 6.3V
CERM-X5R
0402-1
20%
2 4V
X5R-CERM
0610
10%
2 6.3V
CERM
402
20%
2 6.3V
CERM-X5R
0402-1
20%
2 6.3V
CERM-X5R
0402-1
10%
2 6.3V
CERM
402
20%
2 4V
X7S
0204
+/-0.5PF
2 16V
NP0-C0G-CERM
01005
B
T17 R18
T21 R24
T23
U8 34 9 7 6 4 =PP1V8_VDDIO18_H5
1 CA150 1 CA151 1 CA152 1 CA153

=PPVDD_SOC_H5 0.22UF 0.22UF 0.22UF 0.22UF
34 9 20% 20% 20% 20%
2 6.3V
X5R
6.3V
2 X5R 6.3V
2 X5R 6.3V
2 X5R
C1100 1 C1101 1 C1102 1 C1103 1 C1104 1 C1105 1 0201 0201 0201 0201
10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20%
6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2
X5R X5R X5R X5R X5R X5R
603 603 603 603 603 603
TABLE_ALT_HEAD

C1106 1 C1107 1 C1108 1 C1109 1
C1110 1 C1111 1 1 C1113 1 C1114
1 C1115 1 C1116 1 C1117 1 C1118
PART NUMBER
4.3UF 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF 1UF 1UF 1UF 1UF 1UF 1UF
TABLE_ALT_ITEM
20% 20% 20% 20% 20% 20% 10% 10% 10% 10% 10% 10% 138S0702 138S0657 QTY 21 RDAR://PROBLEM/8837828
4V 4V 4V 4V 4V 4V 6.3V
X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 2 6.3V
CERM 2 6.3V
CERM
2 CERM 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM C1106,C1107,C1108,C1109,C1110,C1111,C1147,C1148,C1155,C1156,C1167,C1168,C1180,C1181,C1190,C1191,C1315,C1321,C1415,C1421,CA194
0610 0610 0610 0610 0610 0610 402 402 402 402 402 402
C1119 1 C1120 1 C1121 1 C1122 1 C1123 1 C1124 1 C1125 1 C1126 1

A 0.47UF
20%
4V
CERM-X5R-1 2
0.47UF
20%
4V
CERM-X5R-1 2
0.47UF
20%
4V
CERM-X5R-1 2
0.47UF
20%
4V
CERM-X5R-1 2
0.47UF
20%
4V
CERM-X5R-1 2
0.47UF
20%
4V
CERM-X5R-1 2
0.47UF
20%
4V
CERM-X5R-1 2
0.47UF
20%
4V
CERM-X5R-1 2
201 201 201 201 201 201 201 201 PAGE TITLE
AP: POWER
DRAWING NUMBER SIZE

REVISION
C1128 1 C1129 1 C1130 1 C1131 1 C1132 1 C1133 1 C1134 1 C1135 1 C1136 1 C1137 1 C1138 1 C1139 1 C1140 1 C1141 1 C11A0 1 C11A1 1
R
A.0.0
0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 8.2PF 8.2PF NOTICE OF PROPRIETARY PROPERTY: BRANCH
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% +/-0.5PF +/-0.5PF
6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 16V 16V THE INFORMATION CONTAINED HEREIN IS THE
X5R X5R X5R X5R X5R X5R X5R X5R X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 NP0-C0G-CERM 2NP0-C0G-CERM 2 PROPRIETARY PROPERTY OF APPLE INC.
0201 0201 0201 0201 0201 0201 0201 0201 01005 01005 01005 01005 01005 01005 01005 01005 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
11 OF 154
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BOOT CONFIG ID STUFF FOR FORM FACTOR BOARD

=PP1V8_H5
JTAG
34 10 7 5 4
NOSTUFF NOSTUFF
1 1 1 1
R1200 R1201 R1202 R1203
10K 10K 10K 10K
5% 5% 5% 5%
1/32W 1/32W 1/32W 1/32W
MF MF MF MF
2 01005 2 01005 2 01005 2 01005
BOOT_CONFIG[3] 5 OUT GPIO_BOOT_CONFIG_3 R1210
100
1 2 JTAG_AP_SEL OUT 4
BOOT_CONFIG[2] 5 OUT GPIO_BOOT_CONFIG_2
5%
1/32W
D BOOT_CONFIG[1] 5 OUT GPIO_BOOT_CONFIG_1 MF

01005 D
BOOT_CONFIG[0] 5 OUT GPIO_BOOT_CONFIG_0
R1211
100
1 2 JTAG_AP_TRST_L OUT 4 36 39
BOOT_CONFIG[3-0] S/W READ FLOW 5%

1/32W
MF
CURRENT SETTING ---> 1100 FMI0/1 2/2 CS 1. SET GPIO AS INPUT 01005
1101 FMI0/1 4/4 CS 2. DISABLE PU AND ENABLE PD
1110 FMI0/1 4/4 CS WITH TEST 3. READ
FOR REFERENCE
BOOT_CONFIG[3:0]
0000 SPI0
0001 SPI1
0010 SPI0 W/TEST
0011 SPI1 W/TEST
0100 FMI0 2CS
0101 FMI0 4CS
0110 FMI0 4CS W/TEST
0111 RESERVED
1000 FMI1 2 CS
1001 FMI1 4 CS
1010 FMI1 4CS W/TEST
1100 FMI0/1 2/2 CS
1101 FMI0/1 4/4 CS
1110 FMI0/1 4/4 CS W/TEST
1111 RESERVED
C C
R1260
1
100K 2 AP_TESTMODE OUT 4
5%
1/32W
MF
BOARD ID 01005
34 10 7 5 4 =PP1V8_H5
NOSTUFF
MLB_D&MLB_E MLB_C&MLB_E MLB_B&MLB_D DEV
1 1 1 1 XW1200
R1220 R1204 R1205 R1206 SHORT-01005
10K 10K 10K 10K 2 1 AP_TST_STPCLK OUT 4
5% 5% 5% 5%
1/32W 1/32W 1/32W 1/32W
MF MF MF MF NOSTUFF
2 01005 2 01005 2 01005 2 01005
XW1201
SHORT-01005
2 1 AP_FAST_SCAN_CLK OUT 4
NOSTUFF
XW1202
BOARD_ID[3] 5 OUT GPIO_BOARD_ID_3 SHORT-01005
2 1 AP_HOLD_RESET OUT 4
BOARD_ID[2] 5 OUT GPIO_BOARD_ID_2
BOARD_ID[3-0] S/W READ FLOW
1. SET GPIO AS INPUT

B
0000
0001
X140
X140
AP WLAN (MLB A)
DEV WLAN 2.
3.
DISABLE PU AND ENABLE PD
READ
B
0010 X140 AP BB_41 (MLB B)
0011 X140 DEV BB_41
0100 X140 AP BB_42 (MLB C)
0101 X140 DEV BB_42 25 IN USB_BRICKID MAKE_BASE=TRUE PMU_USB_BRICKID OUT 30
1010 X140 AP BB_26A (MLB D)

1011 X140 DEV BB_26A
1110 X140 AP BB_26 (MLB E)
1111 X140 DEV BB_26
BOARD REVISION
5 OUT GPIO_BRD_REV2
5 OUT GPIO_BRD_REV1
5 OUT GPIO_BRD_REV0
NOSTUFF NOSTUFF
1 1 1
R1207 R1208 R1209
10K 10K 10K
5% 5% 5%
1/32W 1/32W 1/32W
MF MF MF
2 01005 2 01005 2 01005
A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
AP: MISC & ALIASES

DRAWING NUMBER SIZE
BRD_REV[2-0] S/W READ FLOW
REVISION
1. SET GPIO AS INPUT
000 PROTO
2. ENABLE PU AND DISABLE PD
R
A.0.0
001 PROTO 2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
010 EVT 3. READ
CURRENT SETTING ---> 011 DVT THE INFORMATION CONTAINED HEREIN IS THE
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38 8 DDR1_CA<0> T15 CA0_1 CA0_2 G16 DDR0_CA<0> 8 38
38 8 DDR1_CA<1> U15 CA1_1 U1300 CA1_2 G17 DDR0_CA<1> 8 38
38 8 DDR1_CA<2> U14 CA2_1 H4G-DRAM CA2_2 H17 DDR0_CA<2> 8 38
38 8 DDR1_CA<3> V14 CA3_1 XXXMB CA3_2 H18 DDR0_CA<3> 8 38

BGA
38 8 DDR1_CA<4> T13 CA4_1 CA4_2 J16 DDR0_CA<4> 8 38
SYM 1 OF 2
D 34 12 11 =PP1V2_S2R_DDR
38 8
38 8
DDR1_CA<5>
DDR1_CA<6>
T9
U9
CA5_1
CA6_1
OMIT_TABLE CA5_2
CA6_2
N16
N17
DDR0_CA<5>
DDR0_CA<6>
8 38
8 38
D
38 8 DDR1_CA<7> U8 CA7_1 CA7_2 P17 DDR0_CA<7> 8 38 34 12
=PP1V8_S2R_DDR
1
R1305 DDR1_CA<8> V8 P18 DDR0_CA<8>
10K
1 C1360 38 8 CA8_1 CA8_2 8 38
1% 0.01UF 38 8 DDR1_CA<9> T7 CA9_1 CA9_2 R16 DDR0_CA<9> 8 38 C1301 1 C1302 1 C1303 1 C1304 1 C1305 1 A2 VDD1_0 VSS0 A16
1/32W
MF
10%
6.3V 10UF 1UF 1UF 0.01UF 0.01UF B1 VDD1_1 U1300 VSS55 A19
2 X5R 20% 10% 10% 10% 10%
2 01005 01005 DDR1_CK_P U12 CK_1 CK_2 K17 DDR0_CK_P 6.3V 6.3V 6.3V 6.3V 6.3V B11 VDD1_2 H4G-DRAM VSS2 A4
38 8 8 38 X5R 2 CERM 2 CERM 2 X5R 2 X5R 2
38 8 DDR1_CK_N U11 CKB_1 CKB_2 L17 DDR0_CK_N 8 38
603 402 402 01005 01005 F17 VDD1_3 XXXMB VSS3 A6
V13 CKE_1 BGA
38 8 DDR1_CKE<0> CKE_2 J18 DDR0_CKE<0> 8 38 L2 VDD1_4 VSS4 B15
PPVREF_DDR0_CA
VDD1
11 38 39
M16 VDD1_5 SYM 2 OF 2 VSS49 C1
1 VOLTAGE=0.6V T10 OMIT_TABLE B9
R1306 1 C1350 MIN_NECK_WIDTH=0.2MM
VDD1_6 VSS6
10K 0.01UF NET_SPACING_TYPE=PWR C1306 C1308 1 C1309 1 U18 VDD1_7 VSS7 C11
1% 10%
6.3V
MAX_NECK_LENGTH=3 MM
DDR1_CSN<0> U13 CSB_1 CSB_2 J17 DDR0_CSN<0> 0.22UF
1 C1307 1 0.22UF 56PF V17 VDD1_8
1/32W
MF 2 X5R 38 8 8 38
20% 0.22UF 20% 5%
01005 6.3V 20% 6.3V 6.3V V6 VDD1_9 VSS9 D1
2 01005 X5R 2 6.3V X5R 2 NP0-C0G 2
0201 X5R 2 0201 01005 W17 VDD1_10 VSS10 D19
0201
38 8 DDR1_DM<1> C12 DM0_1 DM0_2 K3 DDR0_DM<1> 8 38
U19 VDD1_11 VSS1 A1
38 8 DDR1_DM<0> B10 DM1_1 DM1_2 M2 DDR0_DM<0> 8 38 VSS12 E12
38 8 DDR1_DM<3> B16 DM2_1 DM2_2 G4 DDR0_DM<3> 8 38 34 12 11 =PP1V2_S2R_DDR E11 VDD2_1 VSS13 E13
38 8 DDR1_DM<2> D7 DM3_1 DM3_2 T2 DDR0_DM<2> 8 38 E19 VDD2_2 VSS51 G5
34 12 11 =PP1V2_S2R_DDR L5
C1310 1 C1311 1 C1312 1 C1313 1 VDD2_3
DDR1_DQ<8> C15 DQ0_1 DQ0_2 G3 DDR0_DQ<8> 0.22UF M18 VDD2_4 VSS52 T16
1 38 8 8 38
0.22UF 0.22UF 0.22UF
R1351 DDR1_DQ<9> D15 DQ1_1 DQ1_2 G2 DDR0_DQ<9> 20% 20% 20% 20%
6.3V U17 VDD2_5 VSS50 E7
10K C1361
38 8 8 38 6.3V 6.3V 6.3V X5R 2
DDR_1
DDR_2
1 B14 H5 X5R 2 X5R 2 X5R 2 T18 F16
1% 38 8 DDR1_DQ<10> DQ2_1 DQ2_2 DDR0_DQ<10> 8 38 0201 0201 0201 0201 VDD2_6 VSS18
1/32W 0.01UF DDR1_DQ<11> C14 H4 DDR0_DQ<11> V10 B19
MF 10% 38 8 DQ3_1 DQ3_2 8 38 VDD2_7 VSS48
2 01005 2 6.3V
X5R 38 8 DDR1_DQ<12> D14 DQ4_1 DQ4_2 H3 DDR0_DQ<12> 8 38 V16 VDD2_8 VSS20 G18
VDD2
01005
38 8 DDR1_DQ<13> E14 DQ5_1 DQ5_2 H2 DDR0_DQ<13> 8 38
V18 VDD2_9 VSS53 V1
VSS
38 8 DDR1_DQ<14> B13 DQ6_1 DQ6_2 J3 DDR0_DQ<14> 8 38
W5 VDD2_10 VSS22 J1
PPVREF_DDR1_CA
C 1
R1352 1 C1352
11 38 39
VOLTAGE=0.6V
38 8
38 8
DDR1_DQ<15>
DDR1_DQ<0>
C13
C9
DQ7_1
DQ8_1
DQ7_2
DQ8_2
J2
N4
DDR0_DQ<15>
DDR0_DQ<0>
8 38
8 38
C1314
10UF
1 C1315
4.3UF
1
C1316
1UF
1 C1317 1
1UF
C1318
0.01UF
1 C1319
56PF
1 W16
W19
VDD2_11
VDD2_12
VSS23
VSS24
K18
K5
C
MIN_LINE_WIDTH=0.3MM 20% 10% 5%
10K 0.01UF NET_SPACING_TYPE=PWR 38 8 DDR1_DQ<1> D9 DQ9_1 DQ9_2 N3 DDR0_DQ<1> 8 38
20%
6.3V 4V 10%
6.3V
10%
6.3V 10V 6.3V W18 VDD2_13 VSS25 L18
1% 10% MAX_NECK_LENGTH=3 MM X5R 2 X5R-CERM 2 CERM 2 CERM 2 X5R-CERM 2 NP0-C0G 2
DDR1_DQ<2> B8 DQ10_1 DQ10_2 P5 DDR0_DQ<2> V19 VDD2_14 VSS26 L3
1/32W
MF 2 6.3V
X5R
38 8 8 38 603 0610 402 402 0201 01005
01005 DDR1_DQ<3> C8 DQ11_1 DQ11_2 P4 DDR0_DQ<3> A3 VDD2_15 VSS27 M5
2 01005 38 8 8 38
38 8 DDR1_DQ<4> D8 DQ12_1 DQ12_2 P3 DDR0_DQ<4> 8 38 T19 VDD2_16 VSS28 N18

38 8 DDR1_DQ<5> E8 DQ13_1 DQ13_2 P2 DDR0_DQ<5> 8 38 VSS29 N5
38 8 DDR1_DQ<6> B7 DQ14_1 DQ14_2 R4 DDR0_DQ<6> 8 38 34 12 11
=PP1V2_VDDQ_DDR H1 VDDQ27
38 8 DDR1_DQ<7> C7 DQ15_1 DQ15_2 R3 DDR0_DQ<7> 8 38 M1 VDDQ32 VSS47 A18
38 8 DDR1_DQ<24> B18 DQ16_1 DQ16_2 B2 DDR0_DQ<24> 8 38 C1323 1 C1320 1 C1321 1 C1324 1 C1325 1 C1326 1 C1322 1 W3 VDDQ31 VSS32 R18
=PP1V2_VDDQ_DDR 38 8 DDR1_DQ<25> C18 DQ17_1 DQ17_2 C2 DDR0_DQ<25> 8 38
56PF 10UF 4.3UF 0.22UF 0.22UF 0.22UF 0.01UF E1 VDDQ VSS33 R2
34 12 11 5% 20% 20% 20% 20% 20% 10%
DDR1_DQ<26> D18 DQ18_1 DQ18_2 D3 DDR0_DQ<26> 6.3V 6.3V 2 4V 6.3V 2 6.3V 2 6.3V 2 6.3V 2 U1 VDDQ1 VSS34 T1
38 8 8 38 NP0-C0G 2 X5R X5R-CERM 2 X5R X5R X5R X5R
1 DDR1_DQ<27> E18 D2 DDR0_DQ<27> 01005 603 0610 0201 0201 0201 01005 B12 T17
R1353 38 8 DQ19_1 DQ19_2 8 38 VDDQ3 VSS35
4.7K
1 C1362 38 8 DDR1_DQ<28> B17 DQ20_1 DQ20_2 E4 DDR0_DQ<28> 8 38 D4 VDDQ6 VSS36 U16
1% 0.01UF DDR1_DQ<29> D17 E3 DDR0_DQ<29> U3
1/32W 10% 38 8 DQ21_1 DQ21_2 8 38 VDDQ30
MF 6.3V
2 X5R DDR1_DQ<30> E17 DQ22_1 DQ22_2 E2 DDR0_DQ<30> A14 VDDQ23 VSS54 W2
2 01005 01005
38 8 8 38
DDR1_DQ<31> E16 F2 DDR0_DQ<31> C17 U6

38 8 DQ23_1 DQ23_2 8 38 VDDQ25 VSS39
VDDQ
38 8 DDR1_DQ<16> B6 DQ24_1 DQ24_2 T5 DDR0_DQ<16> 8 38
C19 VDDQ26 VSS40 V11
PPVREF_DDR0_DQ 11 38 39 38 8 DDR1_DQ<17> B5 DQ25_1 DQ25_2 U5 DDR0_DQ<17> 8 38
A10 VDDQ22 VSS41 V12
VOLTAGE=0.6V 38 8 DDR1_DQ<18> C5 DQ26_1 DQ26_2 U4 DDR0_DQ<18> 8 38 A17 VDDQ34 VSS42 V15
1
MIN_LINE_WIDTH=0.3MM 38 8 DDR1_DQ<19> D5 DQ27_1 DQ27_2 U2 DDR0_DQ<19> 8 38 J5 VDDQ16 VSS43 T6
4.7K 0.01UF NET_SPACING_TYPE=PWR B4 V5 K2 V9
1% 10% MAX_NECK_LENGTH=3 MM 38 8 DDR1_DQ<20> DQ28_1 DQ28_2 DDR0_DQ<20> 8 38 VDDQ17 VSS44
1/32W 6.3V
MF 2 X5R 38 8 DDR1_DQ<21> C4 DQ29_1 DQ29_2 V4 DDR0_DQ<21> 8 38 A8 VDDQ21 VSS45 W1
01005
2 01005 38 8 DDR1_DQ<22> B3 DQ30_1 DQ30_2 V3 DDR0_DQ<22> 8 38 N2 VDDQ19 VSS46 W4
38 8 DDR1_DQ<23> C3 DQ31_1 DQ31_2 V2 DDR0_DQ<23> 8 38 R5 VDDQ20
A13 VDDQ24
B 38 8
38 8
DDR1_DQS_P<1>
DDR1_DQS_N<1>
D13 DQS0_1
D12 DQSB0_1
DQS0_2 J4
DQSB0_2 K4
DDR0_DQS_P<1>
DDR0_DQS_N<1>
8 38
8 38
E10
E15
VDDQ28
VDDQ29 B
P1 VDDQ33
=PP1V2_VDDQ_DDR 38 8 DDR1_DQS_P<0> D10 DQS1_1 DQS1_2 M4 DDR0_DQS_P<0> 8 38
34 12 11
38 8 DDR1_DQS_N<0> C10 DQSB1_1 DQSB1_2 M3 DDR0_DQS_N<0> 8 38 34 12 11 =PP1V2_S2R_DDR F18 VDDCA1
1 H16
R1355 VDDCA2
4.7K
1 C1363 38 8 DDR1_DQS_P<3> C16 DQS2_1 DQS2_2 F4 DDR0_DQS_P<3> 8 38 C1327 1 C1328 1 C1329 1 C1330 1 C1331 1 K16 VDDCA3
1% 0.01UF D16 DQSB2_1 10UF 1UF 1UF 0.01UF 0.01UF
1/32W 10% DDR1_DQS_N<3> DQSB2_2 F3 DDR0_DQS_N<3> L16 VDDCA4
VDDCA
38 8 8 38
MF 6.3V 20% 10% 10% 10% 10%
2 X5R 6.3V 6.3V 6.3V 6.3V 6.3V P16
2 01005 X5R 2 CERM 2 CERM 2 X5R 2 X5R 2 VDDCA5
01005 603 402 402 01005 01005
38 8 DDR1_DQS_P<2> D6 DQS3_1 DQS3_2 T3 DDR0_DQS_P<2> 8 38
T11 VDDCA6
38 8 DDR1_DQS_N<2> C6 DQSB3_1 DQSB3_2 T4 DDR0_DQS_N<2> 8 38 T12 VDDCA7
PPVREF_DDR1_DQ 11 38 39
T14 VDDCA8
1 VOLTAGE=0.6V 39 38 11 PPVREF_DDR1_CA U10 VREFCA_1 VREFCA_2 M17 PPVREF_DDR0_CA 11 38 39 V7 VDDCA9
PPVREF_DDR1_DQ D11 VREFDQ_1 VREFDQ_2 L4 PPVREF_DDR0_DQ T8
4.7K 0.01UF
39 38 11 11 38 39
C1332 1 C1333 1 C1334 1 C1335 1 VDDCA10
1% 10%
6.3V
MAX_NECK_LENGTH=3 MM 0.22UF 0.22UF 0.22UF 56PF
1/32W 20% 20% 5%
MF 2 X5R 38 DDR1_ZQ U7 ZQ_1 ZQ_2 R17 38 DDR0_ZQ 6.3V 20% 6.3V 6.3V
01005 X5R 2 6.3V X5R 2 NP0-C0G 2
2 01005 0201 X5R 2 0201 01005
0201
1 1
R1320 R1321
240 240
1% 1%
1/20W 1/20W
MF MF
2 201 2 201
PAGE TITLE
DDR 0 AND 1
DRAWING NUMBER SIZE

REVISION
R
A.0.0
13 OF 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
38 8 DDR3_CA<0> T15 CA0_1 CA0_2 G16 DDR2_CA<0> 8 38

34 11 =PP1V8_S2R_DDR A2 VDD1_0 VSS0 A16
38 8 DDR3_CA<1> U15 CA1_1 U1400 CA1_2 G17 DDR2_CA<1> 8 38
B1 VDD1_1 U1400 VSS55 A19
38 8 DDR3_CA<2> U14 CA2_1 H4G-DRAM CA2_2 H17 DDR2_CA<2> 8 38
C1401 1 C1402 1 C1403 1 C1404 1 C1405 1 B11 VDD1_2 H4G-DRAM VSS2 A4
=PP1V2_S2R_DDR DDR3_CA<3> V14 CA3_1 XXXMB CA3_2 H18 DDR2_CA<3>
34 12 11 38 8
BGA
8 38
10UF 1UF 1UF 0.01UF 0.01UF F17 VDD1_3 XXXMB VSS3 A6
38 8 DDR3_CA<4> T13 CA4_1 CA4_2 J16 DDR2_CA<4> 8 38
20% 10% 10% 10% 10%
BGA
1 6.3V 6.3V 6.3V 6.3V 6.3V L2 B15
R1405 DDR3_CA<5> T9
SYM 1 OF 2
N16 DDR2_CA<5> X5R 2 CERM 2 CERM 2 X5R 2 X5R 2 VDD1_4 VSS4
C1460 CA5_1 CA5_2
VDD1
1 38 8
OMIT_TABLE 8 38
SYM 2 OF 2
10K U9 N17
603 402 402 01005 01005 M16 VDD1_5 VSS49 C1
1% 0.01UF 38 8 DDR3_CA<6> CA6_1 CA6_2 DDR2_CA<6> 8 38
T10 OMIT_TABLE B9
D
1/32W
MF
2 01005
10%
6.3V
2 X5R
01005
38 8
38 8
DDR3_CA<7>
DDR3_CA<8>
U8
V8
CA7_1
CA8_1
CA7_2
CA8_2
P17
P18
DDR2_CA<7>
DDR2_CA<8>
8 38
8 38
U18
V17
VDD1_6
VDD1_7
VSS6
VSS7 C11 D
T7 R16 VDD1_8
38 8 DDR3_CA<9> CA9_1 CA9_2 DDR2_CA<9> 8 38
V6 D1
C1406 1 C1407 1 C1408 1 C1409 1 VDD1_9 VSS9
PPVREF_DDR2_CA 12 38 39
U12 CK_1 0.22UF 0.22UF 0.22UF 56PF W17 VDD1_10 VSS10 D19
38 8 DDR3_CK_P CK_2 K17 DDR2_CK_P 8 38 20% 20% 20% 5% U19 A1
VOLTAGE=0.6V U11 CKB_1 6.3V 2 6.3V 6.3V 2 6.3V VDD1_11 VSS1
1
R1406 1 C1450 MIN_NECK_WIDTH=0.2MM 38 8 DDR3_CK_N CKB_2 L17 DDR2_CK_N 8 38 X5R X5R 2 X5R NP0-C0G 2
E12
MIN_LINE_WIDTH=0.3MM 0201 0201 01005 VSS12
10K 0.01UF NET_SPACING_TYPE=PWR 38 8 DDR3_CKE<0> V13 CKE_1 CKE_2 J18 DDR2_CKE<0> 8 38
0201
E11 E13
1% 10% MAX_NECK_LENGTH=3 MM VDD2_1 VSS13
1/32W 6.3V
MF 2 X5R E19 VDD2_2 VSS51 G5
01005
2 01005 L5 VDD2_3
34 12 11 =PP1V2_S2R_DDR
M18 VDD2_4 VSS52 T16
38 8 DDR3_CSN<0> U13 CSB_1 CSB_2 J17 DDR2_CSN<0> 8 38
U17 E7
C1410 1 C1411 1 C1412 1 C1413 1 VDD2_5 VSS50
0.22UF T18 VDD2_6 VSS18 F16
0.22UF 0.22UF 0.22UF 20%
20% 20% 20% 6.3V 2 V10 VDD2_7 VSS48 B19
DDR3_DM<1> C12 K3 DDR2_DM<1> 6.3V 6.3V 6.3V
38 8 DM0_1 DM0_2 8 38 X5R 2 X5R 2 X5R 2 X5R
V16 G18
0201 VDD2_8 VSS20
VDD2
34 12 11 =PP1V2_S2R_DDR 38 8 DDR3_DM<0> B10 DM1_1 DM1_2 M2 DDR2_DM<0> 8 38
0201 0201 0201
V18 V1
B16 G4 VDD2_9 VSS53
DDR3_DM<3> DM2_1 DM2_2 DDR2_DM<3>
VSS
38 8 8 38
1 W5 J1
R1451 DDR3_DM<2> D7 T2 DDR2_DM<2>
VDD2_10 VSS22
10K 1 C1461 38 8 DM3_1 DM3_2 8 38
W16 VDD2_11 VSS23 K18
1% 0.01UF C1415 1 C1418 1 C1419 1
1/32W 10%
C15 G3 C1414 1 C1416 1 C1417 1 W19 VDD2_12 VSS24 K5
MF 6.3V
2 X5R 38 8 DDR3_DQ<8> DQ0_1 DQ0_2 DDR2_DQ<8> 8 38
10UF 4.3UF 1UF 1UF 0.01UF 56PF W18 L18
2 01005 D15 G2 20% 20% 10% 10% 10% 5% VDD2_13 VSS25
01005 38 8 DDR3_DQ<9> DQ1_1 DQ1_2 DDR2_DQ<9> 8 38
6.3V 4V 6.3V 6.3V 10V 6.3V
V19 L3
X5R-CERM 2 X5R-CERM 2 NP0-C0G 2 VDD2_14 VSS26
DDR_1
DDR_2
DDR3_DQ<10> B14 H5 DDR2_DQ<10> X5R 2 CERM 2 CERM 2
38 8 DQ2_1 DQ2_2 8 38 603 0610 402 402 0201 01005
A3 M5
C14 H4 VDD2_15 VSS27
38 8 DDR3_DQ<11> DQ3_1 DQ3_2 DDR2_DQ<11> 8 38
PPVREF_DDR3_CA 12 38 39
D14 H3
T19 VDD2_16 VSS28 N18
38 8 DDR3_DQ<12> DQ4_1 DQ4_2 DDR2_DQ<12> 8 38
VOLTAGE=0.6V VSS29 N5
1 DDR3_DQ<13> E14 H2 DDR2_DQ<13>
38 8 DQ5_1 DQ5_2 8 38
H1 VDDQ27
10K 0.01UF NET_SPACING_TYPE=PWR 38 8 DDR3_DQ<14> B13 DQ6_1 DQ6_2 J3 DDR2_DQ<14> 8 38
M1 A18
1% 10% MAX_NECK_LENGTH=3 MM VDDQ32 VSS47
1/32W 6.3V
2 X5R 38 8 DDR3_DQ<15> C13 DQ7_1 DQ7_2 J2 DDR2_DQ<15> 8 38 34 12 11 =PP1V2_VDDQ_DDR W3 R18
MF C9 N4 VDDQ31 VSS32
2 01005
01005 DDR3_DQ<0> DQ8_1 DQ8_2 DDR2_DQ<0>
C C
38 8 8 38
E1 VDDQ VSS33 R2
38 8 DDR3_DQ<1> D9 DQ9_1 DQ9_2 N3 DDR2_DQ<1> 8 38 C1423 1 C1420 1 C1421 1 C1424 1 C1425 1 C1426 1 C1422 1
U1 VDDQ1 VSS34 T1
38 8 DDR3_DQ<2> B8 DQ10_1 DQ10_2 P5 DDR2_DQ<2> 8 38
56PF 10UF 4.3UF 0.22UF 0.22UF 0.22UF 0.01UF
5% 20% 20% 20% 20% 20% 10% B12 VDDQ3 VSS35 T17
DDR3_DQ<3> C8 P4 DDR2_DQ<3> 6.3V 6.3V 4V 6.3V 6.3V 6.3V 6.3V
38 8 DQ11_1 DQ11_2 8 38 NP0-C0G 2 X5R 2 X5R-CERM 2 X5R 2 X5R 2 X5R 2 X5R 2 D4 U16
D8 P3 01005 603 0610 0201 0201 0201 01005 VDDQ6 VSS36
38 8 DDR3_DQ<4> DQ12_1 DQ12_2 DDR2_DQ<4> 8 38
U3 VDDQ30
38 8 DDR3_DQ<5> E8 DQ13_1 DQ13_2 P2 DDR2_DQ<5> 8 38
A14 VDDQ23 VSS54 W2
38 8 DDR3_DQ<6> B7 DQ14_1 DQ14_2 R4 DDR2_DQ<6> 8 38 C17
34 12 11 =PP1V2_VDDQ_DDR VDDQ25 VSS39 U6
VDDQ
38 8 DDR3_DQ<7> C7 DQ15_1 DQ15_2 R3 DDR2_DQ<7> 8 38
C19 VDDQ26 VSS40 V11
1 DDR3_DQ<24> B18 B2 DDR2_DQ<24>
R1453 38 8 DQ16_1 DQ16_2 8 38
A10 V12
4.7K 1 C1462 38 8 DDR3_DQ<25> C18 DQ17_1 DQ17_2 C2 DDR2_DQ<25> 8 38
VDDQ22 VSS41
1% 0.01UF A17 VDDQ34 VSS42 V15
1/32W 10% 38 8 DDR3_DQ<26> D18 DQ18_1 DQ18_2 D3 DDR2_DQ<26> 8 38
MF 6.3V J5 VDDQ16 VSS43 T6
2 X5R DDR3_DQ<27> E18 DQ19_1 DQ19_2 D2 DDR2_DQ<27>
2 01005 01005
38 8 8 38
K2 VDDQ17 VSS44 V9
38 8 DDR3_DQ<28> B17 DQ20_1 DQ20_2 E4 DDR2_DQ<28> 8 38
A8 VDDQ21 VSS45 W1
38 8 DDR3_DQ<29> D17 DQ21_1 DQ21_2 E3 DDR2_DQ<29> 8 38
N2 VDDQ19 VSS46 W4
PPVREF_DDR2_DQ 12 38 39 38 8 DDR3_DQ<30> E17 DQ22_1 DQ22_2 E2 DDR2_DQ<30> 8 38
R5
E16 F2 VDDQ20
VOLTAGE=0.6V 38 8 DDR3_DQ<31> DQ23_1 DQ23_2 DDR2_DQ<31> 8 38
1 A13
MIN_LINE_WIDTH=0.3MM 38 8 DDR3_DQ<16> B6 DQ24_1 DQ24_2 T5 DDR2_DQ<16> 8 38
VDDQ24
4.7K 0.01UF NET_SPACING_TYPE=PWR
DDR3_DQ<17> B5 U5 DDR2_DQ<17>
E10 VDDQ28
1% 10% MAX_NECK_LENGTH=3 MM 38 8 DQ25_1 DQ25_2 8 38
E15
1/32W 6.3V
C5 U4 VDDQ29
MF 2 X5R 38 8 DDR3_DQ<18> DQ26_1 DQ26_2 DDR2_DQ<18> 8 38
01005 P1 VDDQ33
2 01005 38 8 DDR3_DQ<19> D5 DQ27_1 DQ27_2 U2 DDR2_DQ<19> 8 38
38 8 DDR3_DQ<20> B4 DQ28_1 DQ28_2 V5 DDR2_DQ<20> 8 38

34 12 11 =PP1V2_S2R_DDR F18 VDDCA1
38 8 DDR3_DQ<21> C4 DQ29_1 DQ29_2 V4 DDR2_DQ<21> 8 38
H16 VDDCA2
DDR3_DQ<22> B3 DQ30_1 DQ30_2 V3 DDR2_DQ<22>
38 8
DDR3_DQ<23> C3 V2 DDR2_DQ<23>
8 38
C1427 1 C1428 1 C1429 1 C1430 1 C1431 1 K16 VDDCA3
38 8 DQ31_1 DQ31_2 8 38
10UF 1UF 1UF 0.01UF 0.01UF L16 VDDCA4
VDDCA
20% 10% 10% 10% 10%
6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 P16 VDDCA5
D13 DQS0_1 X5R CERM CERM X5R X5R
38 8 DDR3_DQS_P<1> DQS0_2 J4 DDR2_DQS_P<1> 8 38
11 =PP1V2_VDDQ_DDR
34 12
603 402 402 01005 01005 T11 VDDCA6
38 8 DDR3_DQS_N<1> D12 DQSB0_1 DQSB0_2 K4 DDR2_DQS_N<1> 8 38
T12
B 1
R1455
4.7K
1 C1463 38 8 DDR3_DQS_P<0> D10 DQS1_1 DQS1_2 M4 DDR2_DQS_P<0> 8 38
T14
V7
VDDCA7
VDDCA8 B
1% 0.01UF C10 DQSB1_1 VDDCA9
1/32W 10% 38 8 DDR3_DQS_N<0> DQSB1_2 M3 DDR2_DQS_N<0> 8 38
T8
MF
2 01005
6.3V
2 X5R C1432 1 C1433 1 C1434 1 C1435 1 VDDCA10
01005
C16 DQS2_1 0.22UF 0.22UF 0.22UF 56PF
38 8 DDR3_DQS_P<3> DQS2_2 F4 DDR2_DQS_P<3> 8 38 20% 20% 20% 5%
6.3V 2 6.3V 2 6.3V 2 6.3V
38 8 DDR3_DQS_N<3> D16 DQSB2_1 DQSB2_2 F3 DDR2_DQS_N<3> 8 38 X5R X5R NP0-C0G 2
0201 X5R 0201 01005
PPVREF_DDR3_DQ 12 38 39
0201
VOLTAGE=0.6V 38 8 DDR3_DQS_P<2> D6 DQS3_1 DQS3_2 T3 DDR2_DQS_P<2> 8 38

1
MIN_LINE_WIDTH=0.3MM 38 8 DDR3_DQS_N<2> C6 DQSB3_1 DQSB3_2 T4 DDR2_DQS_N<2> 8 38
4.7K 0.01UF NET_SPACING_TYPE=PWR
1% 10% MAX_NECK_LENGTH=3 MM
1/32W 6.3V
MF 2 X5R 39 38 12 PPVREF_DDR3_CA U10 VREFCA_1 VREFCA_2 M17 PPVREF_DDR2_CA 12 38 39
01005
2 01005 39 38 12 PPVREF_DDR3_DQ D11 VREFDQ_1 VREFDQ_2 L4 PPVREF_DDR2_DQ 12 38 39
38 DDR3_ZQ U7 ZQ_1 ZQ_2 R17 38 DDR2_ZQ
1
1
R1420 R1421
240 240
1% 1%
1/20W 1/20W
MF MF
2 201 2 201
PAGE TITLE
DDR 2 AND 3
DRAWING NUMBER SIZE

REVISION
R
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8 7 6 5 4 3 2 1
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=PP1V8_NAND
34 =PP3V3_NAND 13 34
1 C1600 1 C1601 1 C1602 1 C1610 1 C1611 1 C1612 1 C1613 1 C1614 1 C1615

10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
6.3V
2 CERM-X5R 6.3V
2 CERM-X5R 6.3V
2 CERM-X5R
D
0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1 0402-1
1 C1604 1 C1605 1 C1606 1 C1620 1 C1621 1 C1622 1 C1623 1 C1624 1 C1625

0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF
20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V
2 X5R 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V
2 X5R 2 6.3V 2 6.3V 6.3V
2 X5R
X5R X5R X5R X5R X5R X5R
0201 0201 0201 0201 0201 0201 0201 0201 0201
1 C1607 1 C1608 1 C1609 1 C1630 1 C1631 1 C1632 1 C1633 1 C1634 1 C1635

27PF 27PF 27PF 27PF 27PF 27PF 27PF 27PF 27PF
5% 5% 5% 5% 5% 5% 5% 5% 5%
2 25V
NP0-C0G
25V
2 NP0-C0G 2 25V
NP0-C0G
25V
2 NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G
25V
2 NP0-C0G 2 25V
NP0-C0G 2 25V
NP0-C0G
0201 0201 0201 0201 0201 0201 0201 0201 0201
PPVDDI_NAND_U1600
VOLTAGE=1.2V
C
1
5%
C1652
27PF
1 C1651
1UF
20%
1 C1650
1UF
20%
MAX_NECK_LENGTH=3MM C
25V
2 NP0-C0G 2 6.3V 6.3V
2 X5R
X5R
0201 0201 0201
OB8
OC8
OD8
OE0
OF8
OA8
B6
F2
M6
N1
N7
G0
VDDI
VCC VCCQ
=PP1V8_NAND 13 34
FMI0_AD<0> G3 IO0-0 OMIT_TABLE
38 13 6 BI A5 FMI0_CE0_L
CE0* 6 38
38 6 BI FMI0_AD<1> H2 IO1-0 U1600 CLE0 A3 FMI0_CLE
IN
FMI0_AD<2> J3 LGA-12X17 IN 6 13 38
38 6 BI IO2-0 C1
K2 ALE0 FMI0_ALE IN 6 13 38 R1655
FMI0_AD<3> IO3-0
XXNM-XGBX8-MLC-PPN1.5-ODP
38 6 BI E3 FMI0_WE_L
L5 WE0* IN 6 13 38 1
38 6 BI FMI0_AD<4> IO4-0
38 6 FMI0_AD<5> K6 IO5-0 100K
BI
RE0 B4 5%
38 6 BI FMI0_AD<6> J5 IO6-0 NC 1/32W
RE0* C7 FMI0_RE_L 6 13 38
MF
2 01005
FMI0_AD<7> H6 IN
38 6 BI IO7-0
G1 DQS0 H4 FMI0_DQS IN 6 13 38
38 13 6 BI FMI1_AD<0> IO0-1
J1 DQS0* F4 NC
38 6 BI FMI1_AD<1> IO1-1
38 6 BI FMI1_AD<2> L1 IO2-1
N3 R/B0* E5 NAND_SLOT0_RDYBSY_L
38 6 BI FMI1_AD<3> IO3-1
38 6 FMI1_AD<4> N5 IO4-1
BI C5 FMI1_CE0_L
L7 CE1* IN 6 38
38 6 BI FMI1_AD<5> IO5-1
CLE1 C3 FMI1_CLE IN 6 13 38
FMI1_AD<6> J7 IO6-1
38 6 BI D2 FMI1_ALE
G7 ALE1 IN 6 13 38
38 6 BI FMI1_AD<7> IO7-1
WE1* E1 FMI1_WE_L IN 6 13 38 =PP1V8_NAND 13 34
RE1 D4 NC
B RE1* D6 FMI1_RE_L IN 6 13 38
TEST POINTS B
DQS1 M4 FMI1_DQS 1
IN 6 13 38 R1690 1 C1690 DO NOT PLACE IN NAND SINGLE PCS SHIELD CAN AREA
DQS1* K4 NC 51.1K 0.1UF
1% 20%
R/B1* E7
1/32W
MF 2 4V
X5R
2 01005 01005
38 13 6 FMI0_AD<0> 1 TPTP1600
VREF G5 FMI_DQVREF_NAND 38 13 6 FMI0_ALE 1 TPTP1601
TPTP1602
TP_FMI_TCKC_U1600 38 13 6 FMI0_CLE 1
OA0 TCKC ZQ A1 FMI_ZQ_U1600
TP_FMI_TMSC_U1600 OB0 TMSC 38 13 6 FMI0_RE_L 1 TPTP1603
VSS VSSQ
1
R1654 38 13 6 FMI0_WE_L 1 TPTP1605
243
B2
F6
L3
A7
M2
OC0
OD0
OE8
OF0
G8
1%
1
R1691 1 C1691
1/20W 51.1K 0.1UF
MF 1% 20% 38 13 6 FMI0_DQS 1 TPTP1613
2 201 1/32W 2 4V
X5R
MF 01005
2 01005
38 13 6 FMI1_AD<0> 1 TPTP1606
38 13 6 FMI1_ALE 1 TPTP1607
38 13 6 FMI1_CLE 1 TPTP1608
TPTP1609
38 13 6 FMI1_RE_L 1
38 13 6 FMI1_WE_L 1 TPTP1611
38 13 6 FMI1_DQS 1 TPTP1615
PAGE TITLE
NAND
DRAWING NUMBER SIZE

REVISION
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D D
WIFI ALIASES
36 4 HSIC1_WLAN_DATA MAKE_BASE=TRUE 50_HSIC_WLAN_DATA 27
36 4 HSIC1_WLAN_STB MAKE_BASE=TRUE 50_HSIC_WLAN_STROBE 27
36 5 GPIO_WLAN_HSIC_HOST_RDY MAKE_BASE=TRUE AP_HSIC3_RDY 27
36 5 GPIO_WLAN_HSIC_DEV_RDY MAKE_BASE=TRUE DEV_HSIC3_RDY 27
30 PMU_GPIO_WLAN_REG_ON MAKE_BASE=TRUE WLAN_REG_ON 27
30 PMU_GPIO_WLAN_HOST_WAKE MAKE_BASE=TRUE HOST_WAKE_WLAN 27
30 PMU_GPIO_BT_REG_ON MAKE_BASE=TRUE BT_REG_ON 27
30 PMU_GPIO_BT_HOST_WAKE MAKE_BASE=TRUE HOST_WAKE_BT 27
5 GPIO_BT_WAKE MAKE_BASE=TRUE BT_WAKE 27
36 5 UART3_BT_RXD MAKE_BASE=TRUE BT_UART_TXD 27
36 5 UART3_BT_TXD MAKE_BASE=TRUE BT_UART_RXD 27
36 5 UART3_BT_CTS_L MAKE_BASE=TRUE BT_UART_RTS_L 27
36 5 UART3_BT_RTS_L MAKE_BASE=TRUE BT_UART_CTS_L 27
36 30 PMU_GPIO_CLK_32K_WLAN MAKE_BASE=TRUE CLK32K_AP 27
36 5 I2S2_BT_BCLK MAKE_BASE=TRUE BT_PCM_CLK 27
I2S2_BT_DOUT BT_PCM_IN
C
36 5
36 5 I2S2_BT_DIN
MAKE_BASE=TRUE
MAKE_BASE=TRUE BT_PCM_OUT
27
27 C
36 5 I2S2_BT_LRCK MAKE_BASE=TRUE BT_PCM_SYNC 27
36 5 UART4_WLAN_RXD MAKE_BASE=TRUE WLAN_UART_TXD 27
36 5 UART4_WLAN_TXD MAKE_BASE=TRUE WLAN_UART_RXD 27
5 GPIO_WL_HSIC_RESUME MAKE_BASE=TRUE WLAN_HSIC3_RESUME 27
34 VDDIO_WLAN_BT_1V8 MAKE_BASE=TRUE PP_WL_BT_VDDIO_AP 27
B B
PAGE TITLE
ALIASES
DRAWING NUMBER SIZE

REVISION
R
A.0.0
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EDP CONNECTOR
34 =PP3V3_LCD
39 34 30 29 25 PPVCC_MAIN TABLE_ALT_HEAD

1 C2240 PART NUMBER
0.1UF L2242,L5500,L5510,L5520,L5530,L5540,L5930,L5931
TABLE_ALT_ITEM
10% 155S0667 155S0583 RDAR://PROBLEM/8616060, RADAR://PROBLEM/9015335

2 6.3V
X5R 1
1 C2239
0.1UF
TABLE_ALT_ITEM
201 155S0625 155S0559 L2202,L2212,L2222,L2232

RDAR://PROBLEM/9017591
10%
VDD 6.3V
2 X5R
U2200 201
D LCD_RAMP 7 CAP
SLG5AP302
TDFN
3 VOLTAGE=3.3V
CRITICAL
L2201 D
D MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM FERR-120-OHM-1.5A
CRITICAL
5 IN PM_LCDVDD_PWREN 2 ON S 5 39 15 PP3V3_S0_LCD_FERR 1 2
1 0402A
R2205 GND NOSTUFF
100K 8 1 1 C2232 1 C2206
5% 1 C2241 1 C2203 1 C2202 R2290 1 C2230
1/20W 0.1UF 1UF 47K 8.2PF 1000PF
MF 3900PF 10% 10% 5% 82PF +/-0.1PF% 10%
2 201
10%
50V
LAYOUT NOTE:
2 6.3V 2 6.3V 1/20W 5% 2 25V 2 16V
2 X7R PUT THERMAL VIAS AROUND U2200 IN CASE OF SHORTED CONDITION X5R CERM MF 2 25V
NP0-C0G-CERM
CER
0201
X7R-CERM
0201
0402 201 402 2 201 0201
R2280 VOLTAGE=3.3V
1.00M MIN_LINE_WIDTH=0.30 MM
1 2 CONN_EDP_DATA_EMI_N<0> 15 37
39 15 PP3V3_S0_LCD_FERR MIN_NECK_WIDTH=0.20 MM 39 PP3V3_LCDVDD_SW_F
01005
C2280 1
1.2PF R2240
1 2 100K
1% CRITICAL
NOSTUFF
+/-0.1PF 1/32W
MF L2242
16V 01005
NP0-C0G 2 90-OHM-50MA
01005
EDP_AUX_N C22501 20.1UF
37 EDP_AUX_EMI_N 2 TCM0605-1 3 CONN_EDP_AUX_EMI_N 518S0827
37 7 IN 15 37
CRITICAL
R2281 201 6.3V 10% X5R EDP_HPD
1.00M 0.1UF
J2200 OUT 7 37
1 2 CONN_EDP_DATA_EMI_P<0> 15 37 37 7 IN EDP_AUX_P C22511 2 37 EDP_AUX_EMI_P 1 4 CONN_EDP_AUX_EMI_P 15 37 502250-8051-B 1

01005 201 6.3V 10% X5R SYM_VER-2
F-RT-SM R2242
1 54 100K
R2241
C C2281
1.2PF
1 2
100K
1%
1/32W
52
1%
1/32W
MF
2 01005
C
MF 1
NOSTUFF 2 01005 2
+/-0.1PF 3
16V NC 4
NP0-C0G 5
01005 6
7
8
R2282 CONN_EDP_AUX_EMI_P 9 NC
20.1UF 2 CRITICAL 3
37 15
1.00M 37 7 IN EDP_DATA_N<0> C22421 37 EDP_DATA_EMI_N<0> CONN_EDP_DATA_EMI_N<0> 15 37 11
10 CONN_EDP_AUX_EMI_N 15 37
1 2 CONN_EDP_DATA_EMI_N<1> 15 37
201 6.3V 10% X5R 12 CONN_EDP_DATA_EMI_N<0> 15 37
13
01005 NC 14 CONN_EDP_DATA_EMI_P<0>
EDP_DATA_P<0> C22431 0.1UF
2 EDP_DATA_EMI_P<0> 1 4 CONN_EDP_DATA_EMI_P<0> 15
15 37
C2282 37 7 IN 37
TCM0806-4SM
15 37
17
16 CONN_EDP_DATA_EMI_N<1> 15 37
1.2PF 201 6.3V 10% X5R SYM_VER-2
NC
12-OHM-100MA-8.5GHZ 18 CONN_EDP_DATA_EMI_P<1> 15 37
1 2 19
L2212 20 CONN_EDP_DATA_EMI_N<2> 15 37
NOSTUFF 21
+/-0.1PF NC 22 CONN_EDP_DATA_EMI_P<2> 15 37
16V 23
NP0-C0G 24 CONN_EDP_DATA_EMI_N<3>
C22441 20.1UF 2 CRITICAL 3
15 37
01005 EDP_DATA_N<1> EDP_DATA_EMI_N<1> CONN_EDP_DATA_EMI_N<1> 25
37 7 IN 37 15 37 NC 26 CONN_EDP_DATA_EMI_P<3> 15 37
201 6.3V 10% X5R 27
28
R2283 J2200_29_GND 29
1.00M2 EDP_DATA_P<1> C22451 0.1UF
2 EDP_DATA_EMI_P<1> 1 4 CONN_EDP_DATA_EMI_P<1>
39 15
30 LED_IO_6_B IN 30 37
1 CONN_EDP_DATA_EMI_P<1> 15 37
37 7 IN 37 15 37
37 30 IN LED_IO_5_B 31
201 6.3V 10% X5R TCM0806-4SM
SYM_VER-2 32 LED_IO_4_B IN 30 37
01005 12-OHM-100MA-8.5GHZ 37 30 IN LED_IO_3_B 33
34 LED_IO_2_B IN 30 37
L2222 LED_IO_1_B 35
C2283 37 30 IN 36 J2200_36_GND 15 39
1.2PF 37 30 IN LED_IO_6_A 37
38 LED_IO_5_A IN 30 37
1 2 LED_IO_4_A 39
C22461 20.1UF 2 CRITICAL 3
37 30 IN 40 LED_IO_3_A
NOSTUFF 37 7 IN EDP_DATA_N<2> 37 EDP_DATA_EMI_N<2> CONN_EDP_DATA_EMI_N<2> 15 37
37 30 LED_IO_2_A 41 IN 30 37
+/-0.1PF IN 42 LED_IO_1_A
16V 201 6.3V 10% X5R IN 30 37
NP0-C0G 39 15 J2200_43_GND 43
44
01005
EDP_DATA_P<2> C22471 0.1UF
2 EDP_DATA_EMI_P<2> 1 4 45 NC
37 7 IN 37 CONN_EDP_DATA_EMI_P<2> 15 37 46
201 6.3V 10% X5R TCM0806-4SM
SYM_VER-2 47
R2284 12-OHM-100MA-8.5GHZ NC 48
B 1
1.00M2
CONN_EDP_DATA_EMI_N<2> 15 37 L2232
49
51
50
NC B
01005
C2284 EDP_DATA_N<3> C22481 20.1UF 37 EDP_DATA_EMI_N<3> 2 CRITICAL 3 CONN_EDP_DATA_EMI_N<3> 53
37 7 IN 15 37
1.2PF 201 6.3V 10% X5R 55
1 2
NOSTUFF EDP_DATA_P<3> C22491 0.1UF
2 37 EDP_DATA_EMI_P<3> 1 4 CONN_EDP_DATA_EMI_P<3>
+/-0.1PF 37 7 IN 15 37
16V 201 6.3V 10% X5R TCM0806-4SM
SYM_VER-2
NP0-C0G 12-OHM-100MA-8.5GHZ
01005
L2202
R2285
1
1.00M2
CONN_EDP_DATA_EMI_P<2> 15 37
01005
C2285
1.2PF
1 2 CRITICAL
NOSTUFF L2210
+/-0.1PF
16V R2295 FERR-240-OHM-25%-300MA
NP0-C0G 0 1 2
01005 1 2 J2200_29_GND 15 39 34 =PPLED_REG_B 39 PPLED_BACK_REG_B
VOLTAGE=20.4V 0402
5% MIN_LINE_WIDTH=0.6 MM
R2286 1/20W
MF
MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR 1 C2253 1 C2270 1 C2271
1
1.00M2 201 MAX_NECK_LENGTH=3 MM 100PF 820PF 8.2PF
CONN_EDP_DATA_EMI_N<3> 15 37
5% 10% +/-0.25PF
01005 2 50V 50V
2 CERM 2 50V
R2296 CERM
0402 0402
CERM
402-1
C2286 1
0 2 J2200_36_GND
1.2PF 15 39
1 2 5%
1/20W
NOSTUFF MF
201
+/-0.1PF
A 16V
NP0-C0G
01005
CRITICAL
L2200 SYNC_MASTER=N/A SYNC_DATE=N/A A
R2297 FERR-240-OHM-25%-300MA PAGE TITLE
R2287
1.00M2
1
0 2 J2200_43_GND 15 39
34 =PPLED_REG_A
VOLTAGE=20.4V
1 2 39 PPLED_BACK_REG_A VIDEO: EDP CONNECTOR
1 CONN_EDP_DATA_EMI_P<3> 15 37 5% 0402 DRAWING NUMBER SIZE
1/20W MIN_LINE_WIDTH=0.6 MM
01005 MF
201
NET_SPACING_TYPE=PWR 1 C2233 1 C2220 1 C2221 Apple Inc. 051-9385 D
C2287 MAX_NECK_LENGTH=3 MM 100PF 820PF 8.2PF REVISION
5% 10% +/-0.25PF
1.2PF 2 50V
CERM
50V
2 CERM 2 50V
CERM
R
A.0.0
1 2 0402 0402 402-1 NOTICE OF PROPRIETARY PROPERTY: BRANCH
NOSTUFF THE INFORMATION CONTAINED HEREIN IS THE
+/-0.1PF PROPRIETARY PROPERTY OF APPLE INC.
16V THE POSESSOR AGREES TO THE FOLLOWING: PAGE
NP0-C0G
01005 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
22 OF 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
16 PP18V_GRAPE =PP3V0_GRAPE_MARIO1 34
=PP3V0_GRAPE
C3005 1 C3007 1 C3053 1
1 C3006
16 17 34
0.1UF 0.1UF 0.1UF

10% 10% 10% 0.1UF 1
R3025
25V 25V 25V 10%
TABLE_5_HEAD
X5R 2 X5R 2 X5R 2 6.3V
2 X5R
10K
402 402 402 5%
F3
E9
B6
A6
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 201 1/20W
TABLE_5_ITEM MF
343S0525 1 IC,ASIC,GROUNDHOG B0,120B BGA U3003 CRITICAL VCC_DIG 2 201
VDDH
CONNECTORS TO GRAPE FLEX B1

U3003
GROUNDHOG A1 MT_PANEL_OUT<0> 36 16 5 SPI3_GRAPE_SCLK MAKE_BASE=TRUE GRAPE_SCLK 17
MUX_IN<0> BGA
D
17 MUX0 VSTM0 16
D SPI3_GRAPE_CS_L GRAPE_CS_L
MAKE_BASE=TRUE
R3070 C1 B2 MT_PANEL_OUT<1> 36 16 5 17 TO Z2
17 MUX_IN<1> MUX1 VSTM1 16
AG_SHLD_TST_FLEX 1
0 2 AG_SHLD_TST MUX_IN<2> E1 CRITICAL C2 MT_PANEL_OUT<2>
16 17 17 MUX2 VSTM2 16
MUX_IN<3> F2 OMIT D1 MT_PANEL_OUT<3>

5% 17 MUX3 VSTM3 16
1/20W
MF 17 MUX_IN<4> H1 MUX4 VSTM4 D2 MT_PANEL_OUT<4> 16
201
J1 E2 36 16 5 SPI3_GRAPE_MOSI MAKE_BASE=TRUE GRAPE_MOSI 17
MUX_IN<5> MUX5 VSTM5 MT_PANEL_OUT<5>
17 16
GPIO_GRAPE_RST_L MAKE_BASE=TRUE RST_GRAPE_Z1_L
NOSTUFF 17 MUX_IN<6> J2 MUX6 VSTM6 F1 MT_PANEL_OUT<6> 16
5 17
1
R3071 RST_GRAPE_Z2_L
0
1 C3070 17 MUX_IN<7> J3 MUX7 VSTM7 G1 MT_PANEL_OUT<7> 16
17
5% 0.1UF 17 MUX_IN<8> K4 MUX8 VSTM8 G2 MT_PANEL_OUT<8> 16

1/20W 10%
MF
25V
2 X5R 17 MUX_IN<9> H5 MUX9 VSTM9 I1 MT_PANEL_OUT<9> 16
2 201 402 17 MUX_IN<10> I5 MUX10 VSTM10 H2 MT_PANEL_OUT<10> 16
17 MUX_IN<11> J8 MUX11 VSTM11 I2 MT_PANEL_OUT<11> 16

J9 SPI3_GRAPE_MISO MAKE_BASE=TRUE GRAPE_MISO
17 MUX_IN<12> MUX12 VSTM12 K1 MT_PANEL_OUT<12> 16
36 16 5 17
17 MUX_IN<13> K8 MUX13 VSTM13 K2 MT_PANEL_OUT<13> 16
17 MUX_IN<14> J10 MUX14 VSTM14 I3 MT_PANEL_OUT<14> 16
MUX_IN<15> I10 MUX15 VSTM15 K3 MT_PANEL_OUT<15> =PP3V0_GRAPE

P/N 518S0828 =PP3V0_GRAPE
17 16
34 17 16 16 17 34
17 MUX_IN<16> H10 MUX16 VSTM16 J4 MT_PANEL_OUT<16> 16
MATES WITH LEFTMOST GRAPE FLEX TAIL 17 MUX_IN<17> F11 MUX17 VSTM17 I4 MT_PANEL_OUT<17> 16
1
R3030 1
R3031 1 C3030 1 C3031 1R3032 1R3033
17 MUX_IN<18> C11 MUX18 VSTM18 K6 MT_PANEL_OUT<18> 16 10K 10K 0.1UF 0.1UF 3.3K 10K
5% 5% 10% 10% 5% 5%
MUX_IN<19> E10 MUX19 VSTM19 H6 MT_PANEL_OUT<19> 1/20W 1/20W 6.3V
2 X5R 2 6.3V 1/20W 1/20W
CRITICAL 17 16
MF MF X5R MF MF
2
A11 VSTM20 K5 MT_PANEL_OUT<20> 201 201
J3010 NC
B4
MUX20 16
2 201 2 201
VCCA VCCB 2 201 2 201
MUX21 VSTM21 J5 MT_PANEL_OUT<21>
502250-8037-B NC 16
A5 MUX22 VSTM22 I7 MT_PANEL_OUT<22> U3007
F-RT-SM NC 16
PQFP1
41 A2 MUX23 VSTM23 K9 MT_PANEL_OUT<23>
NC 16 SPI3_GRAPE_SCLK 6 1A1 CRITICAL 1B1 15 Z1_SCLK
39 I8 MT_PANEL_OUT<24> 36 16 5 IN OUT 17
C7 VSTM24 16
SPI3_GRAPE_CS_L 8 2A1
17 Z1_BON_L<0> BON_L0 K10 MT_PANEL_OUT<25> 36 16 5 IN 2B1 13 Z2_H_CS_L OUT 16 17
SN74AVCH4T245RSV
A7 VSTM25 16
17 Z1_BON_L<1> BON_L1 TO Z1/Z2
16 MT_PANEL_OUT<36> 37 VSTM26 I6 MT_PANEL_OUT<26> 16
4 1DIR
36 MT_PANEL_OUT<37> Z1_BON_L<2> B7 BON_L2
C C
16 17
16 MT_PANEL_OUT<38> 35 VSTM27 J7 MT_PANEL_OUT<27> 16
1 1OE*
34 MT_PANEL_OUT<39> 16 17 Z1_BON_L<3> B8 BON_L3
33 VSTM28 K11 MT_PANEL_OUT<28> 16
SPI3_GRAPE_MOSI
32 Z1_BON_L<4> A8 BON_L4 7 1A2 1B2 14 Z1_MISO
MT_PANEL_IN<29> 31
17
I9 MT_PANEL_OUT<29> 36 16 5 IN OUT 17
17 VSTM29 16
30 MT_PANEL_IN<28> 17 17 Z1_BON_L<5> C8 BON_L5 9 2A2 2B2 12 Z1_CS_OE OUT 16 17
17 MT_PANEL_IN<27> 29 VSTM30 J11 MT_PANEL_OUT<30> 16
28 MT_PANEL_IN<26> 17
MT_PANEL_IN<25> 27 C6 VSTM31 I11 MT_PANEL_OUT<31> DIR_U3007 5 2DIR
17
NC 16
MT_PANEL_IN<23> 25 D3 VSTM32 H11 MT_PANEL_OUT<32> GPIO_GRAPE_FW_DNLD_EN_L 16 2OE* APN:311S0485

17
NC 16 5 IN
MT_PANEL_IN<21> 23 D4 VSTM33 G11 MT_PANEL_OUT<33>
17
NC 16
(A -> B)
MT_PANEL_IN<19> 21 D5 VSTM34 G10 MT_PANEL_OUT<34>
17
NC 16
MT_PANEL_IN<17> 19 D6 VSTM35 F10 MT_PANEL_OUT<35> GND

17
NC 16
MT_PANEL_IN<15> D8 MT_PANEL_OUT<36>
10
11
17 VSTM36 C10
17
NC 16
MT_PANEL_IN<13> 15 D9 VSTM37 D10 MT_PANEL_OUT<37>

17
NC 16
MT_PANEL_IN<11> 13 E4 VSTM38 E11 MT_PANEL_OUT<38>

17
NC 16
MT_PANEL_IN<9> 11 E8 VSTM39 D11 MT_PANEL_OUT<39>

17
NC 16
MT_PANEL_IN<7> 9 F4 VSTM40 B11

17
8 MT_PANEL_IN<6> 17
NC NC
MT_PANEL_IN<5> 7 F5 VSTM41 B10
17
6 MT_PANEL_IN<4> NC NC
MT_PANEL_IN<3> 5
17
F8 NC VSTM42 C4
17
4 MT_PANEL_IN<2> NC NC
17 MT_PANEL_IN<1> 3
17
NC
F9 VSTM43 A4
NC 34 =PP1V8_MISC =PP3V0_GRAPE 16 17 34
2 MT_PANEL_IN<0> 17
AG_SHLD_TST_FLEX 1 G3 VSTM44 B5
16
NC NC
NC
G4 VSTM46 A3
NC
1 C3060
G9 C5 0.1UF
38 NC VSTM45 NC 10%
6.3V
40 H3 VSTM47 B3 2 X5R A1 A2
NC NC 201
H4 VCCA VCCB
NC A_AD_R0 A10 Z1_B_ADR<0> 17
NC
H7
A_AD_R1 B9 Z1_B_ADR<1> 17
U3060
H8 SN74LVC1T45YZPR
NC A_AD_R2 A9 Z1_B_ADR<2> 17 BGA
H9 GPIO_GRAPE_IRQ_L A B GPIO_GRAPE_IRQ_3V0_L
NC 5 OUT C1 C2
IN 17
J6
NC B2
K7 DIR
B NC
GND
GND
B
G8
G7
G6
G5
F7
F6
E7
E6
E5
E3
D7
C9
MATES WITH RIGHTMOST GRAPE FLEX TAIL B1
CRITICAL
J3011
NOSTUFF
502250-8037-B R3060
F-RT-SM 0
41 1 2
39 BOOST CONVERTOR MIN_NECK_MIDTH SHOULD BE 0.4MM 5%
1/20W
CRITICAL MF
CRITICAL LOAD CURRENT ~ 153UA 201
37 L3000 VOLTAGE=18V
MT_PANEL_OUT<1> 35
36 MT_PANEL_OUT<0> 16 4.7UH-700MA-280MOHM MIN_LINE_WIDTH=0.2MM
D3000 MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM R3066
16 SOD-323 =PP3V0_GRAPE
MT_PANEL_OUT<3>
34 MT_PANEL_OUT<2> 16
VR_BOOST_L 1 2 VR_BOOST_SW
0.1 PP18V_GRAPE =PP3V0_GRAPE 16 17 34
16 33 A K PP18V_R_GRAPE 1 2 16 16 17 34
32 MT_PANEL_OUT<4> 16 VOLTAGE=18V
MT_PANEL_OUT<6>
MIN_LINE_WIDTH=0.2MM VLF 1% MIN_LINE_WIDTH=0.6MM
1 C3050
1 C3041
MT_PANEL_OUT<7> 29
30 16
C3009 B0520WSXG 1/20W
MF
CRITICAL 0.1UF
6
16
0.1UF 10%
16
34 17 16
=PP3V0_GRAPE 1 2
VCC 10% CRITICAL 6.3V
2 X5R
C3008 1 R30091 1 C3000 U3010
2 6.3V
X5R
U3009
201
24 MT_PANEL_OUT<12> 16 0.1UF 33PF 1M SN74LVC1G126DRYR-M
201
22 MT_PANEL_OUT<14> 10% 5% 1% 1UF SN74LVC1G125DRYR-M 6
MT_PANEL_OUT<15> 16 25V 25V 10% LLP LLP Z1_MOSI
16 21 X5R NPO-C0G 2 1/16W
2 25V Z1_CS_OE SPI3_GRAPE_MISO 2 IN 17
20 MT_PANEL_OUT<16> 2 0201 MF-LF X5R 1 OE 4
MT_PANEL_OUT<17> 19
16
402 402 2 603-1
17 16 IN 36 16 5 OUT
16
18 MT_PANEL_OUT<18> NC 5
MT_PANEL_OUT<19> 17
16
VIN OE* NC
16
16 MT_PANEL_OUT<20> 16 CRITICAL 17 16
Z2_H_CS_L 2 A Y 4 Z1_CS_L 17
3
MT_PANEL_OUT<21> 15 IN OUT
16
MT_PANEL_OUT<23> 13
14 MT_PANEL_OUT<22> 16 1 L U3000 FB 4 VR_BOOST_FBK 1
16
TPS61045 GND NC
16 MT_PANEL_OUT<25> 11 QFN-1 1 Z1_CS_OE
10 MT_PANEL_OUT<26> 3 5 PM_BOOST_EN R3012
5
16
NC DO CTRL 17 17 16 IN
MT_PANEL_OUT<27> 9
16
8 MT_PANEL_OUT<28> 1 C3002 71.5K
A
16
MT_PANEL_OUT<29> NC
A
7 1%
16
MT_PANEL_OUT<31>
1 C3001 SW 8 470PF 1/20W
5 2.2UF 10% MF SYNC_MASTER=N/A SYNC_DATE=N/A
PGND
16
4 MT_PANEL_OUT<32> THRML 16V
2 201
GND
16 2 X5R-X7R-CERM
MT_PANEL_OUT<33> 3 10% PAGE TITLE
2 6.3V
GRAPE: GROUNDHOG,CONN,BOOST
16
2 MT_PANEL_OUT<34> PAD 0201
MT_PANEL_OUT<35> 1
16 X5R
16 603
9 7 6
DRAWING NUMBER SIZE
AGND_U3000
TABLE_ALT_HEAD

051-9385 D
39
38
40 2
PART NUMBER
TABLE_ALT_ITEM
Apple Inc. REVISION
XW3000
311S0523 311S0485 U3007
TABLE_ALT_ITEM
R
A.0.0
SM 311S0524 311S0533 U3009 NOTICE OF PROPRIETARY PROPERTY: BRANCH
1 TABLE_ALT_ITEM

311S0525 311S0532 U3010 PROPRIETARY PROPERTY OF APPLE INC.
30 OF 154
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
ZEPHYR 1+ ASIC
34 =PP3V0_GRAPE_Z1 ARM9 MCU (Z2 BASED)
1 C3102 Z1_1V8_OUT =PP3V0_GRAPE_Z2
0.1UF 17
Z2_VDDCORE 34
10%
6.3V VOLTAGE=1.8V
VOLTAGE=3.0V
2 X5R
201 1 C3101
1 C3111 1 C3109 MIN_LINE_WIDTH=0.5MM
1 C3105 1 C3107
R3101 MIN_NECK_WIDTH=0.2MM
2.2UF 10UF 0.1UF NET_SPACING_TYPE=PWR 0.1UF 4.7UF
20% 10% 10% 20%
4.7 NET_SPACING_TYPE=PWR
20% 2 6.3V 6.3V
2 X5R 6.3V
2 X5R 6.3V
1 2 MT_3V3_INT 2 4V CERM-X5R 2 X5R-CERM1
D
X5R VDDANA AND VDDCORE 0402-1 201 201 402
D
5% 402
1/20W
MF
1 C3104 1 C3103 ARE EACH GENERATED WITHIN
Z2 AND BYPASSED OUTSIDE
201 4.7UF 0.1UF =PP3V0_GRAPE 16 17 34 VOLTAGE=1.8V
20% 10%
6.3V
2 X5R-CERM1
6.3V
2 X5R Z2_VDDANA MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM R3190
402 201 VOLTAGE=1.8V
Z2_3V3_1V8_IN 1
1.00 2 Z1_1V8_OUT
1
R3155 MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.1MM VOLTAGE=1.8V
17
5%
100K 1 C3112 1 C3110
NET_SPACING_TYPE=PWR 1%
1/20W
2.2UF 0.1UF 1 C3108 1 C3191 1 C3192 MF
1/20W
MF 20% 1 C3106 201
4V 10% 0.1UF 0.1UF 10UF 10UF MIN_NECK_MIDTH SHOULD BE 0.4MM
K10
C10
2 201 2 X5R 6.3V
G6
G7
G8
K4
C5
C9
B6
2 X5R 10% 10% 20% 20%
402 6.3V
201 2 X5R 6.3V
2 X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
MT_PANEL_IN<0> H2 IN0 VDDDIG V18 SCLK A11 Z1_SCLK 201 201 0402-1 0402-1
16 VDDANA VDDIO IN 16 17
16 MT_PANEL_IN<1> G2 IN1 CRITICAL CS* B10 Z1_CS_L IN 16
16 MT_PANEL_IN<2> D7 IN2 U3100 MISO B9 Z1_MISO IN 16 17
D2
E1
G8
H2
J5
E2
E3
16 MT_PANEL_IN<3> C1 IN3 BCM5973 MOSI B8 Z1_MOSI OUT 16 17
16 MT_PANEL_IN<4> F1 IN4 BGA

J1 VDDANA VDDCORE VDDIO VDDLDO
16 MT_PANEL_IN<5> IN5 GO A8 Z1_GO 17
MT_PANEL_IN<6> D2 DONE B7 Z1_DONE A9 F9

16 IN6 17
NC IN0_0 B_ADR0 R3120
16 MT_PANEL_IN<7> D1 IN7 NC
B9 IN0_1 B_ADR1 F8 Z1_PCLK 17 0 Z2 - PRODUCT STRAP OPTIONS
CFG1 CFG0 MODE 5%
16 MT_PANEL_IN<8> K7 IN8 PCLK A12 Z1_PCLK 17 B_ADR2 G9 1/20W
A7 IN1_0 MF BON_L5 BON_L4 BON_L3 MODE
16 MT_PANEL_IN<9> H1 IN9 0 0 DEPENDENT 1 NC CRITICAL 201
A8 J8 Z1_CS_OE_R 1 2 Z1_CS_OE
16 MT_PANEL_IN<10> E1 IN10 STMOUT A10 Z1_STMIN NC IN1_1 U3101 BON_L0 IN 16
LOW X X K48
H9 NC_BON_L1 NO_TEST=TRUE
16 MT_PANEL_IN<11> E2 IN11 STMIN A13
0 1 DEPENDENT 2
NC
B8 IN2_0 BCM5974CKFBGH BON_L1
J9
FBGA BON_L2 AG_SHLD_TST 16 FLOAT FLOAT FLOAT K94
MT_PANEL_IN<12> J2 IN12 1 0 AUTONOMOUS C8 IN2_1
16
NC BON_L3 H7 NC_BON_L3 NO_TEST=TRUE
16 MT_PANEL_IN<13> G1 IN13 B_ADR0 A5 Z1_B_ADR<0> 16 FLOAT LOW FLOAT J2
1 1 SLAVE B7 IN3_0 BON_L4 J7
16 MT_PANEL_IN<14> F2 IN14 B_ADR1 B5 Z1_B_ADR<1> 16
NC
C7 IN3_1 BON_L5 H5 NC_BON_L5 NO_TEST=TRUE
ALL OTHER STRAPS CRITICAL ERROR
16 MT_PANEL_IN<15> J7 IN15 B_ADR2 A6 Z1_B_ADR<2> 16
NC
16 MT_PANEL_IN<16> K2 IN16 K48 USES DEPENDENT 2 MODE NC
A6
IN4_0 GPIO0 J2 GPIO_GRAPE_IRQ_3V0_L OUT 16 DEFAULT J2
MT_PANEL_IN<17> N4 IN17 BON_L0 A2 Z1_BON_L<0> B6 IN4_1 GPIO1 J3 PM_BOOST_EN
C
NC
C
16 16 OUT 16
16 MT_PANEL_IN<18> M5 IN18 BON_L1 A1 Z1_BON_L<1> 16 GPIO2 H4 Z1_GO 17

C6 IN5_0
MT_PANEL_IN<19> N5 A3 Z1_BON_L<2> NC J6 Z1_DONE 1
16 IN19 BON_L2 16
C5 IN5_1 GPIO3 17 R3160
16 MT_PANEL_IN<20> M6 IN20 BON_L3 A4 Z1_BON_L<3> 16
NC GPIO4 G3 GRAPE_CS_L IN 16 100K
B5 IN6_0 F3 5%
MT_PANEL_IN<21> N3 IN21 BON_L4 B4 Z1_BON_L<4> GPIO5 GRAPE_MOSI 1/20W
16 16
NC IN 16
MF
MT_PANEL_IN<22> M3 IN22 BON_L5 B3 Z1_BON_L<5> A5 IN6_1 GPIO6 F4 GRAPE_MISO
16 16
NC OUT 16 2 201
MT_PANEL_IN<23> L1 IN23 GPIO7 H6 GRAPE_SCLK
16
A4 IN 16
K1 NC IN7_0
16 MT_PANEL_IN<24> IN24 TM A9 U3100_TM
B4 IN7_1 G6 TP_U3101_TCK
L2 NC JTAG_TCK
16 MT_PANEL_IN<25> IN25 E8
A3 JTAG_TDI TP_U3101_TDI
MT_PANEL_IN<26> N6 RESET* A7 RST_GRAPE_Z1_L 1
16 IN26 16 R3181 NC IN8_0
JTAG_TDO E9 TP_U3101_TDO
MT_PANEL_IN<27> M2 IN27 100 B3 IN8_1
16
5% =PP3V0_GRAPE NC JTAG_TMS F7 TP_U3101_TMS
16 MT_PANEL_IN<28> M4 IN28 1/32W
34 17 16
C2 IN9_0
=PP3V0_GRAPE 16 17 34
MF NC H1
MT_PANEL_IN<29> M1 IN29 H_CS* Z2_H_CS_L
16
2 01005 A2 IN9_1 IN 16 1
16 MUX_IN<0> N2 IN30 NC H_SCLK J1 Z1_SCLK IN 16 17
R3107
N1 B2 H3
100K
MUX_IN<1> IN31 1
R3173 IN10_0 H_SDI Z1_MISO 5%
16
NC IN 16 17
1/20W
MUX_IN<2> N13 IN32 0 C1 IN10_1 H_SDO J4 Z1_MOSI MF
16
NC OUT 16 17
16 MUX_IN<3> N12 IN33

5%
1/20W 2 201
MF B1
IN11_0 A_CS* F1 Z2_A_CS_L
MUX_IN<4> M10 IN34 NC
16
2 201 A1 IN11_1 A_SCLK G1 TP_Z2_A_SCLK
16 MUX_IN<5> M13 IN35 NC
A_SDI F2 TP_Z2_A_SDI
MUX_IN<6> N8 IN36 E6 ARMTAPMD*
16
NC A_SDO G4 TP_Z2_A_SDO
16 MUX_IN<7> M12 IN37
BOOT_CFG0_R F6 BOOT_CFG0
16 MUX_IN<8> K13 IN38 TM0 E7 TP_U3101_TM0
BOOT_CFG1_R D3 BOOT_CFG1
16 MUX_IN<9> L13 IN39 TM1 D4 U3101_TM1
MUX_IN<10> L12 IN40 G5 FLOO
16
NC CLKIN E5 HOST_REFCLK PMU_GPIO_CLK_32K_GRAPE IN 30 36
MUX_IN<11> M11 F5 1
16 IN41 1
R3171 NC LFOO
CLKOUT E4 MAKE_BASE=TRUE R3180
MUX_IN<12> N11 IN42 NC 100
16
0 G7 EXTFLLIN 5%
16 MUX_IN<13> M8 IN43 5% NC INTERNAL PU RESET* D5 RST_GRAPE_Z2_L IN 16 1/32W
1/20W
B 16
16
MUX_IN<14>
MUX_IN<15>
N9
M9
IN44
IN45
MF
2 201 GND
MF
2 01005 B
MUX_IN<16> N10 IN46
C3
C4
D6
D7
D8
C9
D9
G2
D1
H8
16
16 MUX_IN<17> K12 IN47

16 MUX_IN<18> J13 IN48
16 MUX_IN<19> F12 IN49
G13 IN50
NC
J12 IN51
NC
E12 IN52
NC
E13 IN53
NC
H13 IN54
NC
N7 IN55
NC
D13 IN56
NC
D12 IN57
NC
H12 IN58
NC
F13 IN59
NC
C13 IN60
NC
E7 IN61
NC
M7 IN62
NC
G12 IN63
NC
GNDANA PAGE TITLE
GNDDIG GNDIO
GRAPE: Z1, Z2
B1
B2
B12
B13
C2
C3
C6
C7
C8
C11
C12
D3
D11
F7
H7
L3
L4
L5
L6
L7
L8
L9
L10
L11
C4
B11
DRAWING NUMBER SIZE

REVISION
R
A.0.0
31 OF 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
34 19 =PPVCC_MAIN_AUDIO
34 18 =PP1V8_AUDIO CRITICAL MIKEY BUS FILTER

C3604 1 1 C3609
1 C3602 1 C3615 0.1UF 4.7UF
10% 20%
0.1UF 0.1UF 16V
X5R-CERM 2 2 10V
X5R-CERM
20% 20%
4V
2 X5R 2 4V 0201 0402 SIGNAL_MODEL=EMPTY
X5R
01005 01005 1 C3630
100PF
5%
PLACE R3630 & R3631 CLOSE TO U3600 2 25V
34 19 =PP1V7_VA_VCP R3698 R3630
NP0-CERM
0201
1.00 1
D 1 C3603 1
CRITICAL
C3699
R3699
1
1.00 2
VOLTAGE=1.7V
MIN_LINE_WIDTH=0.6 MM
PP1V7_VA_VCP_R 1 C3614
2
1%
1/20W
1
12
5%
2
NOSTUFF
D
1.0UF 4.7UF 0.1UF MF
L81_MBUS_P 1/20W 1 C3631 MIKEY_TS_P
20% 20% 1% CRITICAL 10% 201 37 18 MF BI 25 37
2 6.3V 6.3V 1/20W 201 100PF
X5R 2 X5R-CERM1 MF 1 C3698 1 C3601 2 16V
X5R-CERM 37 18 L81_MBUS_N 5% MIKEY_TS_N BI 25 37
0201-MUR 402 201
1.0UF 4.7UF 0201 R3631 2 25V
20% 20%
1
R3697 12
NP0-CERM
0201
2 6.3V
X5R 2 6.3V
X5R-CERM1 255K 1 2
0201-MUR 402 1%
GND_AUDIO_CODEC PP_VPROG_CP_R 1/20W 5%
39 18
VOLTAGE=4.7V MF 1/20W SIGNAL_MODEL=EMPTY
MIN_LINE_WIDTH=0.6 MM 2 201
MF
CRITICAL MIN_NECK_WIDTH=0.2 MM 201 1 C3632
NOSTUFF 100PF
C3605 R3696 5%
4.7UF 2 25V
NP0-CERM
2 1 L81_FLYP PP_VPROG_MB_R 1
0 2 LDO10 0201
29 39
MIN_LINE_WIDTH=0.3MM VOLTAGE=4.7V
MIN_NECK_WIDTH=0.15MM MIN_LINE_WIDTH=0.6 MM 5%
20%
6.3V
1 C3613 MIN_NECK_WIDTH=0.2 MM 1/20W
VPROG_CP G10
MF
0.1UF
G1
VCP0 G8
VCP1 G9
A9
VL A8
VP0 E8
VP1 E9
VPROG_MB H1
X5R-CERM1 201
402 10% CRITICAL
L81_FLYC 16V
2 X5R-CERM C3607
VA
VD
MIN_LINE_WIDTH=0.3MM 0201
CRITICAL MIN_NECK_WIDTH=0.15MM 4.7UF
C3606 1 2
4.7UF
2 1 CRITICAL 0.15MM 20%
L81_FLYN 6.3V
MIN_LINE_WIDTH=0.3MM H10 FLYP U3600 +VCP_FILT H9 L81_PVCP 0.30MM X5R-CERM1
MIN_NECK_WIDTH=0.15MM 402
20%
6.3V J10 FLYC CS42L81-CWZR-A1 J9 L3620
X5R-CERM1 K10 WLCSP
GNDCP
K9 R3620 240-OHM-0.2A-0.8-OHM
402 FLYN -VCP_FILT L81_NVCP CRITICAL 3.3K 2
CODEC_HP_DET 1 CODEC_HP_DET_R 1 2 CONN_HP_HEADSET_DET
R3601 SYM 1 OF 2 0.15MM
0.30MM
C3608 18
0201 IN 20
2.21K2 NC_MIC1_BIAS NO_TEST=TRUE

H2 MIC1_BIAS AOUT1+ F10 NC_LEFT_CH_OUT_P 4.7UF 5%
1/32W
NOSTUFF
1 L81_MIC2_BIAS_IN NO_TEST=TRUE
18 AIN1P
E3 AIN1+ AOUT1_M F9 NO_TEST=TRUE
NC_LEFT_CH_OUT_N
1 2 GND_AUDIO_CODEC 18 39 MF
01005
1 C3620
1% E4 4700PF
1/20W 18 AIN1N AIN1- 20% 10%
MF H3 6.3V 2 10V
201 18 MIC1_BIAS_FILT MIC1_BIAS_FILT X5R-CERM1 X7R
L81_MIC2_BIAS
C CRITICAL AOUT2+
D10 NC_RIGHT_CH_OUT_P
NO_TEST=TRUE
402 201
PLACE L3600 TO 3605 CLOSE

C
C3611 1 AOUT2- D9 NO_TEST=TRUE
NC_RIGHT_CH_OUT_N TO THE HP CONNECTOR
1.0UF J3
20% CRITICAL MIC2_BIAS_IN
6.3V 2 G4
X5R C3612 MIC2_BIAS
0201-MUR K3 J4
4.7UF MIC2_BIAS_FILT_IN DP L81_MBUS_P 18 37 HP_LEFT_FILT OUT 22
1 2 L82_MIC2_BIAS_FILT F3 MIC2_BIAS_FILT DN K4 L81_MBUS_N 18 37
L81_MIC2_BIAS_FILT_IN 37 L81_AIN2_P C1 AIN2+ HPOUTA J8 CODEC_HP_LEFT MAKE_BASE=TRUE
20%
6.3V 37 L81_AIN2_N D1 AIN2M HPOUTB K8 CODEC_HP_RIGHT
X5R-CERM1
402 J1 CODEC_HP_HS3
C3616 HS3 TO HEADPHONE JACK
XW3602 HS4 K1 CODEC_HP_HS4
SHORT-8L-0.25MM-SM 0.01UF H4 HP_RIGHT_FILT OUT 22
2 1 1 2 NC_MIC3_BIAS NO_TEST=TRUE MIC3_BIAS HS3_REF K7 MIN_LINE_WIDTH=0.20MM
18 CODEC_HP_HS4_REF 37 HP_MIC_P
NOSTUFF 18 AIN3P C3 AIN3+ HS4_REF J7 MAKE_BASE=TRUE
10V 10% C2 H8
0201
X5R-CERM 18 AIN3N AIN3- HPDETECT CODEC_HP_DET 18
18 MIC3_BIAS_FILT G3 MIC3_BIAS_FILT
XW3603 C3617 HP_HS3_FILT IN 22
SHORT-8L-0.25MM-SM 0.01UF
2 1 1 2 LINEOUTA K6 NO_TEST=TRUE
NC_CODEC_LINE_OUT_L MIN_LINE_WIDTH=0.50MM
18 CODEC_HP_HS3_REF 37 HP_MIC_N
NO_TEST=TRUE
F4
NOSTUFF NC_MIC4_BIAS MIC4_BIAS LINEOUTB J6 NO_TEST=TRUE
NC_CODEC_LINE_OUT_R MAKE_BASE=TRUE
10V 10% 18 AIN4P D2 AIN4+ LINEOUT_REF H6

0201
X5R-CERM E2
18 AIN4N AIN4-
MIC4_BIAS_FILT F2 MIC4_BIAS_FILT FILT+ E1 L81_FILT
18 HP_HS4_FILT IN 22
FILT- F1 MIN_LINE_WIDTH=0.50MM
1 C3610 CODEC_HP_HS3_REF 18
MAKE_BASE=TRUE
4.7UF MIN_LINE_WIDTH=0.15MM
L81_SPEAKER_VQ C10 MIN_NECK_WIDTH=0.1MM
GNDHS
GNDHS
SPEAKER_VQ 20%
GNDP
GNDD
GNDA
NOSTUFF 2 6.3V
X5R-CERM1
CRITICAL 402
HP_HS3_REF_FILT 22
C3618 1 IN
B 2.2UF
B
E10
A10
K2
J2
G2
10% CODEC_HP_HS4_REF 18 MAKE_BASE=TRUE
6.3V 2 MIN_LINE_WIDTH=0.15MM
X5R MIN_NECK_WIDTH=0.1MM
402
NOSTUFF
GND_AUDIO_CODEC 18 39 XW3600
SHORT-8L-0.25MM-SM HP_HS4_REF_FILT IN 22
1 2 GND_AUDIO_CODEC18 39
NOSTUFF MAKE_BASE=TRUE
R3614 L81_MBUS_REF OUT 18 25
1
0 2
5% DIGITAL MIC
1/20W GND0 C6
MF B1
201 22 IN DMIC1_FF_SD R3612 1
1/32W 5%
2 22 L81_DMIC1_FF_SD
MF 01005
DMIC1_SD
GND1 D3
CODEC_AIN AIN1P 18
22 IN DMIC1_FF_SCLK R3613 1
1/32W 5%
2 22 L81_DMIC1_FF_SCLK
MF 01005
B2 DMIC1_SCLK CRITICAL D5
GND2
MAKE_BASE=TRUE
AIN1N 18
U3600 GND3 D6
B7 DMIC2_SD CS42L81-CWZR-A1
AIN3P 18
GND4 D7
NC_DMIC2_SCLK NO_TEST=TRUE
B6 DMIC2_SCLK WLCSP
1 C3690 AIN3N 18
GND5 D8
0.01UF SYM 2 OF 2
10% AIN4P 18
GND6 E5
I2S0_CODEC_ASP_MCK_R C8 MCLK
2 6.3V
X5R AIN4N 18
36 5 IN
GND7 E6
01005 A3 E7
36 5 IN I2S0_CODEC_ASP_BCLK ASP_SCLK GND8
I2S0_CODEC_ASP_LRCK B3 ASP_LRCK GND9 F5
36 5 IN
I2S0_CODEC_ASP_DOUT A2 ASP_SDIN GND10 F6
36 5 IN
36 5 IN I2S0_CODEC_ASP_DIN R3610
1/32W 5%
1 2 22 36 I2S0_CODEC_ASP_SDOUT
MF 01005
A1 ASP_SDOUT GND11 F7
GND12 F8
CODEC_MIC_BIAS_FILT MIC1_BIAS_FILT 18 I2S3_CODEC_XSP_BCLK B4 XSP_SCLK GND13 G5
MAKE_BASE=TRUE
36 5 IN
MIC3_BIAS_FILT 18 I2S3_CODEC_XSP_LRCK B5 XSP_LRCK_FSYNC GND14 G6
36 5 IN
MIC4_BIAS_FILT 18 I2S3_CODEC_XSP_DOUT A5 XSP_SDIN_DAC2_MUTE GND15 G7
36 5 IN
A 1 C3691 34 18 =PP1V8_AUDIO
36 5
25 18
IN
IN
I2S3_CODEC_XSP_DIN
L81_MBUS_REF
R3611
1/32W 5%
1 2 22
MF 01005
I2S3_CODEC_XSP_SDOUT A4
K5
XSP_SDOUT
MBUS_REF
GND16
GND17
H5
H7 SYNC_MASTER=N/A SYNC_DATE=N/A A
C5 J5 PAGE TITLE
0.01UF SPI1_CODEC_CS_L
10%
2 6.3V
X5R 1
NOSTUFF
36 5
36 5
OUT
OUT SPI1_CODEC_SCLK A6
CS*
CCLK
GND18
AUDIO: L81 CODEC
01005 R3640 36 5 IN SPI1_CODEC_MOSI B8 CDIN DRAWING NUMBER SIZE
1.00K
5% 36 5 OUT SPI1_CODEC_MISO A7 CDOUT Apple Inc. 051-9385 D
1/32W TSTI0 C4 REVISION
MF TSTI1 C7
2 01005 5 OUT GPIO_CODEC_IRQ_L B9 INT*
R
A.0.0
B10 TSTI2 D4 NOTICE OF PROPRIETARY PROPERTY: BRANCH
30 OUT PMU_GPIO_CODEC_HS_INT_L WAKE*
30 IN PMU_GPIO_CODEC_RST_L C9 RESET* THE INFORMATION CONTAINED HEREIN IS THE
18 OF 39
36 OF 154
IV ALL RIGHTS RESERVED
8 7 6 5 4 3 2 1
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LEFT SPEAKER AMP I2C ADDRESS: 1000000X

PART#
117S0002
QTY
4
DESCRIPTION
RES,MF,1/20W,0.0OHM,5,0201,SMD
REFERENCE DESIGNATOR(S)
R3742,R3743,R3752,R3753
CRITICAL
?
BOM OPTION
?
TABLE_5_HEAD
TABLE_5_ITEM
TABLE_5_ITEM
113S0022 4 RES,MF,1/10W,0OHM,5,0603,SMD,LF FL3740,FL3741,FL3750,FL3751 ? ?

34
18 =PPVCC_MAIN_AUDIO =PP1V7_VA_VCP 18 19 34
19
CRITICAL CRITICAL CRITICAL L19_L_VBOOST
1 C3741 1 C3742 1 C3743 1 C3744 CRITICAL CRITICAL
1 C3713 1 C3746
4.7UF 4.7UF 4.7UF 0.1UF 1 C3745 1 C3710 1 C3711 1 C3712 27PF 0.1UF
20% 20% 20% 10% 5% 10%
22UF 22UF 0.1UF 27PF 16V 6.3V
2 10V 10V 10V 16V
X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 20% 20% 10% 5% 2 NP0-C0G 2 X5R
0402 0402 0402 0201 10V
2 X5R-CERM
2 10V 2 16V 2 16V 01005 201
X5R-CERM X5R-CERM NP0-C0G
C3747
D
A1
B1
F5
0603-1 0603-1 0201 01005
C1
D1
A4
A5
D VBST VP
VA
4.7UF
1 2
CRITICAL 20% X5R-CERM1
CRITICAL 6.3V 402
L3740
2.2UH-20%-3.3A-0.115OHM U3740 R3745 SPKR_L_VSENSE_N
A2
CS35L19B-CWZR C3748 1
10K 2
1 2 L19_L_SWITCH WLCSP FILT+ F2 L19_L_FILT 4.7UF 19 37
B2 SW VER1 NOSTUFF 5%
TFA302610A-SM LDO_FILT C5 L19_L_LDO_FILT 1 2
1/20W
20% X5R-CERM1 C3767 1
MF
36 30 25 19 5 I2C0_SDA_1V8 D5
SDA 6.3V 402 100PF 201
VSENSE- E3 37 SPKR_L_VSENSE_N_FILT 5%
25V
I2C0_SCL_1V8 D6
SCL VSENSE+ E2 37 SPKR_L_VSENSE_P_FILT NP0-CERM 2
36 30 25 19 5
0201
A7 NOSTUFF
5 GPIO_SPKAMP_LEFT_IRQ_L INT* ISENSE- F1 37 SPKR_L_SES_N
A6 ISENSE+ E1 37 SPKR_L_SES_P C3760 R3744 SPKR_L_VSENSE_P
19 5 GPIO_SPKAMP_RST_L RESET* 0.01UF 1
10K 2 19 37
D7 ALIVE OUT+ D2 37 SPKR_L_P 1 2
19 5 GPIO_SPKAMP_KEEPALIVE 5%
OUT- C2 37 SPKR_L_N 10%
10V
X5R-CERM
0201 NOSTUFF 1/20W
C7 ADO OMIT_TABLE MF
1 OMIT_TABLE C3768 1 201
IREF+ B7 L19_L_IREF R3743 1
R3742 100PF
I2S1_SPKAMP_MCK_R E7 10 10 5%
19 5 MCLK 25V
5% 5% OMIT_TABLE NP0-CERM 2
E6 1/20W 1/20W CRITICAL 0201
19 5 I2S1_SPKAMP_BCLK SCLK MF MF
F6
2 201 CRITICAL 2 201 FL3741
19 5 I2S1_SPKAMP_LRCK LRCK/FSYNC R3740 MIN_LINE_WIDTH=0.5220-OHM-2.0A
MM
0.100 MIN_NECK_WIDTH=0.2 MM
F7 1 2 37 SPKR_L_FLR 1 2 SPKR_L_CONN_P
19 5 I2S1_SPKAMP_DOUT SDIN
19 37
MIN_LINE_WIDTH=0.5 1%
MM 0603
E5 MIN_NECK_WIDTH=0.2 MM
1/4W
SPEAKER CONNECTOR
I2S1_SPKAMP_DIN 1 NOSTUFF
19 5 SDOUT R3741 MF
0805 NOSTUFF 1 C3740 1 C3763
GNDP GNDA 44.2K 1 C3761 8.2PF 3.9PF
1% +/-0.1PF% +/-0.1PF
1/20W 18PF
MF 5% 2 25V
CER 2 25V
NP0-C0G-CERM
2 201 25V
C
A3
B3
B4
B5
B6
C3
C4
D3
D4
C6
E4
F3
F4
C
2 NP0-C0G-CERM 0201 0201
0201
OMIT_TABLE
CRITICAL APN 518S0672
FL3740 SPKR_L_CONN_P CRITICAL
220-OHM-2.0A 37 19
XW3774 J3700
1 2 SPKR_L_CONN_N 19 37
SM 78171-6006
MIN_LINE_WIDTH=0.5 MM 0603 37 19 SPKR_L_VSENSE_P 1 2 SIGNAL_MODEL=EMPTY M-RT-SM
7
MIN_NECK_WIDTH=0.2 MM NOSTUFF
1 C3749 1 C3766 37 19 SPKR_L_CONN_N
8.2PF 3.9PF XW3775 1
NOSTUFF +/-0.1PF% +/-0.1PF SM
2 25V
CER 25V SPKR_L_VSENSE_N 1 2 SIGNAL_MODEL=EMPTY 2
1 C3764 0201
2 NP0-C0G-CERM
0201
37 19
18PF 5 OUT SPK_ID 3

5% 4
2 25V
RIGHT SPEAKER AMP

NP0-C0G-CERM
0201 37 19 SPKR_R_CONN_P 5
XW3776 6
SM
37 19 SPKR_R_VSENSE_P 1 2 SIGNAL_MODEL=EMPTY
8
I2C ADDRESS: 1000001X 37 19 SPKR_R_CONN_N
XW3777
SM NOSTUFF NOSTUFF
34
18 =PPVCC_MAIN_AUDIO =PP1V7_VA_VCP 18 19 34 SPKR_R_VSENSE_N 1 2 SIGNAL_MODEL=EMPTY CRITICAL CRITICAL
19
CRITICAL CRITICAL CRITICAL L19_R_VBOOST

37 19
1 C3770 1 C3772
100PF 100PF
1C3751 1 C3752 1 C3753 1 C3754 CRITICAL CRITICAL 1 C3723 1 C3756 5% 5%
4.7UF 4.7UF 4.7UF 0.1UF
1 C3755 1 C3720 1 C3721 1 C3722 27PF 0.1UF PLACE XWS CLOSE TO CONNECTOR 2 16V
NP0-C0G 2 16V
NP0-C0G
20% 20% 20% 10% 22UF 22UF 0.1UF 27PF 5% 10% 01005 01005
2 10V
X5R-CERM 2 10V 10V 16V 20% 20% 10% 5% 2 16V
NP0-C0G 2 6.3V
X5R
0402 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 10V 2 10V 16V 16V 01005 201 NOSTUFF
0402 0402 0201 X5R-CERM X5R-CERM2 X5R-CERM 2 NP0-C0G C3757 CRITICAL NOSTUFF
A1
B1
F5
C1
D1
A4
A5
0603-1 0603-1 0201 01005 CRITICAL

4.7UF
VA 1 2 C3771 1 C3773 1
VBST VP 100PF 100PF
20% X5R-CERM1 5% 5%
B CRITICAL
L3750
2.2UH-20%-3.3A-0.115OHM
CRITICAL
U3750
6.3V 402
R3755 SPKR_R_VSENSE_N
16V
NP0-C0G 2
01005
16V
NP0-C0G 2
01005 B
A2
CS35L19B-CWZR C3758 1
10K 2
1 2 L19_R_SWITCH WLCSP FILT+ F2 L19_R_FILT 4.7UF 19 37
B2 SW VER1 NOSTUFF 5%
TFA302610A-SM LDO_FILT C5 L19_R_LDO_FILT 1 2
1/20W
20% X5R-CERM1 C3787 1 MF
36 30 25 19 5 I2C0_SDA_1V8 D5 SDA 6.3V 402 100PF 201
VSENSE- E3 37 SPKR_R_VSENSE_N_FILT 5%
25V
I2C0_SCL_1V8 D6 SCL VSENSE+ E2 37 SPKR_R_VSENSE_P_FILT NP0-CERM 2
36 30 25 19 5 0201
5 GPIO_SPKAMP_RIGHT_IRQ_L A7 INT* ISENSE- F1 37 SPKR_R_SES_N NOSTUFF
A6 RESET* ISENSE+ E1 37 SPKR_R_SES_P C3780 R3754 SPKR_R_VSENSE_P
19 5 GPIO_SPKAMP_RST_L 0.01UF 1
10K 2 19 37
D7 ALIVE OUT+ D2 37SPKR_R_P 1 2
19 5 GPIO_SPKAMP_KEEPALIVE 5%
OUT- C2 SPKR_R_N 37
10%
10V
X5R-CERM
0201 NOSTUFF 1/20W
MF
PP1V7_VA_VCP C7 ADO OMIT_TABLE C3788 1 201
39 34 29
IREF+ B7 L19_R_IREF 1OMIT_TABLE 1
E7 MCLK
R3753 R3752 100PF
I2S1_SPKAMP_MCK_R 10 10 5%
19 5
5% 5% OMIT_TABLE 25V
1/20W 1/20W NP0-CERM 2
19 5 I2S1_SPKAMP_BCLK E6 SCLK MF MF CRITICAL 0201
2 201 CRITICAL 2 201 FL3751
19 5 I2S1_SPKAMP_LRCK F6 LRCK/FSYNC R3750 MIN_LINE_WIDTH=0.5220-OHM-2.0A
MM
0.100 MIN_NECK_WIDTH=0.2 MM
F7 SDIN 1 2 37 SPKR_R_FLR 1 2 SPKR_R_CONN_P
19 5 I2S1_SPKAMP_DOUT 19 37
MIN_LINE_WIDTH=0.5 1%
MM 0603
E5 SDOUT 1 MIN_NECK_WIDTH=0.2 MM
1/4W NOSTUFF
I2S1_SPKAMP_DIN R3751 MF
19 5
44.2K 0805
1
NOSTUFF 1 C3750 1 C3783
GNDP GNDA 1%
1/20W
C3781 8.2PF
+/-0.1PF%
3.9PF
+/-0.1PF
18PF
MF 5% 2 25V
CER 2 25V
NP0-C0G-CERM
2 201 25V
A3
B3
B4
B5
B6
C3
C4
D3
D4
C6
E4
F3
F4
2 NP0-C0G-CERM 0201 0201

0201
OMIT_TABLE
A CRITICAL
FL3750 SYNC_MASTER=N/A SYNC_DATE=N/A A
220-OHM-2.0A PAGE TITLE
1 2 SPKR_R_CONN_N 19 37
AUDIO: SPEAKER AMP
MIN_LINE_WIDTH=0.5 MM 0603 DRAWING NUMBER SIZE
NOSTUFF
MIN_NECK_WIDTH=0.2 MM 1 C3759 1 C3786 Apple Inc. 051-9385 D
8.2PF 3.9PF REVISION
NOSTUFF +/-0.1PF%
1 C3784 2 25V
CER
+/-0.1PF
2 25V
R
A.0.0
0201 NP0-C0G-CERM NOTICE OF PROPRIETARY PROPERTY: BRANCH
18PF 0201
5% THE INFORMATION CONTAINED HEREIN IS THE
2 25V
NP0-C0G-CERM PROPRIETARY PROPERTY OF APPLE INC.
0201 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
37 OF 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
APN: 518S0828
D CRITICAL
D
J5400
502250-8037-B
F-RT-SM
40
38
22 CONN_ISP0_CAM_RF_SHUTDOWN 1
2 CONN_ISP1_CAM_FF_SHUTDOWN_L 22
36 22 CONN_I2C2_SCL_3V0 3
4 CONN_I2C2_SDA_3V0 22 36
5
6 CONN_ALS_IRQ_L 22
36 22 CONN_I2C1_SCL_1V8 7
8 CONN_I2C1_SDA_1V8 22 36
22 CONN_DMIC1_FF_SD 9
10 CONN_DMIC1_FF_SCLK 22
36 22 CONN_ISP0_CAM_RF_I2C_SCL 11
12 CONN_ISP0_CAM_RF_I2C_SDA 22 36
22 CONN_HALL_IRQ 13
15
14 PP3V0_S2R_HALL_FLT 21
16 CONN_ISP0_CAM_RF_RST_L 22
17
NC 18
19 NC
NC 20
21 NC
NC 22
23 NC
25
24 PP3V0_SENSOR_FLT 5 21
27
26 PP1V8_SENSOR_FLT 21
29
28 PP2V8_CAM_FLT 21
30 CONN_ISP0_CAM_RF_CLK 22 36
31
32 MIPI0C_CAM_RF_DATA_F_N<0> 21 37
37 21 MIPI0C_CAM_RF_DATA_F_P<0> 33
34
37 21 MIPI0C_CAM_RF_DATA_F_N<1> 35
36 MIPI0C_CAM_RF_DATA_F_P<1> 21 37
37
C 39 C
41
APN: 518S0828
CRITICAL
J5401
502250-8037-B
F-RT-SM
40
38
1
NC 2
3 NC
4
5 NC
NC 6
37 21 MIPI0C_CAM_RF_CLK_F_N 7
8 MIPI0C_CAM_RF_CLK_F_P 21 37
9
10 CONN_ISP1_CAM_FF_CLK 22 36
36 22 CONN_ISP1_CAM_FF_I2C_SCL 11
12 CONN_ISP1_CAM_FF_I2C_SDA 22 36
13
B 37 21 MIPI1C_CAM_FF_CLK_F_N 15
17
14
16
MIPI1C_CAM_FF_CLK_F_P 21 37
B
37 21 MIPI1C_CAM_FF_DATA_F_N<0>
18 MIPI1C_CAM_FF_DATA_F_P<0> 21 37
19
20 CONN_GYRO_IRQ2 22
22 CONN_PROX_IRQ_L 21
22 GPIO_BTN_SRL_L 5 30
30 5 GPIO_BTN_ONOFF_L 23
24 GPIO_BTN_VOL_UP_L 5
5 GPIO_BTN_VOL_DOWN_L 25
26
27 NC
NC 28 CONN_ACCEL_IRQ2_L 22
22 CONN_ACCEL_IRQ1_L 29
30 CONN_GYRO_IRQ1 22
18 CONN_HP_HEADSET_DET 31
32 CONN_HP_LEFT_FILT1 22
22 CONN_HP_RIGHT_FILT1 33
34 CONN_HP_HS3_FILT1 22
22 CONN_HP_HS3_REF_MIC2 35
36 CONN_HP_HS4_FILT1 22
22 CONN_HP_HS4_REF_MIC1 37
39
41
PAGE TITLE
SENSOR FLEX CONN

DRAWING NUMBER SIZE

REVISION
R
A.0.0
54 OF 154
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
NOSTUFF
R5500
1
0 2
5%
1/20W
MF
201
CRITICAL
L5500 L5550
90-OHM-50MA 240-OHM-0.2A-0.8-OHM
TCM0605-1
SYM_VER-1
PP3V0_S2R_HALL_FLT
D 37 7 BI MIPI0C_CAM_RF_DATA_N<1> 1 4 MIPI0C_CAM_RF_DATA_F_N<1> BI 20 37
34 23 =PP3V0_S2R_HALL 1
0201
2
VOLTAGE=3.0V
20
D
1 C5550 1 C5551 1 C5552 1 C5553 MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
MIPI0C_CAM_RF_DATA_P<1> 2 3 MIPI0C_CAM_RF_DATA_F_P<1> 82PF 1UF 1000PF 8.2PF NET_SPACING_TYPE=PWR
37 7 BI BI 20 37
5% 10% 10% +/-0.1PF% MAX_NECK_LENGTH=3 MM
25V 10V 16V 25V
2 NP0-C0G-CERM
2 X5R 2 X7R-CERM 2 CER
NOSTUFF 0201 402 0201 0201
R5501
1
0 2
5%
1/20W
MF L5560
201 240-OHM-25%-400MA
=PP1V8_SENSOR 1 2 PP1V8_SENSOR_FLT
NOSTUFF 34 20
R5510 0402
DCR 0.31
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 mm
1
0 2
1 C5560 1 C5561 1 C5562 1 C5563 MIN_NECK_WIDTH=0.2 mm
82PF 1UF 1000PF 8.2PF MAX_NECK_LENGTH=3 MM
5% 5% 10% 10% +/-0.1PF%
1/20W 2 25V 2 10V
NP0-C0G-CERMX5R 2 16V
X7R-CERM 2 25V
CER
MF 0201 402 0201 0201
201
CRITICAL
L5510
90-OHM-50MA
TCM0605-1
L5570
SYM_VER-1 240-OHM-25%-400MA
MIPI0C_CAM_RF_DATA_N<0> 1 4 MIPI0C_CAM_RF_DATA_F_N<0> =PP2V8_CAM 1 2 PP2V8_CAM_FLT

37 7 BI BI 20 37 34 20
0402 VOLTAGE=2.8V
DCR 0.31 MIN_LINE_WIDTH=0.6 mm
37 7 BI MIPI0C_CAM_RF_DATA_P<0> 2 3 MIPI0C_CAM_RF_DATA_F_P<0> BI 20 37
1 C5570 1 C5571 1 C5572 1 C5573 MIN_NECK_WIDTH=0.2 mm
82PF 1UF 1000PF 8.2PF MAX_NECK_LENGTH=3 MM
5% 10% 10% +/-0.1PF%
NOSTUFF 2 25V 2 10V 2 16V 25V
2 CER
NP0-C0G-CERM X5R X7R-CERM
R5511 0201 402 0201 0201
C 1
0
5%
2 C
1/20W
MF
L5580
201 240-OHM-25%-400MA
34 =PP3V0_SENSOR 1 2 PP3V0_SENSOR_FLT 5 20
NOSTUFF 0402
R5520 DCR 0.31 VOLTAGE=3.0V
1
0 2
1 C5580 1 C5581 1 C5582 1 C5583 1 C5584 MIN_NECK_WIDTH=0.2 MM
82PF 1UF 0.1UF 1000PF NET_SPACING_TYPE=PWR
8.2PF MAX_NECK_LENGTH=3 MM
5% 5% 10% 10% 10% +/-0.1PF%
1/20W 25V
2 NP0-C0G-CERM 2
10V 6.3V
2 X5R
16V
2 X7R-CERM
25V
2 CER
MF X5R
201 0201 402 201 0201 0201
CRITICAL
L5520
90-OHM-50MA
TCM0605-1
SYM_VER-1
37 7 IN MIPI0C_CAM_RF_CLK_N 1 4 MIPI0C_CAM_RF_CLK_F_N OUT 20 37
37 7 IN MIPI0C_CAM_RF_CLK_P 2 3 MIPI0C_CAM_RF_CLK_F_P OUT 20 37
NOSTUFF
R5521
1
0 2
5%
1/20W
MF
201
NOSTUFF
R5530
B 1
0 2
B
5%
1/20W
MF
201
CRITICAL
L5530
90-OHM-50MA
TCM0605-1
SYM_VER-1
37 7 IN MIPI1C_CAM_FF_CLK_P 1 4 MIPI1C_CAM_FF_CLK_F_P OUT 20 37
37 7 MIPI1C_CAM_FF_CLK_N 2 3 MIPI1C_CAM_FF_CLK_F_N 20 37
IN OUT
NOSTUFF
R5531
1
0 2
5%
1/20W
MF
201
NOSTUFF
R5540
1
0 2
5%
1/20W
MF
201
A CRITICAL
L5540
PAGE TITLE
90-OHM-50MA
TCM0605-1
SYM_VER-1 SENSOR CONN FILTERS 1
37 7 BI MIPI1C_CAM_FF_DATA_P<0> 1 4 MIPI1C_CAM_FF_DATA_F_P<0> BI 20 37
DRAWING NUMBER SIZE

REVISION
37 7 BI MIPI1C_CAM_FF_DATA_N<0> 2 3 MIPI1C_CAM_FF_DATA_F_N<0> BI 20 37
R
A.0.0
NOSTUFF NOTICE OF PROPRIETARY PROPERTY: BRANCH
R5541 THE INFORMATION CONTAINED HEREIN IS THE

1
0 2
5%
55 OF 154
1/20W SHEET
MF III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
201 IV ALL RIGHTS RESERVED 21 OF 39
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_ALT_HEAD

PART NUMBER
U5600,U5610,U5620,U5630,U5640,U5650,U5660,U5670
TABLE_ALT_ITEM
155S0643 155S0373 ? RADAR:8376668
U5600
800MHZ-100MA-27PF
0603
7 IN ISP1_CAM_FF_SHUTDOWN_L 1 IN1 OUT1 5 CONN_ISP1_CAM_FF_SHUTDOWN_L OUT 20
36 5 BI I2C2_SDA_3V0 2 IN2 OUT2 6 CONN_I2C2_SDA_3V0 BI 20 36
5 OUT GPIO_ALS_IRQ_L 3 IN3 OUT3 7 CONN_ALS_IRQ_L IN 20
36 5 BI I2C1_SDA_1V8 4 IN4 OUT4 8 CONN_I2C1_SDA_1V8 BI 20 36
D GND D
9
10
U5610
800MHZ-100MA-27PF
0603
18 IN DMIC1_FF_SD 1 IN1 OUT1 5 CONN_DMIC1_FF_SD IN 20
I2C1_SCL_1V8 2 CONN_I2C1_SCL_1V8 CRITICAL

36 5 IN IN2 OUT2 6 OUT 20 36
36 5 IN I2C2_SCL_3V0 3 IN3 OUT3 7 CONN_I2C2_SCL_3V0 OUT 20 36 U5660

ISP0_CAM_RF_SHUTDOWN CONN_ISP0_CAM_RF_SHUTDOWN 800MHZ-100MA-27PF
7 IN 4 IN4 OUT4 8 OUT 20 0603-1
GND 20 IN CONN_HP_HS4_FILT1 1 IN1 OUT1 5 HP_HS4_FILT OUT 18
20 IN CONN_HP_HS3_FILT1 2 IN2 OUT2 6 HP_HS3_FILT OUT 18
9
10
20 OUT CONN_HP_LEFT_FILT1 3 IN3 OUT3 7 HP_LEFT_FILT IN 18
NC 4 IN4 OUT4 8 NC
GND
9
10
U5620
800MHZ-100MA-27PF
0603
18 IN DMIC1_FF_SCLK 1 IN1 OUT1 5 CONN_DMIC1_FF_SCLK OUT 20
C 36 7
7
BI
IN
ISP0_CAM_RF_I2C_SDA
ISP0_CAM_RF_RST_L
2
3
IN2
IN3
OUT2 6
OUT3 7
CONN_ISP0_CAM_RF_I2C_SDA
CONN_ISP0_CAM_RF_RST_L OUT
BI 20 36
20
C
36 7 IN ISP0_CAM_RF_I2C_SCL 4 IN4 OUT4 8 CONN_ISP0_CAM_RF_I2C_SCL OUT 20 36
GND
NOSTUFF
DO NOT STUFF WITHOUT 1 C5620 CRITICAL
9
10
AUDIO TEM APPROVAL
AND RECHARACTERIZATION 27PF
5%
25V U5670
2 NP0-C0G 800MHZ-100MA-27PF
0201 0603-1
20 IN CONN_HP_HS4_REF_MIC1 1 IN1 OUT1 5 HP_HS4_REF_FILT OUT 18
20 IN CONN_HP_HS3_REF_MIC2 2 IN2 OUT2 6 HP_HS3_REF_FILT OUT 18
20 OUT CONN_HP_RIGHT_FILT1 3 IN3 OUT3 7 HP_RIGHT_FILT IN 18
U5630 NC 4 IN4 OUT4 8 NC

800MHZ-100MA-27PF
R5630 R5631 0603 GND
ISP0_CAM_RF_CLK 1
22 2 ISP0_CAM_RF_C 1
22 2 ISP0_CAM_RF_FILT CONN_ISP0_CAM_RF_CLK
36 36 1 IN1 OUT1 5
9
10
36 7 IN OUT 20 36
5% 5%
NC 2 IN2 OUT2 6 NC
1/16W NOSTUFF 1/16W
MF-LF MF-LF
NC 3 IN3 OUT3 7 NC
22 OHM
402 1 C5630 402
PMU_GPIO_HALL_IRQ 4 IN4 OUT4 8 CONN_HALL_IRQ
1000PF 30 OUT IN 20
PLACE IT NEAR U0600 10%

16V
2 X7R-CERM GND
0201
9
B 10
U5640 B
800MHZ-100MA-27PF
0603
36 7 IN ISP1_CAM_FF_I2C_SCL 1 IN1 OUT1 5 CONN_ISP1_CAM_FF_I2C_SCL OUT 20 36
5 OUT GPIO_PROX_IRQ_L 2 IN2 OUT2 6 CONN_PROX_IRQ_L IN 20

R5640 R5641 36 7 BI ISP1_CAM_FF_I2C_SDA 3 IN3 OUT3 7 CONN_ISP1_CAM_FF_I2C_SDA BI 20 36
ISP1_CAM_FF_CLK1
22 22
36 7 IN 2 36 ISP1_CAM_FF_C 1 2 36 ISP1_CAM_FF_FILT 4 IN4 OUT4 8 CONN_ISP1_CAM_FF_CLK OUT 20 36
5% 5%
1/16W 1/16W GND
MF-LF NOSTUFF MF-LF
402 1 C5640 402
9
10
22 OHM 1000PF
PLACE IT NEAR U0600 10%
16V
2 X7R-CERM
0201
U5650
800MHZ-100MA-27PF
0603
5 OUT GPIO_GYRO_IRQ1 1 IN1 OUT1 5 CONN_GYRO_IRQ1 IN 20
5 OUT GPIO_ACCEL_IRQ2_L 2 IN2 OUT2 6 CONN_ACCEL_IRQ2_L IN 20
5 OUT GPIO_GYRO_IRQ2 3 IN3 OUT3 7 CONN_GYRO_IRQ2 IN 20
5 OUT GPIO_ACCEL_IRQ1_L 4 IN4 OUT4 8 CONN_ACCEL_IRQ1_L IN 20
GND
9
10
PAGE TITLE
SENSOR CONN FILTERS 2

DRAWING NUMBER SIZE

REVISION
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8 7 6 5 4 3 2 1
L5700
D FERR-22-OHM-1A-0.065-OHM
1 2
TABLE_ALT_HEAD
D
25 E75_ACC_POUT_ID1 CONN_E75_ACC_POUT_ID1 24 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
0201 VOLTAGE=3.3V PART NUMBER
0.055 OHM DCR C MIN_LINE_WIDTH=0.6MM
TABLE_ALT_ITEM
DZ5791 MAX_NECK_LENGTH=3 MM 377S0116 377S0108 DZ5760 RDAR://PROBLEM/8370432

14.2V-6PF
TABLE_ALT_ITEM
155S0320 155S0513 L5700,L5701RDAR://PROBLEM/9625601

0201-1 TABLE_ALT_ITEM
A
155S0657 155S0537 FL5710,FL5750
TABLE_ALT_ITEM
155S0741 155S0397 L5757 RDAR://PROBLEM/11238851
L5701
FERR-22-OHM-1A-0.065-OHM
25 E75_ACC_POUT_ID2 1 2 CONN_E75_ACC_POUT_ID2 24
0201 C VOLTAGE=3.3V
0.055 OHM DCR MIN_LINE_WIDTH=0.6MM
DZ5792 MIN_NECK_WIDTH=0.2MM
14.2V-6PF NET_SPACING_TYPE=PWR FL5710
0201-1 120-OHM-200MA
A
24 DISCRETE_BTN_HOME_L 1 2 GPIO_BTN_HOME_L 5 30
IN OUT
0201
2
DZ5710 1 C5710 1 C5711
6.8V-100PF 8.2PF 8.2PF
0201 +/-0.1PF% +/-0.1PF%
2 25V
CER 2 25V
CER
1 0201 0201
L5757
FERR-70-OHM-4A
C 39 34 PPVBUS_USB_EMI 1
0603
2 CONN_E75_PPVBUS_USB
VOLTAGE=6.0V
24 C
2 1 MIN_LINE_WIDTH=0.6MM NOSTUFF
1 C5721 1 C5722 1
R5790 DZ5760 1 C5750 C5783 MIN_NECK_WIDTH=0.2MM
27PF 8.2PF 100K 27V-100PF 27PF 0.01UF NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM FL5740
5% +/-0.5PF 0402 5% 10% 120-OHM-200MA
2 25V 2 16V
5%
1/20W 25V
2 NP0-C0G 2 50V
X7R
NP0-C0G NP0-C0G-CERM MF 402 CONN_HALL2_IRQ 1 2 PMU_GPIO_HALL2_IRQ
0201 01005 0201 24 IN OUT 30
2 201 1 0201
2 NOSTUFF C5740
1
R5741
1
DZ5740 0 0
5%
6.8V-100PF 1/20W 5%
1/20W
0201 MF MF
1 2 201 2 201
USED TO BE C5740 27PF CAP USED TO BE C5741 27PF CAP

WHEN HALL2 WAS USED WHEN HALL2 WAS USED
USING PADS TO KEEP THIS UNUSED USING PADS TO KEEP THIS UNUSED
SIGNAL FROM FLOATING SIGNAL FROM FLOATING
NOSTUFF
L5730
240-OHM-0.2A-0.8-OHM
34 21 =PP3V0_S2R_HALL 1 2 PP3V0_S2R_HALL2_FLT 24
0201 NOSTUFF NOSTUFF NOSTUFF VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 mm
1 C5730 1 C5731 1 C5732 C5733
1 MIN_NECK_WIDTH=0.2 mm
82PF 1UF 1000PF NET_SPACING_TYPE=PWR
5% 10% 10% 0 MAX_NECK_LENGTH=3 MM
5%
2 25V 2 10V 2 16V 1/20W
B
NP0-C0G-CERMX5R X7R-CERM
B 0201 402 0201 MF
2 201
USED TO BE C5733 8.2PF CAP

WHEN HALL2 WAS USED
USING PADS TO KEEP THIS UNUSED
SIGNAL FROM FLOATING
PAGE TITLE
E75 DOCK SUPPORT

DRAWING NUMBER SIZE

REVISION
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8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
IO FLEX CONNECTOR
PN 516S0542 (PLUG - MALE)
CRITICAL
J5900
CPB6450-0101F
M-ST-SM
51 53
C 1 2
C
3 4 CONN_E75_ACC_POUT_ID1 23
5 6
25 OUT CONN_E75_ACC_DET_L 7 8 1 C5910
9 10 8.2PF
+/-0.5PF
11 12 16V
2 NP0-C0G-CERM
13 14 01005
36 25 BI CONN_E75_DPAIR2_P CONN_E75_ACC_POUT_ID2 23
CONN_E75_DPAIR2_N 15 16
36 25 BI
17 18
19 20
1 C5920
8.2PF
CONN_E75_DPAIR1_N 21 22 +/-0.5PF
BI
2 16V
36 25
CONN_E75_DPAIR1_P 23 24 NP0-C0G-CERM
36 25 BI 01005
25 26
NC
27 28
NC
29 30
31 32
24 23 CONN_E75_PPVBUS_USB 33 34 CONN_E75_PPVBUS_USB 23 24
35 36
37 38
1 C5900 39 40
8.2PF
+/-0.5PF 41 42
16V
2 NP0-C0G-CERM
01005 43 44
45 46
47 48
49 50
B 52 54
B
518S0692
CRITICAL
J5950
FF18-6A-R11AD-B-3H
F-RT-SM
23
PP3V0_S2R_HALL2_FLT 1
2
NC
3
4
NC
23 CONN_HALL2_IRQ 5
OUT
DISCRETE_BTN_HOME_L 6
23 OUT
PAGE TITLE
IO FLEX CONN
DRAWING NUMBER SIZE

REVISION
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34 =PP3V0_S2R_TRISTAR TRISTAR PART#
343S0614
QTY
1
DESCRIPTION
IC,ASIC,TRISTAR,CBTL1608,A1,WLCSP36
REFERENCE DESIGNATOR(S)
U5900
CRITICAL
CRITICAL
BOM OPTION
TABLE_5_HEAD
TABLE_5_ITEM
1 C5930 1 C5935 1 C5940

1.0UF 0.1UF 8.2PF
20% 10% +/-0.5PF
6.3V
2 X5R 2 6.3V 2 16V
X5R NP0-C0G-CERM =PP3V3_ACC
0201-MUR 201 01005 34
1 C5942 1 C5932
34 25 =PP1V8_S2R_USBMUX 8.2PF 0.1UF
+/-0.5PF 10%
2 16V 6.3V
2 X5R
D
NP0-C0G-CERM CRITICAL
1 C5931 1 C5941
D 01005 201
VDD_1V8 F3
VDD_3V0 F4
ACC_PWR D5
0.1UF 8.2PF L5930
10% +/-0.5PF PPVBUS_PROT 90-OHM-50MA
2 6.3V 2 16V
29
X5R NP0-C0G-CERM TCM0605-1
SYM_VER-1
201 01005 1 C5943 1 C5934 1 4 CONN_E75_DPAIR1_P BI 24 36
8.2PF 1UF
+/-0.5PF 10%
2 16V
NP0-C0G-CERM 2 25V
X5R
U5900 01005 0402 2 3 CONN_E75_DPAIR1_N BI 24 36
THS7383IYKAR
C3 WCSP
37 18 MIKEY_TS_P DIG_DP P_IN F6
C4 OMIT_TABLE CRITICAL CRITICAL
37 18 MIKEY_TS_N DIG_DN ACC1 C5 E75_ACC_POUT_ID1 23 2 2
A1 ACC2 E5 E75_ACC_POUT_ID2 23 DZ5900 DZ5901
36 25 USB_TS_BBMUX_P USB1_DP ESD0P2RF-02LS ESD0P2RF-02LS
TO BB USB B1 TSSLP-2-1 TSSLP-2-1
36 25 USB_TS_BBMUX_N USB1_DN DP1 A2 36 TS_E75_DPAIR1_P
C2 DN1 B2 36 TS_E75_DPAIR1_N
1 1
10 USB_BRICKID BRICK_ID
A3 DP2 A4 36 TS_E75_DPAIR2_P
ACCESSORY USB 36 4 BI USB_AP_P USB0_DP
B3 DN2 B4 36 TS_E75_DPAIR2_N
36 4 BI USB_AP_N USB0_DN
E2 CON_DET_L E3 30 PMU_E75_ACC_DET_L CRITICAL
UART2_TS_ACC_TXD UART0_TX
ACCESSORY UART 36 5
E1 L5931
36 5 UART2_TS_ACC_RXD UART0_RX OVP_SW_EN* D6 OVP_SW_EN_L OUT 29 90-OHM-50MA
TCM0605-1
SYM_VER-1
UART6_AP_TXD F2 UART1_TX SWITCH_EN E4 RST_AP_L
36 5 IN 4 26 30 39
1 4 CONN_E75_DPAIR2_P
AP DEBUG UART F1 BI 24 36
36 5 UART6_AP_RXD UART1_RX HOST_RESET B6 TS_HOST_RESET OUT 25
UART1_BB_RXD D2 UART2_TX SDA D3 I2C0_SDA_1V8

36 26 5 5 19 30 36
2 3 CONN_E75_DPAIR2_N
UART1_BB_TXD D1 D4 I2C0_SCL_1V8 BI 24 36
36 26 5 UART2_RX SCL 5 19 30 36
INT C6 PMU_GPIO_TS_INT
MLB_A MLB_A JTAG_AP_TCK_TS_R A5 5 30
BB DEBUG UART JTAG_CLK E6
(T’S OFF TO H5G UART1)
1
R5970 1
R5971 B5 BYPASS BYPASS_U5900 CRITICAL CRITICAL
JTAG_AP_TMS_TS_R JTAG_DIO 2 2
100K 100K DZ5902 DZ5903
C C
DVSS
DVSS
DVSS
5% 5%
1/20W 1/20W 1 C5944 1 C5933 ESD0P2RF-02LS ESD0P2RF-02LS
MF MF TSSLP-2-1 TSSLP-2-1
2 201 2 201 8.2PF 1.0UF
+/-0.5PF 20%
2 16V 6.3V
F5
C1
A6
NP0-C0G-CERM 2 X5R 1 1
01005 0201-MUR
R5930
0.00 2
36 4 JTAG_AP_TCK 1 PPVCC_MAIN 15 29 30 34 39
0%
1/32W
MF
01005 TABLE_ALT_HEAD
1 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

R5991 1 C5991 PART NUMBER
R5931 100K 8.2PF
0.00 2
TABLE_ALT_ITEM
5% +/-0.5PF 155S0773 155S0453 ? FL5990 RDAR://PROBLEM/10882925

36 4 JTAG_AP_TMS 1 1/32W 16V
PLACE NEAR U5900 MF 2 NP0-C0G-CERM
0% 2 01005 01005
1/32W
MF R5929
01005
1
0.00 2
18 OUT L81_MBUS_REF FL5990
0% R5990 120-OHM-210MA
1/32W 10K
MF 1 2 PMU_E75_ACC_DET_R_L 1 2 CONN_E75_ACC_DET_L
01005 IN 24
TRISTAR BASEBAND USB MUX 5%

1/32W
01005
2 CRITICAL
(NEEDED FOR MDM9600 BB) MF
01005
1 C5990
8.2PF
DZ5990
ESD0P2RF-02LS
K CRITICAL +/-0.5PF
16V TSSLP-2-1
=PP3V2_S2R_USBMUX 2 NP0-C0G-CERM
34
D5990 01005
SM-201 1
MLB_D&MLB_E DSF01S30SC
B
1 C5960
0.1UF
10%
A
B
2 6.3V
X5R MLB_D&MLB_E
201 1
R5961
10K
5%
1/20W
MF
2 201 34 25 =PP1V8_S2R_USBMUX
9
VCC
MLB_D&MLB_E
1 C5936
36 4 BI USB11_AP_BBMUX_P 5 M+ Y+ 1 USB_BBMUX_BB_P BI 25 26 36
0.1UF
10%
36 4 BI USB11_AP_BBMUX_N 4 M-
U5902 Y- 2 USB_BBMUX_BB_N BI 25 26 36 2 6.3V
X5R
201
PI3USB102ZLE
USB_TS_BBMUX_P 7 D+ TQFN 6
36 25
AP_WDOG_RESET_IN 2 74LVC1G32 R5935
USB_TS_BBMUX_N 6 D- MLB_D&MLB_E 4 IN SOT891
36 25
R5934 22
R5962 0.00 2 U5903 4 PMU_RESET_IN_R 1 2 PMU_RESET_IN OUT 30
0.00 2 TS_HOST_RESET 1 TS_HOST_RESET_R 1 5%
TS_BBMUX_EN_L 8 OE* SEL 10 PMU_GPIO_BBUSBTODOCK_EN_R 1 PMU_GPIO_BBUSBTODOCK_EN IN 30
25 IN NC 1/32W
0% 0% 5 3 MF
GND 1/32W 1/32W 01005
MF MF
01005 01005
3
MLB_D&MLB_E R5932
1
R5960 SEL Y+ Y- NOTE: ISOLATE SELECT SIGNAL FROM
2
220K 1
10K M+ M- PMU ON MLB_B AND MLB_C SO THE MUX
5% 0 IS PERMANENTLY POINTED TO THE DOCK MF 5%
1/20W 1/32W
MF DEFAULT => 1 D+ D- 01005
2 201
R5933
2
220K 1
MF 5%
1/32W
A BASEBAND USB MUX BYPASS 01005
MLB_B&MLB_C PAGE TITLE
R5965
0
TRISTAR
36 25 USB_TS_BBMUX_P 1 2 USB_BBMUX_BB_P 25 26 36 DRAWING NUMBER SIZE
5%
1/20W Apple Inc. 051-9385 D
MF REVISION
201 R
A.0.0
MLB_B&MLB_C NOTICE OF PROPRIETARY PROPERTY: BRANCH
R5966 THE INFORMATION CONTAINED HEREIN IS THE
USB_TS_BBMUX_N 1
0 2 USB_BBMUX_BB_N
36 25 25 26 36 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
5%
1/20W
59 OF 154
MF SHEET
201 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
CELLULAR/GPS HOTBAR PADS

OMIT
998-3732
J6000
HOT-BAR-PADS
HB-SM DEBUG
5 IN BB_JTAG_TMS_RF 1
2
34 =BATT_POS_F_3G 3 NOSTUFF
4 J6050
MM4829-2702
5 F-ST-SM
6 HSIC3_BB_STB 1
36 26 4
C 7
8 C
4
3
2
9
27 IN WLAN_TX_BLANK 10
39 30 25 4 OUT RST_AP_L 11
5 IN GPIO_BB_RADIO_ON_L 12
30 IN PMU_GPIO_BB_PMU_RST_L 13
5 OUT GPIO_BB_GSM_TXBURST 14
39 5 IN GPIO_BB_RST_L 15 NOSTUFF
5 OUT GPIO_BB_RESET_DET_L 16 J6051
17 MM4829-2702
F-ST-SM
36 5 IN GPIO_BB_HSIC_HOST_RDY 18
36 26 4 HSIC3_BB_DATA 1
36 5 OUT GPIO_BB_HSIC_RESUME 19
5 OUT BB_JTAG_TDO_RF 20
4
3
2
5 IN BB_JTAG_TDI_RF 21
5 IN BB_JTAG_TRST_RF_L 22
5 OUT GPIO_BB_GPS_SYNC 23
30 OUT PMU_GPIO_BB_HOST_WAKE 24
25
30 IN BB_VBUS_DET 26
36 25 BI USB_BBMUX_BB_P 27
36 25 BI USB_BBMUX_BB_N 28
29
36 25 5 OUT UART1_BB_RXD 30
36 25 5 IN UART1_BB_TXD 31
36 5 OUT UART1_BB_CTS_L 32
UART1_BB_RTS_L 33
B
36 5 IN
34 B
5 BI GPIO_AP_MODEM_WAKE 35
36 5 OUT GPIO_BB_HSIC_DEV_RDY 36
37
36 26 4 BI HSIC3_BB_STB 38
39
36 26 4 BI HSIC3_BB_DATA 40
41
5 IN BB_JTAG_TCK_RF 42
PAGE TITLE
CONNECTOR: CELLULAR
DRAWING NUMBER SIZE

REVISION
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WLAN/BT
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN

TABLE_5_HEAD
CONDUCTED TEST PORT

339S0171 1 WIFI MODULE - MURATA U6101_RF CRITICAL
TABLE_5_ITEM
ANTENNA CONNECTOR CRITICAL

J6191_RF CRITICAL
D PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD CRITICAL
J6190_RF
CRITICAL
MM8030-2600RK0
F-ST-SM
CRITICAL
U6104_RF
DPX205850DT-9038A1SJ
D
PART NUMBER
MM4829-2702
F-ST-SM
C6193_RF C6192_RF SM
3.9PF 8.2PF
TABLE_ALT_ITEM
339S0175 339S0171 U6101_RF WIFI MODULE - USI

1 RF_ANT 1 2 RF_ANT_MATCH1 2 1 RF_CAL 1 2 RF_CAL_MATCH 5 COM HI 1
WIFI_50S WIFI_50S WIFI_50S WIFI_50S
TABLE_ALT_ITEM
311S0548 311S0398 U6102_RF 50_OHM 50_OHM OUT IN 50_OHM 50_OHM

+/-0.1PF CRITICAL +/-0.25PF% LO 3
50V 25V
1 C6191_RF
2
3
4
NP0-CERM GND 1 NP0-C0G 1
0402 0.2PF 0201 GND
4
3
1 +/-0.05PF NOSTUFF NOSTUFF
2 50V
6
4
2
NOSTUFF NP0-CERM
0402
L6191_RF L6192_RF
L6190_RF 5.6NH-3%-0.35A 5.6NH-3%-0.35A
0201
5.6NH+/-0.3NH 0201
XW6102_RF 0402
SHORT-0402
2 2
34 =BATT_VCC 1 2 39 BATT_VCC_WLAN
2
1 C6101_RF 1 C6102_RF
10UF 27PF
20% 5%
2 6.3V
CERM-X5R 2 16V
0402-1 NP0-C0G
01005
R6108_RF
0.00 2
39 PP_WLAN_VDDIO_1V8 1 PP_WL_BT_VDDIO_AP 14 27
VOLTAGE=1.8V 0% VOLTAGE=1.8V
1 C6103_RF 1 C6104_RF 1/32W
MF
0.01UF 27PF 01005
10% 5%
NOSTUFF 2 6.3V
X5R 2 16V
NP0-C0G
1 1 01005 01005
R6105_RF R6107_RF
10K 10K
C
5%
1/32W
5%
1/32W
C
15
BATT_VCC 27
VBATT_RF_VCC 46
VBATT_RF_VCC 47
MF MF
2 01005 2 01005 CRITICAL
32K INTERFACE TO AP C6107_RF
XW6101_RF VDDIO_1P8V
SHORT-01005 8.2PF
14 CLK32K_AP 1 2 WLAN_CLK32K 32 CLK32K_AP 2G_ANT 42 38 50_WLAN_G 1 2 38 50_WLAN_G_1
5G_ANT 52 38 50_WLAN_A
GPIO_6 6 GPIO_6 +/-0.25PF%
25V
29 HOST_WAKE_BT 34 HOST_WAKE_BT OUT 14 CRITICAL NP0-C0G
0201
WLAN_BUCK_OUT VIN_1P2LDO C6108_RF
BT_WAKE 39 BT_WAKE IN 14 4.7PF
1 2 38 50_WLAN_A_DIPLX
27 14 IN WLAN_REG_ON 31 WL_REG_ON U6101_RF NOSTUFF +/-0.1PF
LBEE5ZHTWC501 1 C6111_RF 25V
CRITICAL BT_REG_ON 30 BT_REG_ON LGA BT_UART_RXD 38 BT_UART_RXD COG-CERM
14 IN IN 14
0.2PF 0201
L6111_RF JTAG_SEL 14 OMIT_TABLE BT_UART_TXD 37 BT_UART_TXD OUT 14
+/-0.1PF
25V
2.5UH-30%-0.7A-0.24OHM JTAG_SEL
BT_UART_RTS* 35 BT_UART_RTS_L
2 COG-CERM
OUT 14 201
1 2 WLAN_SR_VLX1 28 SR_VLX BT_UART_CTS* 36 BT_UART_CTS_L 14
IN
0603
50_HSIC_WLAN_DATA 24 WLAN_HSIC_DATA BT_PCM_CLK 3 BT_PCM_CLK
27 14 BI 14
27 14 50_HSIC_WLAN_STROBE 25 WLAN_HSIC_STROBE BT_PCM_SYNC 5 BT_PCM_SYNC 14

BI
BT_PCM_OUT 2 BT_PCM_OUT OUT 14
1 C6109 BT_PCM_IN 4 BT_PCM_IN IN 14
4.7UF 1
20% R6109_RF GPIO_0 9 HOST_WAKE_WLAN
2 6.3V OUT 14 27
X5R-CERM1 10K GPIO_1 8 AP_HSIC3_RDY
402 5% IN 14 27
1/32W GPIO_2 10 WLAN_HSIC3_RESUME 1
MF 14
PP PP6101_RF
P4MMSM
2 01005 NC
40 RF_SW_CTRL_3 GPIO_3 12 AGG_CHANNEL 27
NO LONGER NEEDED BASED GPIO_4 7 WLAN_UART_RXD IN 14 27

1
R6111_RF
ON AND GATE REMOVAL
GPIO_5 11 WLAN_UART_TXD 10K
B GPIO_12 13 HSIC_DEVICE_RDY
OUT
OUT
14 27
27
5%
1/32W
MF
PULL DOWN RESISTORS B
2 01005
GND THRML_PAD
17
18
19
20
21
22
1
16
23
26
33
41
43
44
45
48
49
50
51
53
54
55
56
57
58
59
60
GPIO6 SDIO_DATA<1> SDIO_DATA<2> MODE DEFAULT ARM STATE
CHANGE LIST
0 X X SDIO IN RESET 07FEB2012 MUSHTAQ COPIED FROM N41, ADDED J2 ANT MATCH/CONN
1 X 0 GSPI IN RESET
C6107 FROM 20PF TO 8.2PF, C6108 FROM 10PF TO 4.7PF
U6104 FROM SOSHIN TO MURATA LFD212G45DS5D355
1 0 1 HSIC OUT OF RESET
1 1 1 BOOTLESS HSIC IN RESET WLAN_REG_ON 1 13FEB2012 AMANDA CHANGED OMIT TO OMIT_TABLE AND UPDATED
PP PP6102_RF
27 14
P4MM SM BOM OPTION TABLES TO ALTERNATE TABLES
27 14 HOST_WAKE_WLAN 1 PP PP6103_RF
P4MM SM
REMOVED BOM TABLE FOR C6111_RF (NOW ALWAYS NOSTUFF)
AP_HSIC3_RDY 1
27 14 IN PP_WL_BT_VDDIO_AP 27 14 PP PP6104_RF
P4MM SM
27 14 DEV_HSIC3_RDY 1 PP PP6105_RF
P4MM SM
1 WLAN_UART_RXD 1 PP PP6106_RF
R6113_RF 27 14
P4MM SM
10K WLAN_UART_TXD 1
5% 27 14 PP PP6107_RF
1/32W P4MM SM
MF
2 01005
27 HSIC_DEVICE_RDY U6102_RF
74AUP1G08GF
SOT891
6
VCC
R6114_RF AGG_CHANNEL 1 PP PP6109_RF
A
27
0.00 2 P4MM
A
SM
2 A Y 4 DEV_HSIC3_RDY AGG_CHANNEL 1 WLAN_TX_BLANK
R6112_RF 14 27 27 OUT 26
27 14 50_HSIC_WLAN_DATA 1
PP PP6110_RF SYNC_MASTER=N/A SYNC_DATE=N/A
1.00M2
1 1 B
0% P4MM SM
PAGE TITLE
WLAN_REG_ON WLAN_REG_ON_RC 1/32W
IN
WIFI/BT
27 14
MF 50_HSIC_WLAN_STROBE 1
1% 01005
27 14 PP PP6111_RF
P4MM SM
1/32W 5 NC
MF
1 C6110_RF NC
GND 27 HSIC_DEVICE_RDY 1 PP PP6112_RF DRAWING NUMBER SIZE
01005 0.22UF
20%
P4MM SM

3
2 6.3V
X5R REVISION
0201 R
A.0.0
61 OF 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
155S0644 155S0274 ? RDAR://PROBLEM/11282371
FL7500,L3620,L5550,L5730
C C
CRITICAL
34 =BATT_POS_CONN
J7500
TP7500
1
BATT-J2
A F-RT-SMTH
TP-P55 7
NOSTUFF
FL7500 6
240-OHM-0.2A-0.8-OHM
UART5_BATTERY_TRXD 1 2 BATT_SWI_CONN 1 HDQ
30 5 BI
0201 2 THERM
3 PACK_NEG
4 PACK_POS
30 BI BATTERY_NTC 1 C7522 1 C7523 1 C7524 1 C7525 1 C7526 1 C7527 5 SENSE
NET_SPACING_TYPE=ANLG
33PF 33PF 1000PF 82PF 33PF 4.7PF
5% 5% 10% 5% 5% +/-0.1PF
2 25V
NPO-C0G
25V
2 NPO-C0G 2 16V
X7R-CERM
25V 2 50V
2 NP0-C0G-CERM C0G-CERM 2 50V
C0G-CERM
8
NOTE: REMOVED R7541 0201 0201 0201 0201 0402 0402
HAS TP7502
29 BATT_SNS
NET_SPACING_TYPE=ANLG APN:516S0926
B B
TP7501
1
A
TP-P55
NOSTUFF
TP7502
1
A
TP-P55
NOSTUFF
TP7503
1
A
TP-P55
NOSTUFF
A SYNC_MASTER=MADHAVI SYNC_DATE=12/06/2011 A
PAGE TITLE
POWER: BATTERY CONNECTOR

DRAWING NUMBER SIZE

REVISION
R
A.0.0
75 OF 154
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
PLACEMENT_NOTE=PLACE NEAR L8225.1
PPVCC_MAIN
VCC_MAIN BYPASS CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
15 25 29 30 34 39
CRITICAL
L8100 OMIT_TABLE
PP1V1_CPU0_FET
NOSTUFF
30 39
TOTAL CAPS = ~400UF C8166 1 C8165 1 1 C8154 1 C8155 1 C8156 1 C8157 1 C8162 1 C8187 1 C8188 1 C8193 1 C8194 1 C8130 1 C8131 1 C8163 1 C8164 1.0UH-20%-2.74A-59MOHM CRITICAL CRITICAL CRITICAL CRITICAL
PLACE ONE 10UF CAP 150UF 150UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 1UF 82PF 8.2PF BUCK0A_LX0 1 2
1 C8100 1 C8101 1 C8120 1 C8121
20% 20% 20%
6.3V
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 5% +/-0.1PF% 39
22UF 22UF 22UF
22UF
AT EACH VDD INPUT 6.3V 2 6.3V 2 2 X5R 2 6.3V
X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
X5R 2 6.3V
CERM-X5R 2 6.3V
X5R 25V 25V
2 NP0-C0G-CERM2 CER
MIN_NECK_WIDTH=0.25 MM PSB32251E-SM 20% 20% 20% 20%
TANT-1 TANT-1 NET_SPACING_TYPE=PWR 6.3V 6.3V 6.3V
B15G B15G 603 603 0402 0402 0402 0402 0402 0402 603 0402 0201 0201 0201 DIDT=TRUE
CRITICAL 2 X5R-CERM-1 2 X5R-CERM-1 2 X5R-CERM-1 2 6.3V
X5R-CERM-1
ESR MAX=70MOHM ESR MAX=70MOHM L8101 OMIT_TABLE 603 603 603 603
TABLE_5_HEAD
1.0UH-20%-2.74A-59MOHM
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION NOSTUFF
PPVCC_MAIN_CPU0 29 PPVCC_MAIN_CPU1 29 39 BUCK0A_LX1 1 2
CRITICAL CRITICAL CRITICAL
TABLE_5_ITEM 34 34 PPVCC_MAIN_SOC 29 34 MIN_LINE_WIDTH=0.6 MM
PSB32251E-SM
152S1637 6 IND,1.0UH,20%,59MO,2.74A L8100,L8101,L8102,L8103,L8109,L8110 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR 1 C8180 1 C8181 1 C8184
CRITICAL CRITICAL CRITICAL CRITICAL DIDT=TRUE
NOSTUFF
152S1638 1 IND,1.0UH,20%,64MO,2.3A L8104 CRITICAL
TABLE_5_ITEM 1 C8159 1 C8190 1 C8158 1 C8189 1 C8160 1 C8161 1 C8191 1 C8192 XW8100 20%
10UF 10UF
20%
10UF
20%
10UF 10UF 10UF 10UF BUCK0A_FB 1 2 6.3V 6.3V 6.3V
20% 20% 20% 20% 10UF 10UF 10UF 10UF 39
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
D PART NUMBER ALTERNATE FOR

PART NUMBER
BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
2 6.3V
CERM-X5R
0402
6.3V
2 CERM-X5R
0402
2 6.3V
CERM-X5R
0402
2 6.3V
CERM-X5R
0402
20%
6.3V
2 CERM-X5R
0402
20%
6.3V
2 CERM-X5R
0402
20%
6.3V
2 CERM-X5R
0402
20%
6.3V
2 CERM-X5R
0402
SM
CRITICAL
0402 0402 0402
D
TABLE_ALT_ITEM
L8102 OMIT_TABLE
152S1452 152S1292 ? L8111 RDAR://PROBLEM/8376462 1.0UH-20%-2.74A-59MOHM PP1V1_CPU1_FET 30 39
NOSTUFF
TABLE_ALT_ITEM
138S0676 138S0654 ? ? CRITICAL 39 BUCK0B_LX0 1 2

CRITICAL CRITICAL CRITICAL CRITICAL
C8100,C8101,C8102,C8103,C8104,C8105,C8107,C8108,C8109,C8110,C8111,C8112,C8113,C8114,C8117,C8118,C8119,C8120,C8121,C8222,C8123,C8195 L8112 MIN_LINE_WIDTH=0.6 MM
NET_SPACING_TYPE=PWR PSB32251E-SM 1 C8102 1 C8103 1 C8122 1 C8123
2.2UH-20%-4A-32MOHM DIDT=TRUE
CRITICAL
OMIT_TABLE 22UF 22UF 22UF 22UF
PPVCC_MAIN 1 2 SW_CHGA
L8103 OMIT_TABLE 20% 20% 20% 20%
NOSTUFF 39 34 30 29 25 15
U8100 1.0UH-20%-2.74A-59MOHM 6.3V 6.3V 6.3V 6.3V
2 X5R-CERM-1 2 X5R-CERM-1 2 X5R-CERM-1 2 X5R-CERM-1
R8170 PIME101E-SM
OVP_SW_EN_L 4.7K 2 1 2 3 DCR=32MOHM MAX CRITICAL K

NET_SPACING_TYPE=SWITCHNODE
F22 D2018 39 BUCK0B_LX1 1 2
603 603 603 603
RDSON=0.0136@VGS=-2.5V
1 F23 FCBGA
29 25
S D8100 DIDT=TRUE
SYM 2 OF 3
NET_SPACING_TYPE=PWR PSB32251E-SM
NOSTUFF
5% SOD-123W G22 A9 DIDT=TRUE
NOSTUFF CRITICAL CRITICAL CRITICAL
1/20W
MF 4 G CRITICAL PMEG4030ER XW8101
G23 BUCK0A_LX0 B9 1 C8182 1 C8183 1 C8185
201 Q8104 A 39 BUCK0B_FB 1 2
FDMC6683 H22 CHG_LX A11 NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.25 MM SM 10UF 10UF 10UF
MIN_NECK_WIDTH=0.20 MM 20% 20% 20%
MLP3.3X3.3 H23 BUCK0A_LX1 B11 6.3V 6.3V 6.3V
R8172 CRITICAL
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
0 J22 BUCK0A_FB E11 0402 0402 0402
D 28 BATT_SNS 1 2 BATT_SNS_R
J23
L8104 OMIT_TABLE
5 5% NOSTUFF 1.0UH-20%-2.3A-64MOHM
1/20W M14 VBAT A5 PP1V1_CPUB
1 C8172 1 BUCK0C_LX0 1 2
ID=12.0A
MF
201 R8173 M17 IBAT_S BUCK0B_LX0 B5
39 34 39
0.022UF 499
MIN_NECK_WIDTH=0.25 MM PSB25201E-SM
LAYOUT NOTE - 10% 1% P15 A7 NET_SPACING_TYPE=PWR
DIDT=TRUE
NOSTUFF CRITICAL CRITICAL ADDITIONAL DISTRIBUTED
12UF (NO DERATING)
MOSFET FDMC6676BZ R3172- PLACE NEAR BMU 2 25V
X7R 1/20W BUCK0B_LX1 XW8102 1 C8104 1 C8105
C3172- PLACE NEAR PMU MF P16 B7
0402
R3173- PLACE NEAR PMU 2 201 P17 IBAT
39 BUCK0C_FB 1 2 22UF 22UF
CHANNEL P-TYPE BUCK0B_FB E6 NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.25 MM SM 20% 20%
39 34 32 29
PPBATT_VCC P18 MIN_NECK_WIDTH=0.20 MM 6.3V 6.3V
2 X5R-CERM-1 2 X5R-CERM-1
RDS(ON) 27 MOHM @-4.5V ACT_DIO M18 ACT_DIO E1 CRITICAL 603 603
IMAX 6.9 A
NOSTUFF
E22 BUCK0C_LX0 E2 L8105 ADDITIONAL DISTRIBUTED
E23
1.0UH-20%-3.9A-0.035OHM 98UF (NO DERATING)
XW8114 BUCK0C_FB F5
VGS MAX +/- 25V SHORT-0201 VCENTER 1 2 PP1V2_SOC
K22 34 39
4 PPVBUS_USB 2 1 PMU_VCENTER
K23 A13
MIN_NECK_WIDTH=0.25 MM PILE32251E-SM
BUCK2_LX0
C C
MIN_LINE_WIDTH=0.60MM MIN_LINE_WIDTH=0.60MM 39 DIDT=TRUE
PPVBUS_PROT
E20
BUCK2_LX0 B13 L8106 1 C8107 1 C8108 1 C8195
25 MAX_NECK_LENGTH=3 MM 1.0UH-20%-3.9A-0.035OHM
USB/BAT
MIN_LINE_WIDTH=0.60MM MAX_NECK_LENGTH=3 MM
VOLTAGE=6V VOLTAGE=6V
E21
A15 39 BUCK2_LX1 22UF 22UF 22UF
MIN_NECK_WIDTH=0.20MM 20% 20% 20%
BUCK
CRITICAL BUCK2_LX1 B15 MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM 1 2
NOSTUFF
NET_SPACING_TYPE=PWR CRITICAL CRITICAL F19 NET_SPACING_TYPE=PWR
2 6.3V 2 6.3V 2 6.3V
K
DIDT=TRUE
DZ8120 MAX_NECK_LENGTH=3 MM
A17
X5R-CERM-1 X5R-CERM-1 X5R-CERM-1
3
2
1
PILE32251E-SM
R81161 CRITICAL
BZT52C10LP
VOLTAGE=6.0V 1 C8125 1 C8126 F20
BUCK2_LX2
39 BUCK2_LX2
CRITICAL
603 603 603
Q8123 4.7UF 4.7UF B17 MIN_LINE_WIDTH=0.6 MM

470K
1% FDMC6676BZ
S LLP
CRITICAL 10%
35V
10%
35V
F21
A19
NC
DIDT=TRUE L8107
1/20W C8124 1 2 X5R-CERM 2 X5R-CERM G19 1.0UH-20%-3.9A-0.035OHM
A
MF MLP3.3X3.3 G 4 0603 0603 BUCK2_LX3 B19

201 2 NOTE: 10V ZENER 2.2UF G20 NC 1 2
10% BUCK2_FB E15 39 BUCK2_FB CRITICAL CRITICAL CRITICAL
G21 NET_SPACING_TYPE=PWR
VBUS_PROT_G 25V
X5R-CERM 2 LAYOUT NOTE: PLACE VBUS
PILE32251E-SM 1 C8117 1 C8118 1 C8119
MIN_LINE_WIDTH=0.20MM 805 RIGHT AT THE PIN H19 22UF 22UF 22UF
D
MIN_NECK_WIDTH=0.1MM G1 39 BUCK3_LX0 20% 20% 20%
NET_SPACING_TYPE=ANLG H20 MIN_LINE_WIDTH=0.6 MM
NOSTUFF 6.3V 6.3V 6.3V
BUCK3_LX0 G2
R81301 NET_SPACING_TYPE=PWR XW8103 2 X5R-CERM-1 2 X5R-CERM-1 2 X5R-CERM-1
5
DIDT=TRUE
H21 1 2 603 603 603
220K BUCK3_FB H5 39 BUCK3_FB
34 PPVBUS_USB_DCIN 1% LAYOUT NOTE: PLACE J19 NET_SPACING_TYPE=PWR
SM
1/20W RIGHT AT THE PIN J20
MF A3
201 2 39 BUCK4_LX0
J21
R8196 BUCK4_LX0 B3
OVP_SW_EN_L 4.7K 2 OVP_SW_EN_L_R K20 DIDT=TRUE

1 BUCK4_FB D4 39 BUCK4_FB
USB REVERSE VOLTAGE PROTECTION 29 25
1% NOSTUFF
K21 NET_SPACING_TYPE=PWR
E19
LDO BYPASS
1/20W
MF 1 C8196 A21 39 BUCK5_LX0 CRITICAL
K19
PP3V0_GRAPE
201
0.022UF BUCK5_LX0 B21 MIN_LINE_WIDTH=0.6 MM
L8109 OMIT_TABLE ADDITIONAL DISTRIBUTED
39 34 29
LAYOUT NOTE: 10%
25V
L23 VBUS_OVP_OFF
A23 (PP3V3_OUT)
DIDT=TRUE 1.0UH-20%-2.74A-59MOHM 27UF (NO DERATING)
R8196, C8196 CAN BE 2 X7R
39 34 29 19 PP1V7_VA_VCP ANYWHERE BET.TRISTAR 0402 BUCK5_BYP 1 2 PP1V8_S2R
AND PMU 34 29 PPVCC_MAIN_CPU0 A10 B23 29 34 39
39 34 29 PP3V2_S2R_USBMUX B10 VDD_BUCK0A PSB32251E-SM
BUCK5_FB E18 39 BUCK5_FB NOSTUFF CRITICAL CRITICAL
39 34 29 PP3V0_S2R_HALL NET_SPACING_TYPE=PWR
34 29 PPVCC_MAIN_CPU1 A6 MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM XW8104 1 C8109 1 C8110
39 34 29 PP1V0 VDD_BUCK0B (150MA; 1.2-3.1V) 1 2
B6 VLDO1 P9 PP3V0_GRAPE 29 34 39 22UF 22UF
39 34 29 PP3V3_ACC SM 20% 20%
39 34 30 29 25 15 PPVCC_MAIN D1 VLDO2 P4 (100MA; 1.65-1.805V; BUCK3) PP1V7_VA_VCP 19 29 34 39 2 6.3V 6.3V
39 29 LDO5 VDD_BUCK0C (50MA; 2.5-3.3V) CRITICAL X5R-CERM-1 2 X5R-CERM-1
D2 VLDO3 N8 PP3V2_S2R_USBMUX 29 34 603 603
B B
39
39 29 18 LDO10 (100MA; 1.8-3.3V) L8110 OMIT_TABLE
34 29 PPVCC_MAIN_SOC A14 VLDO4 P2 PP3V0_SENSOR 29 34 39 ADDITIONAL DISTRIBUTED
B14 VDD_BUCK2_01 P8 (300MA; 1.7-3.0V) 1.0UH-20%-2.74A-59MOHM 64UF (NO DERATING)
VLDO5 LDO5 29 39
CRITICAL CRITICAL (150MA; 2.5-3.6V) 1 2 PP1V2_S2R
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL A18 VLDO6 P10 PP3V3_ACC 29 34 39
29 34 39
C8133 1 C8132 1
C8149 1 C8148 1 C8146 1 C8145 1 C8144 1 C8147 1 B18 VDD_BUCK2_23 VLDO7 P3 (50MA; 1.2-3.1V) PP3V0_S2R_TRISTAR 29 34
PSB32251E-SM
NOSTUFF CRITICAL CRITICAL
4.7UF 4.7UF
LDO
2.2UF 4.7UF 1UF 2.2UF 10UF 2.2UF PPVCC_MAIN H1 M6 (15MA; 2.0-3.55V) PP3V0_S2R_HALL XW8105
20%
6.3V
20%
6.3V 10%
6.3V 2
20%
6.3V
10%
6.3V 2
10%
6.3V 2
20%
6.3V
10%
6.3V 2
39 34 30 29 25 15
VDD_BUCK3
VLDO8
(300MA; 1.2-3.0V)
29 34 39
1 2
1 C8111 1 C8112
X5R-CERM1 2 X5R-CERM1 2 X5R X5R-CERM1 2 X5R X5R CERM-X5R 2 X5R
H2 VLDO9 P11 PP3V0_IO 29 34 39 22UF 22UF
402 402 SM 20% 20%
402 402 402 402 0402 402 A2 VLDO10 P6 (200MA; 2.5-3.55V) LDO10 18 29 39
2 6.3V 6.3V
VCC-MAIN
X5R-CERM-1 2 X5R-CERM-1
B2 VDD_BUCK4 VLDO11 M1 (250MA; 1.7-3.0V) PP2V8_CAM 29 34 39
CRITICAL 603 603
A22 VLDO12 P5 (150MA; 0.6-1.3V) PP1V0 29 34 39
L8111 ADDITIONAL DISTRIBUTED
39 34 29 PP3V0_SENSOR VDD_BUCK5 (650MA; 1.1V) 2.2UH-20%-3.3A-0.064OHM
B22 VLDO16 P14 PP1V1_SRAM 29 34 39 32UF (NO DERATING)
39 34 29 PP3V0_IO 1 2 PP3V3_OUT
L20 VCC_MAIN_S ON_BUF M16 (5MA; 1.8V) PP1V8_ALWAYS 29 34 39
34 39
34 29 PP3V0_S2R_TRISTAR PIME051E-SM
N15
39 34 29 PP2V8_CAM
CRITICAL CRITICAL
N16 VBUCK4 M2
39 34 29 PP1V1_SRAM
VCC_MAIN (RON=0.05 OHM MAX) NOSTUFF
1 C8113 1 C8114
N17 CPU1V2_SW L1 22UF 22UF
39 34 29 PP1V8_ALWAYS
XW8106 20% 20%
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL N18 CPU1V2_SW L2 1 2
2 6.3V 6.3V
X5R-CERM-1 2 X5R-CERM-1
C8169 1 C8168 1 C8167 1 C8153 1 C8152 1 C8151 1 SM 603 603
0.22UF 4.7UF 4.7UF 2.2UF 4.7UF 2.2UF N9 VDD_LDO1_6 VBUCK3 K2
20% 20% 20% 10% 20% 10%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V PP1V8_S2R N4 CPU1V8_SW J1 (RON=0.05 OHM MAX)
SWITCH POWER
X5R 2 X5R-CERM1 2 X5R-CERM1 2 X5R 2 X5R-CERM1 2 X5R 2 39 34 29 VDD_LDO2
0201 402 402 402 402 402 PPVCC_MAIN N7 PP1V2_S2R
VDD_LDO3_5_8 CPU1V8_SW J2
1 C8135 39 34 30 29 25 15
N3 VDD_LDO4_7 WDIG_SW K1 (RON=0.2 OHM MAX)
29 34 39
1UF PP1V2
10% N11 VDD_LDO9 34 39
LDO INPUT
2 6.3V
CERM N6 VDD_LDO10 PP1V8_S2R
402 29 34 39
N2 VDD_LDO11 MIN_LINE_WIDTH=0.30MM
NOTE: FOR NO BATTERY SITUATION 39 34 29 PP1V2_S2R N5 VDD_LDO12 VPUMP K3 PMU_VPUMP MIN_NECK_WIDTH=0.20MM
PP1V8 32 34 39
1 CAP PER PIN N5 N14 MAX_NECK_LENGTH=3 MM

PPBATT_VCC N14 VDD_LDO16 VOLTAGE=4.6V TP_PP1V8_GRAPE
39 34 32 29
1 C8134 1 C8136
A NOSTUFF
CRITICAL
NOSTUFF
CRITICAL CRITICAL CRITICAL 1UF
10%
1UF
10% NET_SPACING_TYPE=CRYSTAL 36 PMU_XTAL N1 XTAL1
1 C8137
0.01UF SYNC_MASTER=MADHAVI SYNC_DATE=12/06/2011 A
XTAL
1 C8174 1 C8173 1 C8170 1 C8171 2 6.3V 2 6.3V

CERM
CERM 402 36 PMU_EXTAL P1 XTAL2 10%
10V PAGE TITLE
10UF 10UF 10UF 10UF C8138 C8140 C8139 C8141 PMU: ADRIANA PAGE 1
402 NET_SPACING_TYPE=CRYSTAL
2 X5R-CERM 1 1 1 1
20% 20% 20% 20% CRITICAL 0201
6.3V 6.3V 6.3V 6.3V 1UF 1UF 1UF 1UF
2 CERM-X5R
0402-1
2 CERM-X5R
0402-1
2 CERM-X5R
0402-1
2 CERM-X5R
0402-1
Y8138 20% 10% 10% 10% DRAWING NUMBER SIZE
32.768K-20PPM-12.5PF 2 6.3V 2 6.3V 2 6.3V 2 6.3V
1 2 TABLE_ALT_HEAD
X5R
0201
CERM
402
CERM
402
CERM
402
39 BATT_POS_RC CRITICAL CRITICAL PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: REVISION
MIN_LINE_WIDTH=0.30MM PART NUMBER
1 MIN_NECK_WIDTH=0.20MM C8142 1 2012-1 1 C8143 R
A.0.0
R8100 NET_SPACING_TYPE=PWR 18PF 18PF 128S0339 128S0279 ?
TABLE_ALT_ITEM
0.5
VOLTAGE=4.6V 5% 5% C8165,C8166 RDAR://PROBLEM/8967213 NOTICE OF PROPRIETARY PROPERTY: BRANCH
25V 25V
1% NP0-C0G 2 2 NP0-C0G TABLE_ALT_ITEM

1/16W 201 201 197S0399 197S0392 ? Y8138 RDAR://PROBLEM/9936684
MF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
402 2
81 OF 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
(TEMP5 - TOP SIDE NEAR NAND) BOARD_TEMP5_P 30 37
(TEMP6 BOTTOM SIDE NEAR BRIDGE FLEX) BOARD_TEMP6_P 30 37
1
CRITICAL 1 1
R8281 R8203
CRITICAL 1 C8204 200K
10KOHM-1%-0.31MA R8282 0.1UF 1%
10% 1/20W
0201 MF
C8281 1
10KOHM-1%-0.31MA 1 C8292 1 C8206 1 C8207 6.3V
2 X5R 2 201
100PF
2 0201 0.01UF 0.01UF 0.01UF OMIT_TABLE 201
5% C8282 1
2 10% 10% 10%
6.3V
CERM 2
100PF
5% SENSOR LOCATIONS TBD
6.3V
2 X5R
6.3V
2 X5R
6.3V
2 X5R U8100
01005 6.3V 2
CERM LOCATION DESCRIPTIONS ARE FROM J2
01005 01005 01005 D2018 PLACEMENT NOTE: PLACE NEAR PIN K4
01005 FCBGA
D (INTERNAL PULL-DOWN)
NC_FW_ZENER_PWR M19 FW_DPHP_DET
SYM 1 OF 3
IREF M7 PMU_IREF
1 C8212 1 C8209 1 C8210 D
NO_TEST=TRUE NET_SPACING_TYPE=ANLG 0.1UF 1UF 0.22UF
GPIO_BTN_HOME_L C3 P7 PMU_VREF 10% 10% 20%
DIGITAL
BUTTON1 VREF PLACEMENT NOTE: PLACE NEAR PIN K24
REFERENCES
XW8282 23 5 IN
2 6.3V 2 6.3V 2 6.3V
INPUT
37 BOARD_TEMP6_N
1 2 20 5 GPIO_BTN_ONOFF_L D3 BUTTON2 VDD_REF K18 PMU_VDD_REF X5R CERM X5R
IN NET_SPACING_TYPE=ANLG 201 402 0201
SM GPIO_BTN_SRL_L E3 BUTTON3 VDD_REF_A M15
NOSTUFF 20 5 IN
XW8281 25 IN PMU_E75_ACC_DET_L C1 ACC_DET VDD_RTC N10 PMU_VDD_RTC
37 BOARD_TEMP5_N
1 2
PLACE XW AND CAP ADC_REF M10 PMU_ADC_REF
SM
NOSTUFF CLOSE TO PMU R8299 PMU_ACC_ID M8 ACC_ID
6.34K2 MIN_NECK_WIDTH=0.1MM
ANALOG
PMU_USB_BRICKID 1 PMU_USB_BRICKID_R M21 D5 PMU_GPIO_CLK_32K_GRAPE
INPUT
PLACE XW AND CAP 10 IN BRICK_ID GPIO1 OUT 17 36 USED BY Z2 1 C8214
CLOSE TO PMU 1%
1/20W
ADC_IN7 L4 ADC_IN7 GPIO2 C5 PMU_GPIO_CLK_32K_WLAN OUT 14 36 (1.8_S2R PUSH-PULL) 1000PF
L5 C6 10%
MF ADC_IN31 GPIO3 PMU_GPIO_BT_REG_ON OUT 14 (1.8_S2R;NO PD REQ’D PER BB TEAM) 6.3V
2 X5R-CERM
201
GPIO4 C7 PMU_GPIO_WLAN_REG_ON (1.8_S2R;NO PD REQ’D PER BB TEAM) 01005
OUT 14
(TEMP1 - BOTTOM SIDE NEAR H5G) BOARD_TEMP1 L19 TDEV1 GPIO5 C8 PMU_GPIO_BB_PMU_RST_L
37 32 OUT 26
(TEMP2 - BOTTOM SIDE NEAR PMU) BOARD_TEMP2 K15 TDEV2 GPIO6 C9 UART5_BATTERY_TRXD (2.5V ALWAYS ON PU IN BMU)
1 37 32 IN 5 28
(TEMP3 - BOTTOM SIDE NEAR I/O FLEX CONN) 37 BOARD_TEMP3_P K14 TDEV3 GPIO7 C10 PMU_GPIO_BT_HOST_WAKE 14 (INTERNAL PD)
1 IN
CRITICAL
TEMPERATURE
(TEMP4 - BOTTOM SIDE NEAR WIFI) 37 BOARD_TEMP4_P M13 C11 PMU_GPIO_WLAN_HOST_WAKE
GPIO
R8218 CRITICAL 1
TDEV4 GPIO8 IN 14 (INTERNAL PD)
30 BOARD_TEMP5_P M5 C12 PMU_GPIO_BB_HOST_WAKE
10KOHM-1%-0.31MA R8222 CRITICAL
0201 37 TDEV5 GPIO9 IN 26 (INTERNAL PD; CAN’T BE USED FOR 32K CLK OUTPUT)
37 30 BOARD_TEMP6_P M4 TDEV6 GPIO10 C13 PMU_GPIO_CODEC_HS_INT_L 18 (INTERNAL PU TO PP1V8_S2R)
C8215 1
0201 10KOHM-1%-0.31MA R8216 37 BOARD_TEMP7_P L3 TDEV7 GPIO11 C14 PMU_GPIO_BBUSBTODOCK_EN
IN
2 0201 1 2 OUT 25
100PF C8221 1 10KOHM-1%-0.31MA
CRITICAL 37 BOARD_TEMP8_P M3 TDEV8 GPIO12 C15 PMU_GPIO_TS_INT IN 5 25 NEED RADAR TO STOP GENERATING 32K CLOCK
5% 2
6.3V 2
CERM
100PF C8217 1 0201
R8280 28 IN BATTERY_NTC L21 TBAT GPIO13 C16 PMU_GPIO_HALL2_IRQ IN 23
5%
01005 6.3V 100PF 2
C8223 1 RESISTOR FOR TEMP CALIBRATION PMU_TCAL M22 TCAL GPIO14 C17 PMU_GPIO_CODEC_RST_L
CERM 2 5% 10KOHM-1%-0.31MA
NET_SPACING_TYPE=ANLG OUT 18
01005 6.3V 100PF CRITICAL GPIO15 C18 PMU_GPIO_HALL_IRQ BB_VBUS_DET STUFFING OPTION
CERM 2 5% 2 IN 22
01005 6.3V R8219 E10 KEEPACT C19 SELECTING GPIO OPTION BY DEFAULT
GPIO_PMU_KEEPACT NC_PMU_GPIO16 NO_TEST=TRUE
WDOG
CERM 2 XW8203 C8220 1
3.92K
5 IN GPIO16 REMOVE STUFFING RES AND WIRE DIRECTLY FOR PRODUCTION
01005 37 (INTERNAL PULL-DOWN) H3 SHDN C20
XW8202
BOARD_TEMP4_N
1 2 100PF
5%
0.1%
402
32 IN PMU_SHDWN
GPIO17 PMU_GPIO_BB_VBUS_DET 30 R8297
SM
NOSTUFF 6.3V 1/16W 0.00 2
37 BOARD_TEMP3_N
1 2 CERM 2
1 MF 30 PMU_GPIO_BB_VBUS_DET 1
PMU_RESET_IN (INTERNAL PULL-DOWN) G4 RESET_IN C21
C XW8201 SM 01005 25 IN AMUX_A0 NC
C
RESET
NOSTUFF PLACE XW AND CAP F4 RESET* C22
0%
37 BOARD_TEMP8_N
1 2 39 26 25 4 OUT RST_AP_L AMUX_A1 NC 1/32W
CLOSE TO PMU MF
XW8200 SM PLACE XW AND CAP (PULLUP INSIDE H5G)
GPIO_PMU_IRQ_L H4 IRQ* AMUX_A2 E17 01005
NOSTUFF 5 OUT NC
ANALOG MUX
37 BOARD_TEMP7_N
1 2 BB_VBUS_DET OUT 26
PLACE XW AND CAP CLOSE TO PMU AMUX_A3 E14
PLACE XW AND CAP SM NC
NOSTUFF CLOSE TO PMU I2C0_SCL_1V8 E7 SCL AMUX_AY C23 NOSTUFF
36 25 19 5 IN NC
CLOSE TO PMU
I2C0_SDA_1V8 E9 SDA AMUX_B0 D21 R8296
I2C & DWI

36 25 19 5 BI NC 0.00 2
AMUX_B1 D22 NOSTUFF VLCM3 1
NC CRITICAL
30
DWI_AP_CLK (INTERNAL PULL-DOWN) A1 DWI_CK AMUX_B2 D19 (NOTE: 2MHZ) 0%

36 5 IN NC L8229 1/32W
DWI NAMING RELATIVE TO AP DWI_AP_DO (INTERNAL PULL-DOWN) B1 DWI_DI E13
36 5 IN AMUX_B3 NC 2.2UH-1.05A-0.195OHM NOSTUFF MF
01005
DWI_AP_DI C2 DWI_DO AMUX_BY D23 CRITICAL
36 5 OUT NC 1 2
CRITICAL CRITICAL MAKE_BASE=TRUE
VLS201612E-SM
MIN_LINE_WIDTH=0.4 MM D8230
L8225 D8228 WLED_LX_A N21 VDD_LCM_SW N19 PPVCC_MAIN 15 25 29 34 39
VOLTAGE=6.0V
NET_SPACING_TYPE=PWR PMEG2005AEL
4.7UH-3.2A PMEG4010BEA
DIDT=TRUE
P21 WLED_LXA VDD_BOOST_LCM
39 P19 PP6V0_LCM_HI MIN_NECK_WIDTH=0.2MM
DIDT=TRUE
A K
34 30 =PPVCC_MAIN_LED 1 2 (PPLED_OUT_A) K16 VOUT_WLED_A BOOST_LCM_LX
39 P20 LCM_LX MAX_NECK_LENGTH=3 MM
A K
R8227 N13 PP6V0_LCM_VBOOST SOD882
LCM/GRAPE
PIME051E-SM 37 LED_IO1_A_R K5 WLED1_A VDD_LCM
39
CRITICAL DCR=106MOHM MAX SOD-323 1.00 MAKE_BASE=TRUE Q8202
C8226 1 37 15 OUT LED_IO_1_A 1 2 37 LED_IO2_A_R K6 WLED2_A LCM2_EN F3 TP_LCM2_EN (INTERNAL PULLDOWN; TE ENABLE) VOLTAGE=6.0V CSD58874W1015
10UF 1% 37 LED_IO3_A_R K7 WLED3_A LCM_FB M20 MIN_LINE_WIDTH=0.4MM
BGA A1
20%
10V
X5R 2
R8231 1/20W
MF 37 LED_IO4_A_R K8 WLED4_A VLCM1 P13 NC_VLCM1 NET_SPACING_TYPE=PWR
D
B1
0603-1 1.00 201 NO_TEST=TRUE
LED_IO_2_A 1 2 LED_IO5_A_R M9 WLED5_A VLCM2 P12 NC_VLCM2
LED BACKLIGHT
37 15 OUT 37
NO_TEST=TRUE
C1
1% 37 LED_IO6_A_R K9 WLED6_A VLCM3 N12 VLCM3 30 A2 G
39 34 30 PPLED_OUT_A 1/20W
R8232 NOSTUFF NOSTUFF NOSTUFF NOSTUFF
MF
LED_IO_3_A
201
1
1.00
2 N23 CPUA_EN M23 CPU0_SWITCH
C8236 1 1 C8237 1 C8239 1 C8238 B2 S
1 C8232 1 C8233 1 C8234 1 C8235
37 15 OUT
4
2.2UF 10UF 1UF 1UF C2
P23 WLED_LXB CPUA_SW_G J5 CPU0_SW_G 20% 20% 10% 10%
4.7UF 4.7UF 4.7UF 4.7UF 1% DIDT=TRUE
10V 2 25V 2 10V 2 10V
10%
35V
10%
35V
10%
35V
10%
35V
R8235 1/20W
MF K17 VOUT_WLED_B CPUA_SW_S J4 CPU0_SW_S 30
X5R-CERM 2
402
X5R-CERM
0603
X5R
402
X5R
402
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 1.00 201
LED_IO_4_A LED_IO1_B_R K10
0603 0603 0603 0603 37 15 OUT
1 2 37 WLED1_B Q8200
1% 37 LED_IO2_B_R M11 WLED2_B CPUB_EN L22 CPU1_SWITCH 4 CSD58874W1015
1/20W
MF R8239 37 LED_IO3_B_R K11 WLED3_B CPUB_SW_G J3 CPU1_SW_G
BGA A1
B B
29 39
201 1.00 D
37 15 OUT LED_IO_5_A 1 2 37 LED_IO4_B_R K12 WLED4_B CPUB_SW_S K4 CPU1_SW_S 30
B1 PP1V1_CPU0_FET
1% 37 LED_IO5_B_R M12 WLED5_B R8292 C1
R8240 1/20W
K13
0 CPU0_SW_G_R
MF 37 LED_IO6_B_R WLED6_B DPHP E4 NC_PMU_DP_HPD 1 2 A2 G
1.00 201 NO_TEST=TRUE
37 15 OUT LED_IO_6_A 1 2 5%
B2 S
NOSTUFF NOSTUFF 1/20W
1%
1/20W I2C ADDRESS: 0111100X (0X78) 1
R8290 1 C8290
MF
201 C2
MF
201 1M 0.1UF
WLED_LX_B 5% 10%
1/20W
MF 2 16V
X5R-CERM PP1V1_CPU0
CRITICAL CRITICAL MIN_NECK_WIDTH=0.25 MM 0201
39 34
(PPLED_OUT_B) 2 201 Q8201

L8255 D8258 XW8290
CSD58874W1015
4.7UH-3.2A PMEG4010BEA 30 CPU0_SW_S 1 2
BGA PP1V1_CPU1_FET
SM A1 29
34 30 =PPVCC_MAIN_LED 1 2
A K R8257
NOSTUFF D
B1
39
PIME051E-SM
CRITICAL DCR=106MOHM MAX SOD-323 LED_IO_1_B 1
1.00
2 R8293 C1
C8256 1 37 15 OUT
1
0 2 CPU1_SW_G_R A2 G
10UF 1%
20%
10V 2
R8261 1/20W
MF 5%
B2 S
1.00 201 1/20W
X5R 37 15 LED_IO_2_B 1 2 NOSTUFF NOSTUFF MF
0603-1 OUT 1 C2
1%
PPLED_OUT_A 30 34 39 R8291 1 C8291 201
1/20W
R8262 1M 0.1UF Q8203
PPLED_OUT_B MF
C8266 1 5% 10%
39 34 30
201 1.00 1/20W 2 16V
CSD58874W1015
CRITICAL CRITICAL CRITICAL CRITICAL 37 15 OUT LED_IO_3_B 1 2
C8201 1 0.01UF PLACEMENT_NOTE=PLACE NEAR U8100.K16
MF X5R-CERM BGA
A1
10% 0201
1 C8262 1 C8263 1 C8264 1 C8265 1% 0.01UF 50V 2 201 D
4.7UF 4.7UF 4.7UF 4.7UF R8265 1/20W 10% X7R 2
PLACEMENT_NOTE=PLACE NEAR U8100.K16 B1
MF 50V 402
10% 10% 10% 10% 1.00 201 X7R 2 C1
2 35V
X5R-CERM 2 35V
X5R-CERM 2 35V
X5R-CERM
35V
2 X5R-CERM 37 15 OUT LED_IO_4_B 1 2 402 A2
PP1V1_CPU1 G
0603 0603 0603 0603 1% 39 34
1/20W
MF R8269 PPLED_OUT_B
B2 S
201 1.00 30 34 39
XW8291
37 15 OUT LED_IO_5_B 1 2
C8267 1 30 CPU1_SW_S 1 2
C2
1%
C8251 1 0.01UF PLACEMENT_NOTE=PLACE NEAR U8100.K17 MIN_LINE_WIDTH=0.4MM SM
NOSTUFF
A R8270 1/20W 10%
A
MF 0.01UF 50V MAX_NECK_LENGTH=3 MM
1.00 201 10% X7R 2
PLACEMENT_NOTE=PLACE NEAR U8100.K17
37 15 OUT LED_IO_6_B 1 2 50V 2 402 SYNC_MASTER=MADHAVI SYNC_DATE=12/06/2011
X7R PAGE TITLE
1%
1/20W
MF
201
402
PMU: ADRIANA PAGE 2
DRAWING NUMBER SIZE
TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: REVISION
PART NUMBER
TABLE_ALT_ITEM
R
A.0.0
107S0150 107S0208 ? RDAR://PROBLEM/8380367 NOTICE OF PROPRIETARY PROPERTY: BRANCH
R8216,R8218,R8222,R8280,R8281,R8282 THE INFORMATION CONTAINED HEREIN IS THE
82 OF 154
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8 7 6 5 4 3 2 1
D D
OMIT_TABLE
U8100
D2018
FCBGA
SYM 3 OF 3
C4 A8
D20 VSS/VSS_BUCK0A0B B8
F6 A12
F7 VSS/VSS_BUCK0A2 B12
F8 A4
F9 VSS/VSS_BUCK0B4 B4
F10 F1
F11 VSS/VSS_BUCK0C3 F2 ADD A VIA PER PIN FOR ALL VSS_* AND VSSA_* PINS
F12
F13 A16
F14 VSS/VSS_BUCK2_01 B16
F15 A20
C F16
F17
VSS/VSS_BUCK25 B20
C
G3 VSS/VSSA_BUCK0A E12
G5 VSS/VSSA_BUCK0B E8
G7 VSS/VSSA_BUCK0C G6
G8 VSS/VSSA_BUCK2 E16
G9 VSS/VSSA_BUCK3 H6
G10 VSS/VSSA_BUCK4 E5
G11 VSS VSS/VSSA_BUCK5 F18
G12
G13 VSS_WLED N22
G14 VSS_WLED P22
G15 VSS_LCM N20
G16
G17 J6
G18 J7
H7 J8
H8 J9
H9 J10
H10 J11
H11 J12
H12 VSS J13
H13 J14
H14 J15
H15 J16
H16 J17
H17 J18
B H18 B
A SYNC_MASTER=MADHAVI SYNC_DATE=12/06/2011 A
PAGE TITLE
PMU: ADRIANA PAGE 3

DRAWING NUMBER SIZE

REVISION
R
A.0.0
83 OF 154
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
DEBUG RESET ACCESS

34 5 =PP1V8_S2R_MISC 39 34 29 PPBATT_VCC
NOSTUFF
1
R9000 NOSTUFF PP1V8
300 1 39 34 32 29
5% R9002
1/20W 1.5K NOSTUFF
MF 1%
2 201 1/20W 1
R9001
MF
2 201 300
5%
5 GPIO_FORCE_DFU 1/20W
OUT MF
PWR_ON_LED 2 201
30 OUT PMU_SHDWN
A NOSTUFF
LED9000
RED-50MCD-20MA
0603
C K
C
SOCHOT TO PMU TDEV1/TDEV2

39 34 32 29 PP1V8
R9020
470
B
1
R9010
100K
5%
1
R9011
100K
SOCHOT1_TDEV1 1
1%
2 BOARD_TEMP1 OUT 30 37
B
1/20W 5% CRITICAL 3 1/32W
1/20W MF
MF 01005 1
2 201
MF R9021
2 201 D 10K
1%
Q9020 1/32W
MF
SOCHOT1 1 G DMN26D0UFB4
S DFN 2 01005
SYM_VER_1
CRITICAL
3
2
D
Q9010
SOCHOT1_L 1 G DMN26D0UFB4
7 IN
S
R9030
DFN
SOCHOT1_TDEV2 1
470 2 BOARD_TEMP2
SYM_VER_1 OUT 30 37
1%
CRITICAL 3 1/32W
2 MF
01005 1
D
R9031
10K
1%
Q9030 1/32W
1 G MF
DMN26D0UFB4 2 01005
S DFN
SYM_VER_1
A SYNC_MASTER=MLB SYNC_DATE=11/09/2011 A
PAGE TITLE
DEBUG/MISC.
DRAWING NUMBER SIZE

REVISION
R
A.0.0
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D D
PLATED THROUGH HOLES

DRILL SIZE: 1.1MM X 0.4MM
PLATING SIZE: 1.4MM X 0.7MM
FID4200 SL4210
TH-NSP
FID 1
0P5SM1P0SQ-NSP
1 SL-1.1X0.4-1.4X0.7
FID4201
FID SL4201
0P5SM1P0SQ-NSP TH-NSP
1 1
FID4202 SL-1.1X0.4-1.4X0.7
FID
0P5SM1P0SQ-NSP
1
FID4203 SL4212
C FID
0P5SM1P0SQ-NSP
TH-NSP
1 C
1 SL-1.1X0.4-1.4X0.7
FID4204
FID SL4213
0P5SM1P0SQ-NSP TH-NSP
1 1
FID4205 SL-1.1X0.4-1.4X0.7
FID
0P5SM1P0SQ-NSP
1
SL4204 SL4214
TH-NSP
TH-NSP 1
1
SL-1.1X0.4-1.4X0.7
SL-1.1X0.4-1.4X0.7
SL4205 SL4215
TH-NSP
TH-NSP 1
1
SL-1.1X0.4-1.4X0.7
SL-1.1X0.4-1.4X0.7
SL4206 SL4216
TH-NSP
TH-NSP 1
1
SL-1.1X0.4-1.4X0.7
SL-1.1X0.4-1.4X0.7
B B
PAGE TITLE
TEST/HOLES/FIDUCUALS
DRAWING NUMBER SIZE

REVISION
R
A.0.0
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POWER CONNECTIONS
BUCK0A BUCK5 CHARGER MAIN
39 30 PP1V1_CPU0 =PPVDD_CPU0_H5 9
39 29 PP3V3_OUT =PP3V3_NAND 13
LDO9
MAKE_BASE=TRUE
MAKE_BASE=TRUE
VOLTAGE=1.1V VOLTAGE=3.3V =PP3V3_USB_H5 4
39 30 29 25 15 PPVCC_MAIN =PPVCC_MAIN_AUDIO 18 19
D
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=4.7V =PPVCC_MAIN_LED
D MIN_NECK_WIDTH=0.2 MM
=PP3V3_LCD 15
39 29 PP3V0_IO
MAKE_BASE=TRUE
VOLTAGE=3.0V
=PP3V0_VDDIO30_H5 9
PPVCC_MAIN_CPU0
30
29
MIN_NECK_WIDTH=0.2 MM PPVCC_MAIN_CPU1 29
MAX_NECK_LENGTH=3 MM PPVCC_MAIN_SOC
BUCK0B
29
BACKLIGHT BOOST
39 30 PP1V1_CPU1 =PPVDD_CPU1_H5 9
LDO11
MAKE_BASE=TRUE
VOLTAGE=1.1V 39 30 PPLED_OUT_A =PPLED_REG_A 15
MIN_LINE_WIDTH=0.6 MM MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM VOLTAGE=20.4V
NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.6 MM
MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2 MM
39 29 PP2V8_CAM
MAKE_BASE=TRUE
=PP2V8_CAM 21 BATTERY
PPLED_OUT_B =PPLED_REG_B VOLTAGE=2.8V
BUCK0C
39 30 15
MAKE_BASE=TRUE
VOLTAGE=20.4V MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM NET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.2 MM MAX_NECK_LENGTH=3 MM
NET_SPACING_TYPE=PWR 39 32 29 PPBATT_VCC =BATT_POS_CONN 28
39 29 PP1V1_CPUB =PPVDD_CPUB_H5 9 MAX_NECK_LENGTH=3 MM MAKE_BASE=TRUE
VOLTAGE=4.2V
MAKE_BASE=TRUE
VOLTAGE=1.1V MIN_LINE_WIDTH=0.6 MM =BATT_POS_F_3G 26 CELLULAR RADIO
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM NET_SPACING_TYPE=PWR
NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3 MM =BATT_VCC 27
WLAN
LDO1 LDO12
39 29 PP3V0_GRAPE =PP3V0_GRAPE 16 17 USB POWER INPUT
BUCK2
MAKE_BASE=TRUE
VOLTAGE=3.0V =PP3V0_GRAPE_MARIO1 16 39 29 PP1V0 =PP1V0_MIPI_H5 7
MIN_LINE_WIDTH=0.6 MM MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V
39 29 PP1V2_SOC =PPVDD_SOC_H5 9
NET_SPACING_TYPE=PWR =PP3V0_GRAPE_Z1 17
MIN_LINE_WIDTH=0.6 MM =PP1V0_DP_PAD_DVDD_H5 7
MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.2 MM PPVBUS_USB_EMI PPVBUS_USB_DCIN
C C
MAKE_BASE=TRUE 39 23 29
VOLTAGE=1.2V =PP3V0_GRAPE_Z2 17 NET_SPACING_TYPE=PWR =PP1V0_EDP_PAD_DVDD_H5 7 MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM MAX_NECK_LENGTH=3 MM VOLTAGE=6V
MIN_NECK_WIDTH=0.2 MM =PP1V0_USB_H5 4
NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.15 MM
MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR
=PP1V0_HSIC_H5 4 MAX_NECK_LENGTH=3 MM
LDO2 =PP1V0_MIPI_PLL_H5 7
PP1V7_VA_VCP =PP1V7_VA_VCP
BUCK3
39 29 19
MAKE_BASE=TRUE
VOLTAGE=1.7V
18 19
LDO16
MAX_NECK_LENGTH=3 MM PP1V1_SRAM =PPVDD_SRAM_H5
39 29 PP1V8_S2R =PP1V8_S2R_MISC 5 32
39 29
MAKE_BASE=TRUE
9
MAKE_BASE=TRUE
VOLTAGE=1.8V VOLTAGE=1.1V
MIN_LINE_WIDTH=0.6 MM MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM VDDIO_WLAN_BT_1V8 14 MIN_NECK_WIDTH=0.2 MM
MAX_NECK_LENGTH=3 MM =PP1V8_S2R_USBMUX 25 LDO3 (NO LONGER NEEDED) NET_SPACING_TYPE=PWR
=PP1V8_S2R_DDR 11 12
39 29 PP3V2_S2R_USBMUX =PP3V2_S2R_USBMUX 25
MAKE_BASE=TRUE
VOLTAGE=3.0V
BUCK4 39 29 PP1V8_ALWAYS =PP1V8_ALWAYS 5
LDO4 MAKE_BASE=TRUE
VOLTAGE=1.8V
39 29 PP1V2_S2R =PP1V2_S2R_H5 8
MAKE_BASE=TRUE
VOLTAGE=1.2V
B
=PP1V2_S2R_DDR 11 12 39 29 PP3V0_SENSOR
MAKE_BASE=TRUE
VOLTAGE=3.0V
=PP3V0_SENSOR 21
B
BUCK3_SW
32 29
39
PP1V8
CPU1V8_SW
MAKE_BASE=TRUE
=PP1V8_SENSOR 21 LDO6
VOLTAGE=1.8V =PP1V8_AUDIO 18
MIN_NECK_WIDTH=0.1MM =PP1V8_VDDIO18_H5 4 6 7 9
39 29 PP3V3_ACC =PP3V3_ACC 25
NET_SPACING_TYPE=PWR MAKE_BASE=TRUE
MAX_NECK_LENGTH=3MM =PP1V8_H5 4 5 7 10
VOLTAGE=3.3V
=PP1V8_MIPI_H5 7
=PP1V8_DP_H5 7
=PP1V8_EDP_H5 7
=PP1V8_NAND_H5 6 9
=PP1V8_NAND 13
=PP1V8_PLL_H5 4
=PP1V8_MISC
LDO7
16
29 PP3V0_S2R_TRISTAR =PP3V0_S2R_TRISTAR 25
MAKE_BASE=TRUE
VOLTAGE=3.0V
A
BUCK4_SW
SYNC_MASTER=N/A
PAGE TITLE
SYNC_DATE=N/A A
CPU1V2_SW
PP1V2 =PP1V2_VDDQ_DDR
POWER ALIASES
39 29
MAKE_BASE=TRUE
VOLTAGE=1.2V
=PP1V2_VDDIOD_H5
11 12
8 9 LDO8 Apple Inc.

DRAWING NUMBER
051-9385
SIZE
D
MIN_NECK_WIDTH=0.1 MM =PP1V2_HSIC_H5 4
REVISION
MAX_NECK_LENGTH=3 MM R
A.0.0
39 29 PP3V0_S2R_HALL I927
=PP3V0_S2R_HALL 21 23 NOTICE OF PROPRIETARY PROPERTY: BRANCH
MAKE_BASE=TRUE
VOLTAGE=3.0V THE INFORMATION CONTAINED HEREIN IS THE
MIN_LINE_WIDTH=0.6 MM PROPRIETARY PROPERTY OF APPLE INC.
MIN_NECK_WIDTH=0.2 MM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
MAX_NECK_LENGTH=3 MM I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
121 OF 154
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MLB CONSTRAINTS TCF VERSION (USING SPACING RULE)
TABLE_SPACING_RULE_HEAD
TABLE_BOARD_INFO
BOARD LAYERS BOARD AREAS BOARD UNITS ALLEGRO SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
(MIL or MM) VERSION
TCF_VERSION * 0.104 MM ?
TABLE_SPACING_RULE_ITEM
0.104 - 11/30/2011
NOTES:
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,BOTTOM NO_TYPE,BGA,BGA06-06,BGA_P4 MM 16.2
TCF_VERSION NC_UART5_TXD ASSIGNING RULE TO NC NET 0.075 MM ~ 3 MIL

PHYSICAL CONSTRAINTS
I1 5
0.089 MM ~ 3.5 MIL

PHYSICAL_RULE_SET LAYER ALLOW ROUTE
ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
SPACING CONSTRAINTS 0.102 MM ~ 4 MIL
DEFAULT * Y =45_OHM_SE =45_OHM_SE 3.0 MM 0 MM 0 MM
D STANDARD * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT

DEFAULT/BGA SPACING RULES

0.114 MM ~ 4.5 MIL D
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
DEFAULT * 0.100 MM ?
0.125 MM ~ 5 MIL
SINGLE-ENDED PHYSICAL RULES
45 OHMS 0.140 MM ~ 5.5 MIL
STANDARD * =DEFAULT ?
TABLE_PHYSICAL_RULE_HEAD TABLE_SPACING_RULE_ITEM
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP BGA_SPA * =DEFAULT ?
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_ITEM
0.15 MM ~ 6 MIL
45_OHM_SE TOP,BOTTOM Y 0.105 MM 0.055 MM 3.0 MM BGA_P4_SPA * 0.200 MM ?
45_OHM_SE ISL2,ISL9 Y 0.055 MM 0.055 MM 3.0 MM

0.18 MM ~ 7 MIL
0.2 MM ~ 8 MIL

TABLE_PHYSICAL_RULE_ITEM REGULAR SPACING RULES
TABLE_PHYSICAL_RULE_ITEM SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
0.25 MM ~ 10 MIL
45_OHM_SE ISL5 Y 0.072 MM 0.055 MM 3.0 MM TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM 1:1_SPACING * 0.050 MM ? 0.3 MM ~ 12 MIL

45_OHM_SE ISL6 Y 0.059 MM 0.055 MM 3.0 MM TABLE_SPACING_RULE_ITEM
0P08_SPACING * 0.080 MM ?
TABLE_SPACING_RULE_ITEM 0.33 MM ~ 13 MIL
1.5:1_SPACING * 0.075 MM ?
90 OHMS DIFFERENTIAL PAIR PHYSICAL RULES TABLE_SPACING_RULE_ITEM
0.4 MM ~ 16 MIL
TABLE_PHYSICAL_RULE_HEAD 2:1_SPACING * 0.100 MM ?
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER? TABLE_SPACING_RULE_ITEM
90_OHM_DIFF TOP,BOTTOM Y 0.090 MM 0.090 MM =STANDARD 0.170 MM 0.170 MM

TABLE_PHYSICAL_RULE_ITEM 2.5:1_SPACING * 0.125 MM ?
1.0 MM = 39.37 MIL
TABLE_PHYSICAL_RULE_ITEM 3:1_SPACING * 0.150 MM ?
90_OHM_DIFF ISL2,ISL9 Y 0.062 MM 0.062 MM =STANDARD 0.190 MM 0.190 MM TABLE_SPACING_RULE_ITEM


C 90_OHM_DIFF ISL5,ISL6 Y 0.052 MM 0.052 MM =STANDARD 0.105 MM 0.105 MM

TABLE_PHYSICAL_RULE_ITEM 0P5MM_SPACING
0P64MM_SPACING
*
*
0.5 MM
0.64 MM
?
?
C
DDR 45 OHMS SINGLE-ENDED PHYSICAL RULES 0P2_SPACING * 0.20 MM ?

ON LAYER?
DDR_45_OHM_SE Y 0.105 MM 0.105 MM

TOP,BOTTOM 3.0 MM
POWER/GND SPACING RULES
DDR_45_OHM_SE ISL2 Y 0.055 MM 0.055 MM 3.0 MM TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
DDR_45_OHM_SE ISL3 Y 0.065 MM 0.065 MM 3.0 MM TABLE_SPACING_RULE_ITEM
PWR_P1SPACING * 0.1 MM
DDR_45_OHM_SE ISL4 Y 0.053 MM 0.053 MM 3.0 MM TABLE_SPACING_RULE_ITEM
GND_P1SPACING * 0.1 MM
DDR_45_OHM_SE ISL5,ISL6 Y 0.072 MM 0.072 MM 3.0 MM TABLE_SPACING_RULE_ITEM
SWITCHNODE * 0.2 MM
DDR_45_OHM_SE * N 0.055 MM 0.055 MM 3.0 MM
DDR 90 OHMS DIFFERENTIAL PAIR PHYSICAL RULES TABLE_PHYSICAL_RULE_HEAD
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM POWER
DDR_90_OHM_DIFF TOP,BOTTOM Y 0.090 MM 0.090 MM =STANDARD 0.170 MM 0.170 MM TABLE_PHYSICAL_RULE_HEAD
ON LAYER?
DDR_90_OHM_DIFF ISL2 Y 0.062 MM 0.062 MM =STANDARD 0.190 MM 0.190 MM TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM PWR * Y 0.6MM 0.20 MM 3.0 MM

TABLE_PHYSICAL_RULE_ITEM GND_PH * Y 0.6MM 0.075 MM 3.0 MM

TABLE_PHYSICAL_RULE_ITEM PWR_PMU * Y 0.6MM 0.20 MM 3.0 MM

DDR_90_OHM_DIFF ISL5,ISL6 Y 0.066 MM 0.066 MM =STANDARD 0.180 MM 0.180 MM
B B
DDR_90_OHM_DIFF * N 0.056 MM 0.056 MM =STANDARD 0.180 MM 0.180 MM
WIFI PHYSICAL RULES TABLE_PHYSICAL_RULE_HEAD

MISC
TABLE_SPACING_ASSIGNMENT_HEAD
ON LAYER? NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

WIFI_50S TOP,BOTTOM Y 0.245 MM 0.2 MM

TABLE_SPACING_ASSIGNMENT_ITEM
=STANDARD * * BGA BGA_SPA

WIFI_50S N =STANDARD =STANDARD

* =STANDARD CLK * BGA BGA_SPA

WIFI_PWR100 Y 0.10 MM 0.050 MM

* =STANDARD GND * * GND_P1SPACING

WIFI_PWR1000 Y 1.00 MM 0.100 MM

* =STANDARD SWITCHNODE * * SWITCHNODE

ANLG * * 3:1_SPACING
MISC PHYSICAL RULES TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_HEAD * * BGA_P4 BGA_P4_SPA

ON LAYER?
1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.08 MM 0.08 MM

SPEAKER * Y 0.5 MM 0.20 MM 10 MM 0.10 MM 0.10 MM

AUDIO_DIFF * Y 0.1 MM 0.09 MM 10 MM 0.10 MM 0.10 MM

LED * Y 0.1 MM 0.09 MM 10 MM 0.08 MM 0.08 MM

TEMP_SENSE * Y 0.1 MM 0.09 MM 10 MM 0.08 MM 0.08 MM
A SYNC_MASTER=MIKE SYNC_DATE=11/30/2011 A
PAGE TITLE
BGA AREA PHYSICAL RULES
TABLE_PHYSICAL_ASSIGNMENT_HEAD
CONSTRAINTS: MLB RULES
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET DRAWING NUMBER SIZE
TABLE_PHYSICAL_ASSIGNMENT_ITEM

* BGA BGA_PHY REVISION
R
A.0.0
NOTICE OF PROPRIETARY PROPERTY:
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP BRANCH
ON LAYER?
TABLE_PHYSICAL_RULE_ITEM THE INFORMATION CONTAINED HEREIN IS THE
BGA_PHY * Y 0.060 MM 0.060 MM =STANDARD 0.076 MM 0.075 MM PROPRIETARY PROPERTY OF APPLE INC.
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Clock Signal Constraints USB

JTAG
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

USB_90D * 90_OHM_DIFF
CLK_50S * 45_OHM_SE
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

JTAG * * 2:1_SPACING
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

CLK * * 3:1_SPACING USB * * 4:1_SPACING

NET_TYPE
ELECTRICAL_CONSTRAINT_SET
D
PHYSICAL SPACING
D NET_TYPE NET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING I16 JTAG JTAG_AP_TCK 4 25 ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
JTAG JTAG_AP_TMS 4 25
CLK_50S CLK PMU_GPIO_CLK_32K_GRAPE
I15
USB_90D USB USB_AP_P 4 25
I63 17 30
JTAG JTAG_AP_TDI 4
I5
CLK_50S CLK PMU_GPIO_CLK_32K_WLAN

I14
USB_90D USB USB_AP_N 4 25
I162 14 30
JTAG TP_JTAG_AP_TDO 4
I6
I13
USB_90D USB USB_BBMUX_BB_P 25 26
CLK_50S CLK ISP1_CAM_FF_CLK 7 22 RST JTAG_AP_TRST_L 4 10 39
I266
I88 I20
USB_90D USB USB_BBMUX_BB_N 25 26
CLK_50S CLK CONN_ISP1_CAM_FF_CLK 20 22
I267
I89
USB_90D USB USB_TS_BBMUX_P 25
CLK_50S CLK ISP0_CAM_RF_CLK 7 22
I268
I96
USB_90D USB USB_TS_BBMUX_N 25
CLK_50S CLK CONN_ISP0_CAM_RF_CLK 20 22
I269
I94
I270 USB_90D USB USB11_AP_BBMUX_P 4 25
I2S_50S I2S I2S0_CODEC_ASP_MCK 5 36

I2C I271
USB_90D USB USB11_AP_BBMUX_N 4 25
I130
USB_90D USB CONN_E75_DPAIR1_P 24 25
I2S_50S I2S I2S0_CODEC_ASP_MCK_R 5 18 36
I258
I131
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET USB_90D USB CONN_E75_DPAIR1_N 24 25
CLK_50S CLK ISP0_CAM_RF_CLK_R 7
I259
I157 TABLE_PHYSICAL_ASSIGNMENT_ITEM
USB_90D USB CONN_E75_DPAIR2_P 24 25

CLK_50S CLK ISP1_CAM_FF_CLK_R 7 I2C_50S * 45_OHM_SE I260
I158
USB_90D USB CONN_E75_DPAIR2_N 24 25
CLK_50S CLK ISP1_CAM_FF_C 22
I261
I234 TABLE_SPACING_ASSIGNMENT_HEAD
USB_90D USB TS_E75_DPAIR1_P 25

CLK_50S CLK ISP0_CAM_RF_C 22 NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
I263
I235
USB_90D USB TS_E75_DPAIR1_N 25
CLK_50S CLK ISP1_CAM_FF_FILT 22
I262
I256
I2C * * 1.5:1_SPACING USB_90D USB TS_E75_DPAIR2_P 25
CLK_50S CLK ISP0_CAM_RF_FILT 22
I265
I257
I264
USB_90D USB TS_E75_DPAIR2_N 25
NET_TYPE
UART PHYSICAL SPACING
I1 I2C_50S I2C I2C1_SDA_1V8 5 22
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET I2 I2C_50S I2C I2C1_SCL_1V8 5 22
UART_50S * 45_OHM_SE
I3 I2C_50S I2C I2C0_SDA_1V8 5 19 25 30

HSIC
I4
I2C_50S I2C I2C0_SCL_1V8 5 19 25 30
I2C_50S I2C I2C2_SDA_3V0

5 22
I61 NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET I2C_50S I2C I2C2_SCL_3V0 5 22
C C
I62 TABLE_PHYSICAL_ASSIGNMENT_ITEM
I2C_50S I2C ISP0_CAM_RF_I2C_SCL 7 22

HSIC * 45_OHM_SE
I98
UART * * 3:1_SPACING
I99 I2C_50S I2C ISP0_CAM_RF_I2C_SDA 7 22
ISP1_CAM_FF_I2C_SCL
UART UART * 2:1_SPACING I100 I2C_50S I2C 7 22

I101
I2C_50S I2C ISP1_CAM_FF_I2C_SDA 7 22 TABLE_SPACING_ASSIGNMENT_ITEM
I102 I2C_50S I2C CONN_I2C1_SDA_1V8 20 22

HSIC * * 4:1_SPACING
CONN_I2C1_SCL_1V8
NET_TYPE I103 I2C_50S I2C 20 22

HSIC_RDY * * 2:1_SPACING
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING I228 I2C_50S I2C CONN_I2C2_SCL_3V0 20 22
I229 I2C_50S I2C CONN_I2C2_SDA_3V0 20 22
I2C_50S I2C CONN_ISP0_CAM_RF_I2C_SCL 20 22

UART_50S UART UART2_TS_ACC_RXD 5 25
I124
I237
I2C_50S I2C CONN_ISP0_CAM_RF_I2C_SDA 20 22
UART_50S UART UART2_TS_ACC_TXD 5 25
I125
NET_TYPE
I236
I2C_50S I2C CONN_ISP1_CAM_FF_I2C_SCL 20 22
UART_50S UART UART4_WLAN_RXD 5 14
I226
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
I174
I2C_50S I2C CONN_ISP1_CAM_FF_I2C_SDA 20 22
UART_50S UART UART4_WLAN_TXD 5 14
I227
I173
HSIC HSIC HSIC3_BB_DATA 4 26
UART_50S UART UART1_BB_CTS_L 5 26
I191
I175
HSIC HSIC HSIC3_BB_STB 4 26
UART_50S UART UART1_BB_RTS_L 5 26
I194
I176
HSIC HSIC HSIC1_WLAN_DATA
I177 UART_50S UART UART1_BB_TXD 5 25 26 XTAL I193
HSIC HSIC HSIC1_WLAN_STB

4 14
4 14
UART_50S UART UART1_BB_RXD 5 25 26
I192
I178 TABLE_SPACING_ASSIGNMENT_HEAD
HSIC HSIC_RDY GPIO_BB_HSIC_DEV_RDY 5 26

UART_50S UART UART3_BT_CTS_L 5 14 NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
I195
I179
HSIC HSIC_RDY GPIO_BB_HSIC_HOST_RDY 5 26
UART_50S UART UART3_BT_RTS_L 5 14
I196
I182
CRYSTAL * * 5:1_SPACING HSIC HSIC_RDY GPIO_WLAN_HSIC_HOST_RDY 5 14 36
UART_50S UART UART3_BT_RXD 5 14
I197
I181
HSIC HSIC_RDY GPIO_WLAN_HSIC_HOST_RDY 5 14 36
UART_50S UART UART3_BT_TXD 5 14
I198
I180
NET_TYPE HSIC HSIC_RDY GPIO_WLAN_HSIC_DEV_RDY 5 14
I232
UART_50S UART UART6_AP_RXD 5 25
I199

I233 UART_50S UART UART6_AP_TXD 5 25
I92 CRYSTAL XTAL_AP_24M_I 4
I90
CRYSTAL XTAL_AP_24M_O 4
CRYSTAL AP_24M_O
SPI I93
CRYSTAL PMU_XTAL
4
B B
I230 29
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET I231

CRYSTAL PMU_EXTAL 29
SPI_50S * 45_OHM_SE
I2S
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

SPI * * 2:1_SPACING TABLE_PHYSICAL_ASSIGNMENT_ITEM
I2S_50S * 45_OHM_SE
NET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING TABLE_SPACING_ASSIGNMENT_HEAD

I183
SPI_50S SPI SPI3_GRAPE_MISO 5 16
I2S * * 3:1_SPACING
I184 SPI_50S SPI SPI3_GRAPE_MOSI 5 16
I185 SPI_50S SPI SPI3_GRAPE_SCLK 5 16 I2S I2S * 2:1_SPACING

I186 SPI_50S SPI SPI3_GRAPE_CS_L 5 16
I187 SPI_50S SPI SPI2_IPC_MISO

NET_TYPE
I188 SPI_50S SPI SPI2_IPC_MOSI
I189
SPI_50S SPI SPI2_IPC_SCLK
I190 SPI_50S SPI GPIO_BB_HSIC_RESUME 5 26 I140 I2S_50S I2S I2S0_CODEC_ASP_BCLK 5 18
I143 I2S_50S I2S I2S0_CODEC_ASP_LRCK 5 18
I240 SPI_50S SPI SPI1_CODEC_MISO 5 18

I2S_50S I2S I2S0_CODEC_ASP_DIN 5 18
I142
I241 SPI_50S SPI SPI1_CODEC_MOSI 5 18

I2S_50S I2S I2S0_CODEC_ASP_DOUT 5 18
I141
I242
SPI_50S SPI SPI1_CODEC_SCLK 5 18
I2S_50S I2S I2S0_CODEC_ASP_SDOUT 18
I159
I243 SPI_50S SPI SPI1_CODEC_CS_L 5 18

I2S_50S I2S I2S0_CODEC_ASP_MCK 5 36
I144
I148 I2S_50S I2S I2S0_CODEC_ASP_MCK_R 5 18 36
DWI
A I145 I2S_50S I2S I2S3_CODEC_XSP_BCLK 5 18
SYNC_MASTER=MIKE SYNC_DATE=11/30/2011 A
I2S_50S I2S I2S3_CODEC_XSP_LRCK
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET 5 18 PAGE TITLE
CONSTRAINTS: LOW SPEED BUS

I149
I150 I2S_50S I2S I2S3_CODEC_XSP_DIN 5 18
DWI * * 2:1_SPACING
I151 I2S_50S I2S I2S3_CODEC_XSP_DOUT 5 18
DRAWING NUMBER SIZE
I161
I2S_50S I2S I2S0_CODEC_XSP_SDOUT
NET_TYPE I244 I2S_50S I2S I2S2_BT_BCLK 5 14
REVISION
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING I245 I2S_50S I2S I2S2_BT_LRCK 5 14
R
A.0.0
I247
I2S_50S I2S I2S2_BT_DIN 5 14
I152 DWI DWI_AP_CLK 5 30
I2S_50S I2S I2S2_BT_DOUT 5 14
I246 THE INFORMATION CONTAINED HEREIN IS THE
I153
DWI DWI_AP_DI 5 30 PROPRIETARY PROPERTY OF APPLE INC.
DWI DWI_AP_DO
I156 5 30
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EMBEDDED DISPLAYPORT BACKLIGHT
TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
MIPI EDP_90D * 90_OHM_DIFF
EDP_50S * 45_OHM_SE
TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_ASSIGNMENT_HEAD LED * LED LEDA * * 3:1_SPACING

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET LEDB * * 3:1_SPACING

MIPI_90D * 90_OHM_DIFF TABLE_SPACING_ASSIGNMENT_ITEM
EDP * * 4:1_SPACING
NET_TYPE
NET_TYPE
MIPI0C * * 4:1_SPACING ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
D MIPI1C * *
4:1_SPACING I435 EDP_90D

EDP_90D
EDP
EDP
EDP_AUX_P
EDP_AUX_N
7 15
7 15
I482
PHYSICAL
LED LEDA
SPACING
LED_IO1_A_R 30
D
I436
EDP_50S EDP EDP_HPD 7 15 I484 LED LEDB LED_IO1_B_R 30

I437
NET_TYPE EDP_90D EDP EDP_DATA_P<0> 7 15 I483
LED LEDA LED_IO2_A_R 30
I439
EDP_90D EDP EDP_DATA_N<0> 7 15 I485 LED LEDB LED_IO2_B_R 30
I438
EDP_90D EDP EDP_DATA_P<1> LED LEDA LED_IO3_A_R 30

MIPI_90D MIPI0C MIPI0C_CAM_RF_CLK_P 7 21 I440 7 15 I487
I315
EDP_90D EDP EDP_DATA_N<1> LED LEDB LED_IO3_B_R 30
MIPI_90D MIPI0C MIPI0C_CAM_RF_CLK_N 7 21 I442
7 15 I486
I316
MIPI_90D MIPI0C MIPI0C_CAM_RF_DATA_P<0> 7 21 I441 7 15 I489
I343

MIPI_90D MIPI0C MIPI0C_CAM_RF_DATA_N<0> 7 21 I444 7 15 I488
I342
MIPI_90D MIPI0C MIPI0C_CAM_RF_DATA_P<1> 7 21 I443
7 15 I490
I311
MIPI_90D MIPI0C MIPI0C_CAM_RF_DATA_N<1> 7 21 I445 7 15 I491
I312
EDP_90D EDP EDP_AUX_EMI_P 15 I492

LED LEDA LED_IO6_A_R 30
MIPI_90D MIPI0C MIPI0C_CAM_RF_CLK_F_P 20 21
I447
EDP LED LEDB LED_IO6_B_R
I395
EDP_90D EDP_AUX_EMI_N 15 I493 30
MIPI_90D MIPI0C MIPI0C_CAM_RF_CLK_F_N 20 21
I446
EDP LED LEDA LED_IO_1_A

I394
EDP_90D EDP_DATA_EMI_P<0> 15 I494 15 30
MIPI_90D MIPI0C MIPI0C_CAM_RF_DATA_F_P<0> 20 21
I449
EDP LED LEDB LED_IO_1_B
I519
EDP_90D EDP_DATA_EMI_N<0> 15 I495
15 30
MIPI_90D MIPI0C MIPI0C_CAM_RF_DATA_F_N<0> 20 21
I448
I518
MIPI_90D MIPI0C MIPI0C_CAM_RF_DATA_F_P<1> 20 21
I450

I521
EDP_90D EDP_DATA_EMI_N<1> 15 I497 15 30
MIPI_90D MIPI0C MIPI0C_CAM_RF_DATA_F_N<1> 20 21
I451
I520
MIPI_90D MIPI1C MIPI1C_CAM_FF_CLK_P 7 21
I452
I345
MIPI_90D MIPI1C MIPI1C_CAM_FF_CLK_N 7 21
I454
I346
EDP_90D EDP_DATA_EMI_P<3> 15 I500
15 30
MIPI_90D MIPI1C MIPI1C_CAM_FF_DATA_P<0> 7 21
I453
I347
MIPI_90D MIPI1C MIPI1C_CAM_FF_DATA_N<0> 7 21
I455
I348
EDP_90D CONN_EDP_AUX_EMI_P 15 I502 15 30
MIPI_90D MIPI1C MIPI1C_CAM_FF_CLK_F_P 20 21
I457
I354
EDP_90D CONN_EDP_AUX_EMI_N 15 I503
15 30
MIPI_90D MIPI1C MIPI1C_CAM_FF_CLK_F_N 20 21
I456
I356
I458 EDP_90D CONN_EDP_DATA_EMI_P<0> 15 I504 15 30
I415 MIPI_90D MIPI1C MIPI1C_CAM_FF_DATA_F_P<0> 20 21

EDP_90D EDP CONN_EDP_DATA_EMI_N<0> 15 I505 LED LEDB LED_IO_6_B 15 30
I460
I414
MIPI_90D MIPI1C MIPI1C_CAM_FF_DATA_F_N<0> 20 21
EDP_90D EDP CONN_EDP_DATA_EMI_P<1> 15
I459
EDP CONN_EDP_DATA_EMI_N<1>
C I462
I461
EDP_90D
EDP_90D EDP
EDP
CONN_EDP_DATA_EMI_P<2>
15
15 C
I463
EDP_90D CONN_EDP_DATA_EMI_N<2> 15
EDP_90D EDP CONN_EDP_DATA_EMI_P<3> 15

I464
EDP_90D EDP CONN_EDP_DATA_EMI_N<3> 15

I465
TEMP SENSORS
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

BOARD_TEMP * TEMP_SENSE
AUDIO/SPEAKER BOARD_TEMP * * 3:1_SPACING
NET_TYPE
TABLE_SPACING_ASSIGNMENT_ITEM ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
AUDIO * * 3:1_SPACING
I572 BOARD_TEMP BOARD_TEMP1 30 32
NET_TYPE
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING I574 BOARD_TEMP BOARD_TEMP2 30 32
I584 AUDIO_DIFF AUDIO HP_MIC_P 18 I576

BOARD_TEMP BOARD_TEMP BOARD_TEMP3_P 30
I585 AUDIO_DIFF AUDIO HP_MIC_N 18 I577 BOARD_TEMP BOARD_TEMP BOARD_TEMP3_N 30
BOARD_TEMP BOARD_TEMP BOARD_TEMP4_P 30

I587 AUDIO_DIFF AUDIO L81_AIN2_P 18
I578
BOARD_TEMP BOARD_TEMP BOARD_TEMP4_N 30

I586 AUDIO_DIFF AUDIO L81_AIN2_N 18
I579
I580 BOARD_TEMP BOARD_TEMP BOARD_TEMP5_P 30
I589 AUDIO_DIFF AUDIO SPKR_L_VSENSE_N_FILT 19 I581 BOARD_TEMP BOARD_TEMP BOARD_TEMP5_N 30
I588 AUDIO_DIFF AUDIO SPKR_L_VSENSE_P_FILT 19 I582 BOARD_TEMP BOARD_TEMP BOARD_TEMP6_P 30
I591 AUDIO_DIFF AUDIO SPKR_L_VSENSE_N 19 I583 BOARD_TEMP BOARD_TEMP BOARD_TEMP6_N 30
I590 AUDIO_DIFF AUDIO SPKR_L_VSENSE_P 19 I602 BOARD_TEMP BOARD_TEMP BOARD_TEMP7_P 30
B I592 AUDIO_DIFF AUDIO SPKR_R_VSENSE_N_FILT 19

I603
I604
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP
BOARD_TEMP7_N
BOARD_TEMP8_P
30
30
B
I593 AUDIO_DIFF AUDIO SPKR_R_VSENSE_P_FILT 19
I605 BOARD_TEMP BOARD_TEMP BOARD_TEMP8_N 30
I594 AUDIO_DIFF AUDIO SPKR_R_VSENSE_N 19
I595 AUDIO_DIFF AUDIO SPKR_R_VSENSE_P 19
I597 SPEAKER AUDIO SPKR_L_P 19
I596 SPEAKER AUDIO SPKR_L_N 19
I598 SPEAKER AUDIO SPKR_L_CONN_P 19
I599 SPEAKER AUDIO SPKR_L_CONN_N 19
I606 SPEAKER AUDIO SPKR_R_P 19
I607 SPEAKER AUDIO SPKR_R_N 19
I608 SPEAKER AUDIO SPKR_R_CONN_P 19
I609 SPEAKER AUDIO SPKR_R_CONN_N 19
I610 SPEAKER AUDIO SPKR_L_FLR 19
I611 SPEAKER AUDIO SPKR_R_FLR 19
I564
AUDIO_DIFF AUDIO SPKR_L_SES_N 19
I565 AUDIO_DIFF AUDIO SPKR_L_SES_P 19
I558 AUDIO_DIFF AUDIO SPKR_R_SES_N 19
I560 AUDIO_DIFF AUDIO SPKR_R_SES_P 19
A I570 USB_90D USB MIKEY_TS_P 18 25

USB_90D USB MIKEY_TS_N 18 25 PAGE TITLE
CONSTRAINTS: DISPLAY/AUDIO
I569
I600 USB_90D USB L81_MBUS_P 18
USB_90D USB L81_MBUS_N 18

DRAWING NUMBER SIZE
I601

REVISION
R
A.0.0
152 OF 154
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
DDR
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

DDR_50S * DDR_45_OHM_SE DDR * * 3:1_SPACING
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
DDR_90D *
DDR_90_OHM_DIFF NAND WIFI

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
NET_TYPE TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
NAND_50S * 45_OHM_SE
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING NAND0 * * 2:1_SPACING WIFI_50S * WIFI_50S
D NAND1 * *
2:1_SPACING WIFI_PWR100 * WIFI_PWR100

D
WIFI_PWR1000 * WIFI_PWR1000
I221 DDR_50S DDR DDR0_CA<9..0> 8 11
I222 DDR_50S DDR DDR0_DM<3..0> 8 11
I223 DDR_90D DDR DDR0_CK_P 8 11

NET_TYPE NET_TYPE
I225 DDR_90D DDR DDR0_CK_N 8 11

I226 DDR_50S DDR DDR0_CKE<1..0> 8 11

WIFI_50S 50_WLAN_G
I224 DDR_50S DDR DDR0_CSN<2..0> 8 11
NAND_50S NAND0 FMI0_AD<0>
I245 27
I68 6 13
I246 WIFI_50S 50_WLAN_A 27
I69 NAND_50S NAND0 FMI0_AD<1> 6 13

WIFI_50S 50_WLAN_G_1
I228 DDR_50S DDR DDR0_ZQ 11
I247 27
I70 6 13
WIFI_50S 50_WLAN_A_DIPLX
I230 DDR_50S DDR DDR0_DQ<7..0> 8 11
I248 27
I71 6 13
WIFI_50S 50_WIFI_ANT_FD_2
I229 DDR_90D DDR DDR0_DQS_P<0> 8 11
I249
I72 6 13
WIFI_50S 50_WIFI_ANT_FD_1
I231 DDR_90D DDR DDR0_DQS_N<0> 8 11
I250
I73 6 13
WIFI_50S 50_WIFI_ANT_FD
I232 DDR_50S DDR DDR0_DQ<15..8> 8 11
NAND_50S NAND0 FMI0_AD<6> 6 13
I251
I74
I75
NAND_50S NAND0 FMI0_ALE 6 13
I76
I234 DDR_50S DDR DDR0_DQ<23..16> 8 11
NAND_50S NAND0 FMI0_CE0_L 6 13
I77
NAND_50S NAND0 TP_FMI0_CE1_L
I78
I120
I238 DDR_50S DDR DDR0_DQ<31..24> 8 11
I121
I122
I123
I124 NAND_50S NAND0 TP_FMI0_CE6_L

I125 NAND_50S NAND0 TP_FMI0_CE7_L
I201 DDR_50S DDR DDR1_CA<9..0> 8 11
NAND_50S NAND0 FMI0_CLE 6 13
I126
I202 DDR_50S DDR DDR1_DM<3..0> 8 11
C I203
I205
DDR_90D
DDR_90D
DDR
DDR
DDR1_CK_P
DDR1_CK_N
8 11
8 11
I128 NAND_50S NAND0 FMI0_DQS 6 13
C
I206 DDR_50S DDR DDR1_CKE<1..0> 8 11
I204 DDR_50S DDR DDR1_CSN<2..0> 8 11

NAND_50S NAND0 FMI0_RE_L 6 13
I131

NAND_50S NAND0 FMI0_WE_L 6 13
I133
I210 DDR_50S DDR DDR1_DQ<7..0> 8 11

I135
I212 DDR_50S DDR DDR1_DQ<15..8> 8 11
I136
I137
I138
I214 DDR_50S DDR DDR1_DQ<23..16> 8 11
I139
I140
I141
I218 DDR_50S DDR DDR1_DQ<31..24> 8 11
I142
NAND_50S NAND1 FMI1_ALE 6 13
I143
NAND_50S NAND1 FMI1_CE0_L 6 13
I144
I181 DDR_50S DDR DDR2_CA<9..0> 8 12

I146
I182 DDR_50S DDR DDR2_DM<3..0> 8 12

I148
I149
I186 DDR_50S DDR DDR2_CKE<1..0> 8 12
I150
I184 DDR_50S DDR DDR2_CSN<2..0> 8 12
I151
I152 NAND_50S NAND1 FMI1_CLE 6 13

DDR2_ZQ
B I188
I190
DDR_50S
DDR_50S
DDR
DDR DDR2_DQ<7..0>
12
8 12
I154 NAND_50S NAND1 FMI1_DQS 6 13
B
I192 DDR_50S DDR DDR2_DQ<15..8> 8 12

NAND_50S NAND1 FMI1_RE_L 6 13
I156

NAND_50S NAND1 FMI1_WE_L 6 13
I160
I194 DDR_50S DDR DDR2_DQ<23..16> 8 12
I198 DDR_50S DDR DDR2_DQ<31..24> 8 12
I38 DDR_50S DDR DDR3_CA<9..0> 8 12
I39 DDR_50S DDR DDR3_DM<3..0> 8 12
DDR_50S DDR DDR3_CKE<1..0> 8 12

I43
I47 DDR_50S DDR DDR3_CSN<2..0> 8 12
DDR VREF

I37 DDR_50S DDR DDR3_DQ<7..0> 8 12

VREF * * 5:1_SPACING

NET_TYPE
I172 DDR_50S DDR DDR3_DQ<15..8> 8 12
A I173
I174
DDR_90D
DDR_90D
DDR
DDR
DDR3_DQS_P<1>
DDR3_DQS_N<1>
8 12
8 12 I166 PWR PPVREF_DDR0_CA 11 39

DDR_50S DDR DDR3_DQ<23..16> I167 PWR PPVREF_DDR0_DQ 11 39 PAGE TITLE
CONSTRAINTS: DDR/FMI
I175 8 12
DDR_90D DDR DDR3_DQS_P<2> 8 12 I169 PWR PPVREF_DDR1_CA 11 39

I176
DDR_90D DDR DDR3_DQS_N<2> 8 12 I168 PWR PPVREF_DDR1_DQ 11 39
DRAWING NUMBER SIZE
I177
DDR_50S DDR DDR3_DQ<31..24> PWR PPVREF_DDR2_CA 12 39
051-9385 D
I178
DDR_90D DDR DDR3_DQS_P<3>
8 12
8 12
I244
I243 PWR PPVREF_DDR2_DQ 12 39

Apple Inc. REVISION
I179
DDR_90D DDR DDR3_DQS_N<3> 8 12 I241 PWR PPVREF_DDR3_CA 12 39
R
A.0.0
I180
I242 PWR PPVREF_DDR3_DQ 12 39
153 OF 154
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
PWR GND
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
PP_PWR * PWR_PMU
PWR * * 3:1_SPACING GND * GND_PH
NET_TYPE NET_TYPE
VOLTAGE PHYSICAL SPACING
D
I221
I1
1.1V
1.1V
PP_PWR
PP_PWR
PWR
PWR
BUCK0A_LX0
BUCK0A_LX1
29
29
I199
VOLTAGE=0V GND GND GND
D
I2
1.1V PP_PWR PWR BUCK0A_FB 29 I200
VOLTAGE=0V GND GND GND_AUDIO_CODEC 18
I3 1.1V PP_PWR PWR PP1V1_CPU0_FET 29 30
I4 1.1V PP_PWR PWR BUCK0B_LX0 29
I5
1.1V PP_PWR PWR BUCK0B_LX1 29 I203
VOLTAGE=0V GND GND GND_SPKR_AMP1
I6 1.1V PP_PWR PWR BUCK0B_FB 29 I207 VOLTAGE=0V GND GND GND_SPKR_AMP2
I7 1.1V PP_PWR PWR PP1V1_CPU1_FET 29 30
I8
1.1V PP_PWR PWR BUCK0C_LX0 29
I9 1.1V PP_PWR PWR BUCK0C_FB 29 I217 VOLTAGE=0V GND GND AGND_U3000 16
1.1V PP_PWR PWR PP1V1_CPUB 29 34

I12
I224 VOLTAGE=0V GND GND J2200_29_GND 15
I11 1.2V PP_PWR PWR BUCK2_LX0 29
VOLTAGE=0V GND GND J2200_36_GND 15
I225
I10 1.2V PP_PWR PWR BUCK2_LX1 29 I226 VOLTAGE=0V GND GND J2200_43_GND 15
I13
1.2V PP_PWR PWR BUCK2_LX2 29
I15 1.2V PP_PWR PWR BUCK2_FB 29
I14 1.2V PP_PWR PWR PP1V2_SOC 29 34
I16
I18 1.8V PP_PWR PWR PP1V8_S2R 29 34 RST

I19
I20 1.2V PP_PWR PWR BUCK4_FB 29 NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

I21 1.2V PP_PWR PWR PP1V2_S2R 29 34
RST * * 4:1_SPACING
I23 1.1V PP_PWR PWR BUCK5_LX0 29

NET_TYPE
I24
3.3V PP_PWR PWR PP3V3_OUT 29 34
I25 3.0V PP_PWR PWR PP3V0_GRAPE 29 34
1.7V PP_PWR PWR PP1V7_VA_VCP 19 29 34

BB_TRST_L
C C
I26
RST
3.0V PP_PWR PWR PP3V2_S2R_USBMUX 29 34 39
I165
I28
I166 RST DBG_RST
RST DEBUG_RST_L
3.2V PP_PWR PWR LDO5 29
I167
I29
RST GSM_TXBURST_IND
3.3V PP_PWR PWR PP3V3_ACC 29 34
I171
I30
RST JTAG_AP_TRST_L 4 10 36
3.0V PP_PWR PWR PP3V0_S2R_HALL 29 34
I169
I31
RST RST_AP_1V8_L
3.0V PP_PWR PWR PP3V2_S2R_USBMUX 29 34 39
I170
I32
RST RST_AP_L 4 25 26 30
3.0V PP_PWR PWR PP3V0_IO 29 34
I168
I33
RST GPIO_BB_RST_L 5 26
3.0V PP_PWR PWR PP3V0_SENSOR 29 34
I172
I34
RST RST_BB_PMU_L
2.8V PP_PWR PWR PP2V8_CAM 29 34
I174
I35
RST RST_BT_L
1.0V PP_PWR PWR PP1V0 29 34
I173
I36
RST RST_DET_L
1.1V PP_PWR PWR PP1V1_SRAM 29 34
I175
I37
GRAPE RST_GRAPE_L
1.8V PP_PWR PWR PP1V8_ALWAYS 29 34
I176
I38
RST RST_L63_L
1.2V PP_PWR PWR PP1V2 29 34
I177
I39
RST RST_PMU_IN
PP_PWR PWR DSP_SW I178
I40
RST RST_WLAN_L
1.8V PP_PWR PWR PP1V8 29 32 34
I179
I41
RST SIMCRD_RST
I42 1.8V PP_PWR PWR PP1V8_GRAPE I181
4.7V PP_PWR PWR PPVCC_MAIN 15 25 29 30 34

I43
RST UD881_RST
4.2V PWR500 PWR PPBATT_VCC 29 32 34
I182
I44
RST UD882_RST
I45 6.0V PP_PWR PWR PP6V0_LCM_HI 30
I183
I46
6.0V PP_PWR PWR LCM_LX 30
I47 6.0V PP_PWR PWR PP6V0_LCM_VBOOST 30
I49 5.25V PP_PWR PWR PP5V25_VLCM1

I51
1.1V PP_PWR PWR PP1V1_CPU0 30 34
I50 1.1V PP_PWR PWR PP1V1_CPU1 30 34
I53
20.4V PP_PWR PWR PPLED_OUT_A 30 34
B I52
I54
20.4V
1.8V
PP_PWR
PP_PWR
PWR
PWR
PPLED_OUT_B
PP1V8_PL0_F
30 34
4
B
I55 1.0V PP_PWR PWR PP1V0_MIPI_PLL_F 7
I56 1.8V PP_PWR PWR PP1V8_EDP_AVDD_AUX 7
I57
1.8V PP_PWR PWR PP1V8_DP_AVDD_AUX
I58 3.3V PP_PWR PWR PP3V3_S0_LCD_FERR 15
I59 3.3V PP_PWR PWR PP3V3_LCDVDD_SW_F 15
I60
20.4V PWR500 PWR PPLED_BACK_REG_B 15
I61 20.4V PP_PWR PWR PPLED_BACK_REG_A 15
I64 6V PP_PWR PWR PPVBUS_USB_EMI 23 34
I67 0.6V PP_PWR PWR PPVREF_DDR0_CA 11 38
I68
0.6V PP_PWR PWR PPVREF_DDR0_DQ 11 38
I70
0.6V PP_PWR PWR PPVREF_DDR1_DQ 11 38
I72 0.6V PP_PWR PWR PPVREF_DDR2_DQ 12 38
I73
0.6V PP_PWR PWR PPVREF_DDR3_CA 12 38
I74 0.6V PP_PWR PWR PPVREF_DDR3_DQ 12 38
I76 PP_PWR PWR DAC_AP_VREF 7
I75 4.6V PP_PWR PWR BATT_POS_RC 29
I223 4.6V PP_PWR PWR BATT_VCC_WLAN 27
A I222 1.8V PP_PWR PWR PP_WLAN_VDDIO_1V8 27
PAGE TITLE
I227 3.55V PP_PWR PWR LDO10 18 29
CONSTRAINTS: POWER / GND
DRAWING NUMBER SIZE

REVISION
R
A.0.0
154 OF 154
8 7 6 5 4 3 2 1

Ipad4 579ca1458-Schematic

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820-3249-TOP MLB

C1621 C1652 C1635 C1632 C1623

J5400 J5401 J3010 J3011 R9000

C5936 C8109 C8110 C8256

R8170 FL7500 C7523

C1315 C1191 C1107 C1155 C1190 C1415 C3006

C5740 FL5710 C0614 C1180

C0931 C0811 C5580 C5550

C0909 C5572 C5583 C5552

iPad 4th Gen

LAST_MODIFIED=Thu Jul 26 10:29:36 2012

PDF CSA CONTENTS SYNC MASTER DATE (SYSTEM DRI)

1 1 Table of Contents N/A N/A

31 83 PMU: ADRIANA PAGE 3 MADHAVI 12/06/2011 (MADHAVI)

2 2 BLOCK DIAGRAM: SYSTEM N/A N/A

32 90 DEBUG/MISC. MLB 11/09/2011 (AMANDA)

3 4 BOM TABLES N/A N/A (AMANDA)

33 93 TEST/HOLES/FIDUCUALS N/A N/A (AMANDA)

34 121 POWER ALIASES N/A N/A (MADHAVI)

35 150 CONSTRAINTS: MLB RULES MIKE 11/30/2011 (AMANDA)

36 151 CONSTRAINTS: LOW SPEED BUS MIKE 11/30/2011 (AMANDA)

37 152 CONSTRAINTS: DISPLAY/AUDIO MIKE 11/30/2011 (AMANDA)

39 154 CONSTRAINTS: POWER / GND MIKE 11/30/2011 (AMANDA)

16 30 GRAPE: GROUNDHOG,CONN,BOOST N/A N/A

18 36 AUDIO: L81 CODEC N/A N/A

25 59 TRISTAR N/A N/A

28 75 POWER: BATTERY CONNECTOR MADHAVI 12/06/2011 (MADHAVI)

30 82 PMU: ADRIANA PAGE 2 MADHAVI 12/06/2011 (MADHAVI)

Apple Inc. 051-9385 D

CSA 31 ISP_I2C0 REAR CAMERA

GYRO ACCELEROMETER ALS HP

NAND FLASH BLOCK DIAGRAM: SYSTEM

Apple Inc. 051-9385 D

CSA 16 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

SCH AND BOARD P/N

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

051-9385 1 SCH,MLB,X140 SCH1 CRITICAL

(NONE) 820-3249 1 PCBF,MLB,X140 PCB1 CRITICAL

Signal aliases required by this page:

BOM options provided by this page:

ALTERNATE PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

16GB_PROD: 16GB CONFIG

32GB_PROD: 32GB CONFIG 343S0598 1 IC,SOC,H5G,FCBGA1089,0.5MM U0600 CRITICAL

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

343S0622 1 IC,PMU,ADRIANA,D2018A1,FCBGA U8100 CRITICAL

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

333S0636 2 LPDDR2,533MHZ,512MB,SAMSUNG,35NM U1300,U1400 CRITICAL

BOM GROUP BOM OPTIONS

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

335S0878 1 TOSHIBA PPN1.5 16GB U1600 CRITICAL 16GB_PROD

32GB FLASH CONFIGURATIONS

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_HEAD 335S0879 1 TOSHIBA PPN1.5 32GB U1600 CRITICAL 32GB_PROD

B NAND 806-4195 1 FENCE,NAND,TOP,MLB,X140 PD_FENCE_NAND CRITICAL

AUDIO 806-3956 1 FENCE,AMP,MLB,X140 PD_FENCE_AMP CRITICAL

GRAPE 806-4196 1 FENCE,1,BTM,MLB,X140 PD_FENCE_BTM1 CRITICAL

MEMORY 806-3492 1 FENCE,2,BTM,MLB,X140 PD_FENCE_BTM2 CRITICAL

64GB FLASH CONFIGURATIONS

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

825-7838 1 EEEE FOR 639-3736 (MLB A 16G) EEEE_F1WD CRITICAL EEEE_MLB_A_16G

825-7838 1 EEEE FOR 639-3737 (MLB A 32G) EEEE_F1WH CRITICAL EEEE_MLB_A_32G