IPAD 3 J2-MLB 051-8773 r1000

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
10 0001231154 ENGINEERING RELEASED 2011-09-06
J2 MLB - DVT OK2FAB

LAST_MODIFIED=Tue Sep 6 17:35:11 2011
D D
PDF CSA CONTENTS
TABLE_TABLEOFCONTENTS_HEAD
SYNC MASTER DATE PDF CSA CONTENTS
TABLE_TABLEOFCONTENTS_HEAD
SYNC MASTER DATE
1
TABLE_TABLEOFCONTENTS_ITEM
1 Table of Contents MIKE NA 32
62 WLAN 2.4GHZ AND ANT X26_WIFI_MIKE_BT 09/01/2011
2
2 BLOCK DIAGRAM: SYSTEM J2DEV N/A 33
63 WLAN 5GHZ AND TEST POINTS X26_WIFI_MIKE_BT 09/01/2011
3
4 BOM TABLES MIKE N/A 34
75 POWER: BATTERY CONNECTOR MADHAVI 01/13/2011
4
6 AP: MAIN MIKE N/A 35
80 POWER ALIASES MADHAVI 01/13/2011
5
7 AP: I/Os JOE N/A 36
81 POWER: AMELIA PMU MADHAVI 01/13/2011
6
8 AP: NAND MIKE N/A 37
82 POWER: AMELIA PMU MLB 01/14/2011
7
9 AP: TV,DP,MIPI JOE 01/13/2011 38
83 POWER: AMELIA VSS MADHAVI 01/13/2011
8 10 AP: DDR MIKE N/A 39 90 DEBUG AND MISC ALEX 10/04/2010

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
9
11 AP: POWER MIKE N/A 40
93 FCT/ICT TEST/BRACKETS ALEX 10/04/2010
C 10
12 AP: MISC & ALIASES ALEX N/A 41
150 CONSTRAINTS: MLB RULES MIKE 01/21/2011 C
11 13 AP: VIDEO BUFFER,BB USB MUXES CHOPIN 12/10/2010 42 151 CONSTRAINTS: LOW SPEED BUS MIKE 01/21/2011
12
14 NAND MIKE N/A 43
152 CONSTRAINTS: DISPLAY/AUDIO MIKE 01/21/2011
13
16 DDR 0 AND 1 MIKE 06/21/2010 44
153 CONSTRAINTS: DDR/FMI MIKE 01/21/2011
14
17 DDR 2 AND 3 MIKE 06/21/2010 45
154 CONSTRAINTS: POWER / GND MIKE 01/21/2011
15 21 MLB ALIASES/CONNECTIONS ALEX 09/30/2010 46 155 CONSTRAINTS: DEBUG MIKE 01/21/2011

16
22 VIDEO: EDP CONNECTOR JOE 01/19/2011 47
156 FUNC TEST POINTS MIKE 01/21/2011
17
30 GRAPE: GROUNDHOG,CONN,BOOST RAMSIN 12/17/2010 48
157 FUNC TEST POINTS MIKE 01/21/2011
18
31 GRAPE: Z1, Z2 RAMSIN 12/17/2010
19
36 AUDIO: L63B CODEC KAVITHA 02/03/2011
20 37 AUDIO: SPEAKER AMP KAVITHA 02/03/2011

B TABLE_TABLEOFCONTENTS_ITEM
B
21 38 AUDIO: HEADPHONE OUT KAVITHA 02/03/2011
22
42 AUDIO: DETECT/MIC BIAS KAVITHA 02/03/2011
23
43 AUDIO: HP/MIC FILTERS KAVITHA 02/03/2011
24
54 CONNECTOR: SENSOR MARK 01/11/2011
25
55 SENSOR PANEL FILTERS 1 MARK 01/11/2011
26
56 SENSOR PANEL FILTERS 2 MARK 01/11/2011
27
57 IO FLEX: DOCK COMPONENTS JOE 01/19/2011
28
58 DISPLAY PORT MISC JOE 01/19/2011
29
59 IO FLEX: B2B CONNECTOR JOE 01/19/2011
30
60 CONNECTOR: X26 JOE 01/19/2011
A 31 61 WLAN BB & POWER X26_WIFI_MIKE_BT 09/01/2011 SYNC_MASTER=MIKE SYNC_DATE=NA A

TABLE_TABLEOFCONTENTS_ITEM DRAWING TITLE
SCH,J2,MLB
DRAWING NUMBER SIZE
Apple Inc. 051-8773 D

REVISION
R
10.0.0
DRAWING
NOTICE OF PROPRIETARY PROPERTY: BRANCH
DRAWING THE INFORMATION CONTAINED HEREIN IS THE
MLB PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
Schematic / PCB #’s I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 157
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 1 OF 48
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ISP_I2C1 FF CAMERA
Z2 MIPI1C VGA FLEX
CSA 31
SPI1
H4G ISP_I2C0 REAR CAMERA
MIPI0C VA5/8 FLEX
D D
GROUNDHOG DUAL-CORE ARM
Z1 CORTEX-A9 W/ SMP HSIC1_1
950 MHZ MIMO WIFI ANT 1
CSA 30 CSA 31
UART3 WIFI/BT
LPDDR2 UART6 BT_I2S
WIFI/BT ANT 2
1 GBYTE GPU CSA 61-64
4X32-BIT QUAD-CORE IMG
400MHZ/800MB/S SGX543-MP2
X26
CELLULAR/GPS
DISPLAY/ AUDIO HSIC0_1 HSIC1
PRIMARY CELLULAR ANT
TOUCH PANEL EDP AE2 UART1 USART
ARM A5 CPU
DIVERSITY CELLULAR ANT
RESOLUTION: 2048X1536
C SPI2 IPC C
GPS ANT
BACKLIGHT CSA 60
UART5
USB2.0
PMU UART0
BATTERY 30-PIN
AMELIA DOCK
DISPLAYPORT
CSA 75
VIDEO DAC AMP
DWI
I2C 8’H78 I2C0
CSA 81,82
B B
AUDIO CODEC
I2C1 L63B
I2S2 VSP LINEOUT CSA 57
HALL EFF PROX SENSOR COMPASS AMP
I2C 8’H58 I2C 8’H1C I2S0 ASP
SPEAKER
BUTTON FLEX SENSOR PANEL SENSOR PANEL
I2S3 XSP AMP
MIC
I2C2 FMI0 FMI1 FMI2 FMI3 I2C 8’H94
CSA 36
MUX
US/CHINA EXT MIC
I2C 8’H76
A SYNC_MASTER=J2DEV SYNC_DATE=N/A A
PAGE TITLE
GYRO ACCELEROMETER ALS BLOCK DIAGRAM: SYSTEM

DRAWING NUMBER SIZE
I2C 8’HD0 I2C 8’H32 I2C 8’H72 NAND FLASH NAND FLASH Apple Inc. 051-8773
REVISION
D
SENSOR PANEL SENSOR PANEL VGA FLEX PPN1.0 PPN1.0 R

10.0.0
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
CSA 14 CSA 14 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
2 OF 157
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SCH AND BOARD P/N
TABLE_5_HEAD
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
Page Notes 051-8773 1 SCH,MLB,J2 SCH1 CRITICAL ?

TABLE_5_ITEM
TABLE_5_ITEM
Power aliases required by this page: 820-2996 1 PCBF,MLB,J2 PCB1 CRITICAL ?

(NONE) TABLE_5_ITEM
085-3058 1 DEV BOM,MLB,J2 DEV1 ?

Signal aliases required by this page:
(NONE)
BOM options provided by this page: SOC

D PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_HEAD
TABLE_5_ITEM
D
ALL AVAIL BOM OPTIONS 343S0533 1 IC,SOC,H4G,FCBGA1225 U0600 CRITICAL ?
COMMON
ALTERNATE
16GB_PROD
32GB_PROD
64GB_PROD
PMU
128GB_PROD TABLE_5_HEAD

DEVELOPMENT_JTAG TABLE_5_ITEM
DEVELOPMENT_JTAG_TAP 343S0561 1 IC,PMU,AMELIA,D1974AB U8100 CRITICAL ?

JTAG_DAP
SPEAKER
INTERNAL_MIC
NAND_IO_1V8
NAND_IO-3V3
SNOTE
DEV
MLB
J2
SDRAM
TABLE_BOMGROUP_HEAD TABLE_5_HEAD
BOM GROUP BOM OPTIONS PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_BOMGROUP_ITEM TABLE_5_ITEM
BASIC COMMON,ALTERNATE 333S0579 2 SDRAM,LPDDR2,512MB,SAMSUNG 46NM U1600,U1700 CRITICAL ?

TABLE_BOMGROUP_ITEM
AUDIO SPEAKER,INTERNAL_MIC TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
TABLE_ALT_ITEM
333S0580 333S0579 U1600,U1700 LPDDR2,HYNIX 44NM

TABLE_ALT_ITEM
C 333S0581 333S0579 U1600,U1700 LPDDR2,ELPIDA 45NM

C
BARCODE LABEL/EEEE CODES

TABLE_5_HEAD
NAND
825-7691 1 EEEE FOR 639-2352 (J1 16G) EEEE_DNKT CRITICAL EEEE_J1_16G

TABLE_5_ITEM
16GB FLASH CONFIGURATIONS

TABLE_5_HEAD
TABLE_5_ITEM

825-7691 1 EEEE FOR 639-2058 (J1 32G) EEEE_DM2N CRITICAL EEEE_J1_32G TABLE_5_ITEM
TABLE_5_ITEM
335S0781 1 HYNIX 26NM PPN1.0 16GB U1400 CRITICAL 16GB_PROD

825-7691 1 EEEE FOR 639-2059 (J1 64G) EEEE_DM2P CRITICAL EEEE_J1_64G
TABLE_5_ITEM
825-7691 1 EEEE FOR 639-2353 (J2 16G) EEEE_DNKV CRITICAL EEEE_J2_16G TABLE_ALT_HEAD

TABLE_5_ITEM
PART NUMBER
825-7691 1 EEEE FOR 639-1572 (J2 32G) EEEE_DHWV CRITICAL EEEE_J2_32G TABLE_ALT_ITEM
TABLE_5_ITEM
335S0804 335S0781 16GB_PROD U1400 TOSHIBA 24NM PPN1.0

825-7691 1 EEEE FOR 639-1871 (J2 64G) EEEE_DKQL CRITICAL EEEE_J2_64G
TABLE_5_ITEM
825-7691 1 EEEE FOR 639-1870 (J2 128G) EEEE_DKQK CRITICAL EEEE_J2_128G

TABLE_5_ITEM
825-7691 1 EEEE FOR 639-2844 (J2A 16G) EEEE_DRJQ CRITICAL EEEE_J2A_16G

TABLE_5_ITEM TABLE_5_HEAD
825-7691 1 EEEE FOR 639-2826 (J2A 32G) EEEE_DRF6 CRITICAL EEEE_J2A_32G PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM TABLE_5_ITEM
825-7691 1 EEEE FOR 639-2827 (J2A 64G) EEEE_DRF5 CRITICAL EEEE_J2A_64G 335S0781 2 HYNIX 26NM PPN1.0 16GB U1400,U1410 CRITICAL 32GB_PROD
TABLE_ALT_HEAD

PART NUMBER
MECHANICAL PARTS TABLE_ALT_ITEM
B PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_HEAD
335S0804 335S0781 32GB_PROD U1400,U1410 TOSHIBA 24NM PPN1.0
B
TABLE_5_ITEM
806-2105 1 FENCE,NAND,TOP,MLB,J2 PD_FENCE_NAND CRITICAL

806-1857 1 FENCE,LARGE,TOP,MLB,J2 PD_FENCE_LARGE CRITICAL
TABLE_5_ITEM

TABLE_5_HEAD
TABLE_5_ITEM

806-2349 1 FENCE,SMALLER,TOP,MLB,J2 PD_FENCE_SMALL CRITICAL TABLE_5_ITEM
TABLE_5_ITEM
335S0782 2 HYNIX 26NM PPN1.0 32GB U1400,U1410 CRITICAL 64GB_PROD

806-1860 1 FENCE,1,BTM,MLB,J2 PD_FENCE_BTM1 CRITICAL
TABLE_5_ITEM
806-1865 1 FENCE,2,BTM,MLB,J2 PD_FENCE_BTM2 CRITICAL TABLE_ALT_HEAD

TABLE_5_ITEM
PART NUMBER
806-2352 1 FENCE,SMALLER,BTM,MLB,J2 PD_FENCE_BTM3 CRITICAL TABLE_ALT_ITEM

TABLE_5_HEAD

TABLE_5_ITEM
335S0814 2 HYNIX 26NM PPN1.0 64GB U1400,U1410 CRITICAL 128GB_PROD
TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
A SYNC_MASTER=MIKE SYNC_DATE=N/A A
PAGE TITLE
BOM TABLES
DRAWING NUMBER SIZE

REVISION
R
10.0.0
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
4 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R0601 R0605
A1 AJ34
0.00 2 0.00 2
=PP1V1_PLL_H4 1 PP1V1_PL3_F PP1V1_PL4_F 1 =PP1V1_PLL_H4
A2 U0600 AK2
35 4
0%
45
VOLTAGE=1.1V
MIN_LINE_WIDTH=0.2MM
45
VOLTAGE=1.1V
MIN_LINE_WIDTH=0.2MM 0%
4 35
A5 H4G AL1
1/32W
MF
1 C0600 MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.1MM
1 C0603 1/32W
MF
FCBGA 01005 0.01UF MAX_NECK_LENGTH=3MM MAX_NECK_LENGTH=3MM 0.01UF 01005
A8 OMIT AM3 10% 10%
2 6.3V
X5R 2 6.3V
X5R
A11 (11 OF 12) AM8
01005 01005
A14 AM19
A17 AM22
R0602 R0606
0.00 2 0.00 2
1 45 PP1V1_PL2_F 45 PP1V1_PL5_F 1
A34 AM25 VOLTAGE=1.1V VOLTAGE=1.1V
0% MIN_LINE_WIDTH=0.2MM MIN_LINE_WIDTH=0.2MM 0%
A35 AM28 1/32W 1 C0601 MIN_NECK_WIDTH=0.1MM MIN_NECK_WIDTH=0.1MM 1 C0604 1/32W
D AA2 AM32
MF
01005
10%
0.01UF NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM
MAX_NECK_LENGTH=3MM 0.01UF
10%
MF
01005 D
AA8 AM34 2 6.3V 2 6.3V
AA10 AN7
X5R
01005
X5R
01005 FL0600
AA12 AN10
R0603 80-OHM-0.2A-0.4-OHM
0.00 2 1 2
1 45 PP1V1_PL1_F 45 PP1V1_MIPID_PLL_F =PP1V1_MIPI_PLL_H4 35
AA14 AN13 VOLTAGE=1.1V VOLTAGE=1.1V
0% MIN_LINE_WIDTH=0.2MM MIN_LINE_WIDTH=0.2MM 0201
AA16 AN16 1/32W
MF
1 C0620 1 C0621 1 C0622
AA18 AP1 01005 0.01UF MAX_NECK_LENGTH=3MM MAX_NECK_LENGTH=3MM 56PF 0.01UF 1UF
10% 5% 10% 10%
AA20 AP2 6.3V
2 X5R 6.3V
2 NP0-C0G 6.3V
2 X5R 6.3V
2 CERM
AA22 AP6 01005 01005 01005 402
AA24 AP9 R0604
AA26 AP12 0.00 2
1 45 PP1V1_PL0_F =PP1V1_USB_H4 4 35
VOLTAGE=1.1V
AA35 AP15 0% MIN_LINE_WIDTH=0.2MM
AB1 AP18
1/32W
MF
1 C0608 1 C0609
01005 0.01UF MAX_NECK_LENGTH=3MM 0.01UF 0.01UF
AB4 AP22 10% 10% 10%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
AB8 AP25
01005 01005 01005
AB9 AP28
AB11 AP31
=PP3V3_USB_H4 4 35
AB13 AP34 35 =PP1V1_HSIC_H4
AB15 AP35
AB17 AR1
1 C0630 1 C0631 1 C0612 1 C0614
0.01UF 0.01UF 0.01UF 1UF
AB19 AR2 10% 10% 10% 10%
6.3V 6.3V 6.3V 6.3V
AB21 AR5 2 X5R 2 X5R 2 X5R 2 CERM
01005 01005 01005 402
AB23 AR8
AB25 AR11 R0607
AB27 AR14 35 =PP1V2_HSIC_H4 0.00 2
45 PP1V1_PLL_USB_F 1 =PP1V1_USB_H4 4 35
VOLTAGE=1.1V
AC3 AR17 1 C0632 1 C0633 1 C0634 1 C0635 MIN_LINE_WIDTH=0.2MM
0%
1/32W
AC8 AR19 0.01UF 0.01UF 0.01UF 0.01UF
C NET_SPACING_TYPE=PWR MF
C
HSIC0_VDD121 P29
HSIC0_VDD122 P31
HSIC0_DVDD N31
HSIC1_VDD121 K30
HSIC1_VDD122 J30
HSIC1_DVDD H32
V33
U33
T33
R33
P33
N33
MIPI0D_VDD11_PLL F27
MIPI1D_VDD11_PLL F30
U29
L30
R28
M28
PLL_USB_AVDD11 M33
AC10 AR34
10%
6.3V
2 X5R
10%
6.3V
2 X5R
10%
6.3V
2 X5R
10%
6.3V
2 X5R
MAX_NECK_LENGTH=3MM
1 C0615 01005
0.01UF
AC18 AR35 01005 01005 01005 01005 10%
PLL0_AVDD11
PLL1_AVDD11
PLL2_AVDD11
PLL3_AVDD11
PLL4_AVDD11
PLL5_AVDD11
6.3V
USB_DVDD
USB_VDD330
AC20 B1 2 X5R
01005
AC22 B2
AC24 B4
AC28 B9 MLB
10MA
AC32 B12
AC34 B15 BB
7MA 7MA
2.5MA EACH 28MA
R0652
K35 34MA 34MA 0.00 2
AD2 B34 42 30 BI HSIC0_BB_DATA1 HSIC0_DATA1 WDOG AP29 AP_WDOG 1 RST_PMU_IN OUT 37 45
2.5MA
42 30 BI HSIC0_BB_STB1 L35 HSIC0_STB1 0%
AD8 VSS VSS B35 OMIT 14MA 1/32W 01005
46 42 NC_HSIC0_DATA2 K33 HSIC0_DATA2 MF
AD9 C7 JTAGSEL
AD11 C10 0 - PARALLEL
WLAN 46 42 NC_HSIC0_STB2 L33 HSIC0_STB2 U0600 42 XTAL_24M_I
AD19 C13 1 - DAISY CHAIN (FOR USE WITH 5-WIRE JTAG) 40 15
42 BI HSIC1_WLAN_DATA1 H35 HSIC1_DATA1 H4G XI0 W35
HSIC1_WLAN_STB1 J35 FCBGA
2
AD21 C16 PER RADAR #6755237 42 40 15 BI HSIC1_STB1 R0650 CRITICAL
35 10 7 4 =PP1V8_H4
10 7 4 =PP1V8_H4 NC_HSIC1_DATA2 H33 HSIC1_DATA2 (1 OF 12)
AD23 C30 35 46 42
1.00M Y0602
DEVELOPMENT_JTAG_TAP 42 NC_HSIC1_STB2 J33 HSIC1_STB2 1% MF
AD25 C31 010051/32W SM-2
R0620 R0608 46
R0651 24.000MHZ-16PF-60PPM
1
AD27 C32 100K 2 100K 2
1 1 10 JTAG_AP_SEL AK29 JTAG_SEL 22
AD29 C33 5% MF XO0 Y35 42 XTAL_24M_O 1 2 1 3
5% 1/32W 01005 46 NC_JTAG_AP_TRTCK AM27 JTAG_TRTCK
AE1 D3 1/32W 01005 5% 24M_O
45 42 10 IN JTAG_AP_TRST_L AR27 JTAG_TRST* 1/32W 42 2 4
AE8 D5
AE9 D8
R0621 42 10 OUT JTAG_AP_TDO AP30 JTAG_TDO
MF
01005 1 C0650 1 C0651
100K 2 AN30 22PF 22PF
1 42 10 JTAG_AP_TDI JTAG_TDI
AE10 D11 5% 5%
5% JTAG_AP_TMS AJ27 16V 16V
AE18 D14
42 27 JTAG_TMS 2 CERM 2 CERM
1/32W 01005
42 27 JTAG_AP_TCK AN29 JTAG_TCK USB_DP0 U35 USB_DK_D0_P 27 42
01005 01005
AE20 D17
AE22 D30
R0622 USB_DM0 T35 USB_DK_D0_N 27 42
1
100K 2 AH27 TESTMODE N34
10 IN AP_TESTMODE USB_DP1 NC_USB_D1_P 42 46
AE24 D33
B AE26
AF3
E1
E10
5%
1/32W 01005
M31 FUSE1_FSRC
USB_DM1 M34 NC_USB_D1_N 42 46
B
USB11_DP0 T34 USB11_MUX_D0_P 11 42
AF8 E21 35 4 =PP3V3_USB_H4
10 AP_TST_STPCLK AR28 TST_STPCLK USB11_DM0 R34 USB11_MUX_D0_N 11 42
AF9 E22 OUT
TP_AP_TST_CLKOUT AR29 TST_CLKOUT USB11_DP1 N35 NC_USB11_D1_P 42 46 PPVBUS_USB 36 45
AF27 E24
USB11_DM1 P35 NC_USB11_D1_N 42 46
AF30 E25 1 1
AF32 E26
R0640 10 OUT AP_FAST_SCAN_CLK AR33 FAST_SCAN_CLK R0609
10K 100K
AF34 E27 1% USB_ANALOGTEST0 R30 NC_USB_ANALOGTEST0 46 5%
1/32W AN28 HOLD_RESET 1/32W
AG2 E28 MF 10 IN AP_HOLD_RESET USB_ANALOGTEST1 J28 NC_USB_ANALOGTEST1 46 MF
2 01005 2 01005
AG8 E29 45 37 30 27 IN RST_AP_L
45 RST_AP_1V8_L AR30 RESET* USB_VBUS0 T30 USB_AP_VBUS0
AG9 E30 3.16V
AH1 E33 USB_VBUS1 J32 USB_AP_VBUS1 IN 10
1 2
AH8 F2 R0641 GDZ-0201
GDZT2R5.1B
100K W6 CFSB0 USB_ID0 T31 NC_USB_ID0 46
AH9 F5
AH10 F16
1%
1/32W AR32 CFSB1 USB_ID1 K32 NC_USB_ID1 46 1 DZ0600
MF
USB_BRICKID0 T28 USB_BRICKID OUT
AH11 F17 2 01005 37
L6 DDR0_CKEIN USB_BRICKID1 K31 NC_USB_BRICKID1 46
AH12 F21
1.75V F9 DDR1_CKEIN
AH17 F22
AK10 DDR2_CKEIN USB_REXT0 R31 USB_REXT0
AH22 F24 1 C0640 AF6 DDR3_CKEIN USB_REXT1 K28 USB_REXT1
1000PF
AH25 F33
R06421 10%
AH26 G3 42.2K 2 16V
X7R
1
R0612 1R0613
M32 PLL_USB_AVSS11
1% 201
AJ5 G17 1/32W 44.2 44.2
P28 HSIC0_VSS121
P30 HSIC0_VSS122
K29 HSIC1_VSS121
J29 HSIC1_VSS122
MF 1% 1%
PLL0_AVSS11
PLL1_AVSS11
PLL2_AVSS11
PLL3_AVSS11
PLL4_AVSS11
PLL5_AVSS11
AJ13 G18
USB_VSSA0
USB_VSSAC
01005 2 1/20W 1/20W
N30 HSIC0_DVSS
H31 HSIC1_DVSS
MIPI_VSS
USB_DVSS
AJ20 G19 MF MF
AP_DDR1_CKEIN_1V2 2 201 2 201
AJ29 G20 1.16V
AJ32 G21
A R06431 SYNC_MASTER=MIKE SYNC_DATE=N/A A
PAGE TITLE
82.5K
V32
U32
T32
R32
P32
N32
H24
H25
H26
H27
H28
H29
U28
L31
T29
L28
R29
L29
1%
1/32W
MF
AP: MAIN
01005 2 DRAWING NUMBER SIZE

REVISION
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OMIT
U0600
H4G
OMIT FCBGA
R0700 U0600 (2 OF 12)
33.2 H4G 37 28 5 HOME_EMI_L AJ14 GPIO0 EHCI_PORT_PWR0 AG26 GPIO40_BRD_REV0 10
D
1%
1/32W
MF
FCBGA
(3 OF 12)
37 24 5
IN
IN ONOFF_L AK15
AL16
GPIO1 EHCI_PORT_PWR1 AE15 GPIO41_BRD_REV1
IN
IN 10 D
01005
AR26 AJ23 42 30 IN HSIC_BB_RDY GPIO2 EHCI_PORT_PWR2 AE16 GPIO42_BRD_REV2 IN 10
42 19 OUT I2S0_ASP_MCK_R 1 2 42 I2S0_ASP_MCK I2S0_MCK I2C0_SCL I2C0_SCL_1V8 BI 10 19 22 37 42
TO CHARLESTON, CODEC AND PMU 46 NC_AP_GPIO3 AG14 GPIO3
42 19 OUT I2S0_ASP_BCLK AG24 I2S0_BCLK I2C0_SDA AK23 I2C0_SDA_1V8 OUT 10 19 22 37 42
37 IN IRQ_PMU_L AP19 GPIO4 TMR32_PWM0 AD16 NC_AP_GPIO185 46
42 19 OUT I2S0_ASP_LRCK AP26 I2S0_LRCK
CODEC ASP 15 PM_BT_WAKE AH13 GPIO5 TMR32_PWM1 AD14 NC_AP_GPIO186 46
I2S0_ASP_DIN AK25 AN24 I2C1_SCL_1V8 OUT
42 19 IN I2S0_DIN I2C1_SCL BI 10 25 42
AH16
AL25 AR25 TO SENSOR BOARD 19 IN IRQ_CODEC_L GPIO6 TMR32_PWM2 AC12 TP_LED_STROBE_EN
42 19 OUT I2S0_ASP_DOUT I2S0_DOUT I2C1_SDA I2C1_SDA_1V8 OUT 10 25 42
46 NC_AP_GPIO7 AE13 GPIO7
46 NC_AP_GPIO8 AE12 GPIO8
46 NC_I2S1_MCK AC15 I2S1_MCK I2C2_SCL AH21 I2C2_SCL_3V0 BI 25 42
TO SENSOR BOARD (ALS) 30 5 OUT PM_RADIO_ON AH15 GPIO9 UART0_RXD AH14 UART0_AP_RXD IN 15 42
46 NC_I2S1_BCLK AC17 I2S1_BCLK I2C2_SDA AK21 I2C2_SDA_3V0 OUT 25 42 TO DOCK MUX
45 30 RST_DET_L AG17 GPIO10 UART0_TXD AG15 UART0_AP_TXD 15 42
NC_I2S1_LRCK AC14 IN OUT
NOT USED 46 I2S1_LRCK AD13
46 NC_AP_GPIO11 GPIO11
46 NC_I2S1_DIN AC16 I2S1_DIN SWI_DATA AC13 NC_SWI_AP 46 NOTE FOR GPIO12:
42 30 IN SPI2_IPC_SRDY AK17 GPIO12 UART1_CTSN AP23 UART1_BB_CTS_L IN 30 42
46 NC_I2S1_DOUT AF26 I2S1_DOUT - BB_DIAGS_READY (RADAR #9179861)
46 NC_AP_GPIO13 AE14 GPIO13 UART1_RTSN AL21 UART1_BB_RTS_L 30 42
OUT
DWI_CLK AN25 DWI_AP_CLK OUT 37 42 - BB -> H4G AL17 TO BB USART
24 IN AUD_VOL_DOWN_L GPIO14
46 NC_I2S2_MCK AK27 I2S2_MCK DWI_DI AM24 DWI_AP_DI IN 37 42
45 30 15 GSM_TXBURST_IND AF17 GPIO15 UART1_RXD AG21 UART1_BB_RXD 30 42
AF24 IN IN
42 19 15 OUT I2S2_VSP_BCLK I2S2_BCLK DWI_DO AG23 DWI_AP_DO OUT 37 42
AL18
AN26 46 NC_BOARD_ID_3 GPIO16 UART1_TXD AF21 UART1_BB_TXD OUT 30 42
42 19 15 OUT I2S2_VSP_LRCK I2S2_LRCK AK18
CODEC VSP & BT
I2S2_VSP_DIN AG25 26 5 OUT IRQ_GYRO_INT2 GPIO17
42 19 15 IN I2S2_DIN AJ18
AM26 10 IN BOOT_CONFIG_0 GPIO18 UART2_CTSN U5 SRL_L IN 5 24 37
42 19 15 OUT I2S2_VSP_DOUT I2S2_DOUT AD12
AL27 46 NC_AP_GPIO19 GPIO19 UART2_RTSN T7 RST_BB_L OUT 30 45
SDIO0_CLK NC_SDIO0_WL_CLK 46
AH18
24 IN AUD_VOL_UP_L GPIO20
46 NC_I2S3_MCK AP27 I2S3_MCK SDIO0_CMD AR31 NC_SDIO0_WL_CMD 46
18 IRQ_GRAPE_HOST_INT_L AF18 GPIO21 UART2_RXD U8 NC_UART2_RXD 46
I2S3_XSP_BCLK AN27 AK28 NC_SDIO0_WL_DATA<0> OUT
42 19 OUT I2S3_BCLK SDIO0_DATA0 46
AM18
AF25 AL28 37 5 OUT PM_KEEPACT GPIO22 UART2_TXD T5 NC_UART2_TXD 46
42 19 OUT I2S3_XSP_LRCK I2S3_LRCK SDIO0_DATA1 NC_SDIO0_WL_DATA<1> 46
CODEC XSP NOTE FOR GPIO24: 30 BB_EMERGENCY_DWLD AN18 GPIO23
I2S3_XSP_DIN AK26 AM29 NC_SDIO0_WL_DATA<2> OUT
42 19 IN I2S3_DIN SDIO0_DATA2 46
AN19
AL26 AM30 - AP_MODEM_WAKE (RADAR #9179861) 30 IN IPC_GPIO_X26 GPIO24 UART3_CTSN AG22 UART3_BT_CTS_L IN 15 42
42 19 OUT I2S3_XSP_DOUT I2S3_DOUT SDIO0_DATA3 NC_SDIO0_WL_DATA<3> 46
AG18
- H4G -> BB 10 IN BOOT_CONFIG_1 GPIO25 UART3_RTSN AJ21 UART3_BT_RTS_L OUT 15 42
39 5 FORCE_DFU AP20 GPIO26

NC_AP_GPIO216 AG27 SPDIF IN TO BT UART
46
AN20 UART3_RXD AR24
C 10 BOARD_ID_2 U6 SPI0_MISO SPI3_MISO AL30 NC_SPI3_MISO 46
5
10
OUT
IN
DFU_STATUS
BOOT_CONFIG_2 AR20
GPIO27
GPIO28 UART3_TXD AR23
UART3_BT_RXD
UART3_BT_TXD
IN
OUT
15 42
15 42
C
IN BOOT_CONFIG_3 AR21
W5 AL29 10 IN GPIO29
10 IN BOARD_ID_1 SPI0_MOSI SPI3_MOSI NC_SPI3_MOSI 46
42 15 5 HSIC_WLAN_RDY AP21 GPIO30 UART4_CTSN Y6 NC_UART4_CTS_L 46
BOARD_ID_0 T6 AN32 IN
10 IN SPI0_SCLK SPI3_SCLK NC_SPI3_SCLK 46
AK19
W8 AP33 46 NC_AP_GPIO31 GPIO31 UART4_RTSN Y7 NC_UART4_RTS_L 46
46 NC_SPI_FLASH_CS_L SPI0_SSIN SPI3_SSIN NC_SPI3_CS_L 46
26 OUT IRQ_PROX_INT_L
AN21 GPIO32
AH19 UART4_RXD W7
AF20 AF23 NEW GPIO FOR J2. FILE A RADAR 26 IN IRQ_GYRO_INT1 GPIO33 NC_UART4_RXD 46
42 17 IN SPI1_GRAPE_MISO SPI1_MISO SPI2_MISO SPI2_IPC_MISO IN 30 42
AG19
AF19 AL23 42 5 OUT HSIC_HOST_READY_WL GPIO34 UART4_TXD Y5 NC_UART4_TXD 46
42 17 OUT SPI1_GRAPE_MOSI SPI1_MOSI SPI2_MOSI SPI2_IPC_MOSI OUT 30 42
NC_AP_GPIO35 AJ19
TO GRAPE AG20 AH23 TO BB 46 GPIO35
42 17 OUT SPI1_GRAPE_SCLK SPI1_SCLK SPI2_SCLK SPI2_IPC_SCLK OUT 30 42
AR22
3.0V IO AM21 AM23 26 IN IRQ_ACCEL_INT1_L GPIO36 UART5_RTXD AL22 BATTERY_SWI OUT 34 37
42 17 OUT SPI1_GRAPE_CS_L SPI1_SSIN SPI2_SSIN HSIC_HOST_RDY OUT 5 30 42
AL20
25 IN IRQ_ALS_INT_L GPIO37
AJ16 TP_THERM_TEST_OUT AM20 UART6_CTSN U9
THERM_TEST_OUT 26 IN IRQ_ACCEL_INT2_L GPIO38 NC_UART6_CTSN 46
AK16 THERM_RES_EXT AN22 UART6_RTSN V6
THERM_RES_EXT 20 OUT AUD_SPKRAMP_MUTE_L GPIO39 NC_UART6_RTSN 46
AF16 1
VDDA18_TS R0720
AG16 100K AN31 GPIO_3V0 UART6_RXD U7
VSSA18_TS 1 11 OUT PORT_DOCK_VIDEO_AMP_EN UART6_WLAN_RXD IN 15 42
R1030 5%
1/20W 46 NC_AP_GPIO3V1 AP32 GPIO_3V1 UART6_TXD V7 UART6_WLAN_TXD OUT 15 42
100K MF
1% 2 201
1/32W
MF
2 01005
R1180
PP1V8_VDDA18_TS 1
0.00 2 =PP1V8_VDDA18_TS
45 35
0%
1/32W
MF
01005
1 C1188
0.01UF
B 10%
6.3V
2 X5R
B
01005 PM_KEEPACT 5 37
IRQ_GYRO_INT2 5 26
FORCE_DFU 5 39
DEFAULT IS TO TIE HSIC_HOST_READY TO BOTH DEVICES
DFU_STATUS 5
BUT OPTION IS HERE IN CASE THEY NEED TO BE SEPARATE
PM_RADIO_ON 5 30
NOSTUFF
R0730 1
R0711 1
R0712 1
R0713 1
R0714 1
R0715
0.00 2
42 30 5 HSIC_HOST_RDY 1 100K 100K 100K 100K 100K
35 9 =PP1V8_VDDIOD_H4 5% 5% 5% 5% 5%
0% 1/20W 1/32W 1/20W 1/20W 1/20W
1/32W MF MF MF MF MF
MF
01005 HSIC_HOST_READY_WLAN 15 42 NOSTUFF 2 201 2 01005 2 201 2 201 2 201
R0731 R07221
HSIC_HOST_READY_WL 1
0.00 2 100K
42 5 1%
1/20W
0% MF
1/32W 201 2
MF
01005
R08851
100K 42 15 5 HSIC_WLAN_RDY
5%
1/20W
MF
201 2
R0708
=PP1V8_S2R_MISC 1
220K 2
39 35 27 5
5%
1/20W
MF
201
37 28 5 HOME_EMI_L
A 35 =PP1V8_ALWAYS 1
R0709
220K 2 SYNC_MASTER=JOE SYNC_DATE=N/A A
PAGE TITLE
5%
1/20W
MF
AP: I/Os
ONOFF_L 201 DRAWING NUMBER SIZE
37 24 5

R0710 REVISION
220K 2 R
39 35 27 5 =PP1V8_S2R_MISC 1 10.0.0
5%
1/20W
MF THE INFORMATION CONTAINED HEREIN IS THE
SRL_L 201 PROPRIETARY PROPERTY OF APPLE INC.
37 24 5
7 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
45 9 6 PPIO_NAND_H4
G22 OMIT M35
G23 U0600 P1 1 1 1 45 9 6 PPIO_NAND_H4
G30 H4G P8
R0832 R0836 R0831 1R0834 NOSTUFF NOSTUFF NOSTUFF NOSTUFF
FCBGA 100K 100K 100K 100K 1
H1 P9 5%
1/32W
5%
1/32W
5%
1/32W
5%
1/32W R0800 1R0801 1
R0802 1
R0803
H4 P11 MF MF MF MF 100K 100K 100K 100K
(12 OF 12) 2 01005 2 01005 2 01005 2 01005 5% 5% 5% 5%
1/32W 1/32W 1/32W 1/32W
H8 P13 MF MF MF MF
H9 P15 44 12 6 FMI1_CE0_L 2 01005 2 01005 2 01005 2 01005
H10 P17 44 12 6 FMI1_CE1_L
44 12 6 FMI0_WE_L
44 12 6 FMI0_CE0_L
D
H11
H12
P19
P21 44 12 6 FMI0_CE1_L 44 12 6
44 12 6
FMI0_RE_N
FMI1_WE_L
D
H13 P23 44 12 6 FMI1_RE_N
H14 P25
44 12 6 FMI0_ALE
H15 P27
44 12 6 FMI0_CLE
H16 R2
44 12 6 FMI1_ALE
H17 R8
44 12 6 FMI1_CLE
H18 R10
H19 R12 NOSTUFF NOSTUFF NOSTUFF NOSTUFF
H20 R14 1 1 1
H21 R16
R0810 R0811 R0812 1R0813
100K 100K 100K 100K
5% 5% 5% 5%
H22 R18 1/32W 1/32W 1/32W 1/32W
H23 R20 MF MF MF MF
2 01005 2 01005 2 01005 2 01005
H30 R22
H34 R24
J2 R26
J8 P34
J9 T3
J10 T9
J11 T11
J12 T13
J14 T15
J16 T17
J18 T19
J20 T21
J22 T23 35 28 =PP3V0_IO_MISC
J24 T25
C J26
J31
T27
R35
C
J34 U1
K3 U10 1
K8 U12
R0804
100K
OMIT 5%
K9 U14 U0600 1/32W
MF
K10 U16 H4G 2 01005 FMI2-3_CEN IS 3.0V
K11 U18 FCBGA
(4 OF 12)
K13 U20
44 12 6 OUT FMI0_CE0_L AH31 FMI0_CEN0 FMI2_CEN0 AE35 SPK_ID IN 20
K15 U22
44 12 6 OUT FMI0_CE1_L AF31 FMI0_CEN1 FMI2_CEN1 AB28 NC_FMI2_CE1_L 46
K17 VSS VSS U24
46 NC_FMI0_CE2_L AD28 FMI0_CEN2 FMI2_CEN2 AA28 NC_FMI2_CE2_L 46
K19 U26
46 NC_FMI0_CE3_L AG29 FMI0_CEN3 FMI2_CEN3 AB30 NC_FMI2_CE3_L 46
K21 U30
46 NC_FMI0_CE4_L Y29 FMI0_CEN4 FMI2_CEN4 AE28 PM_LCDVDD_PWREN OUT 16 NEW GPIO FOR J2. FILE A RADAR
K23 U31
46 NC_FMI0_CE5_L AH28 FMI0_CEN5 FMI2_CEN5 AF28 NC_FMI2_CE5_L 46
K25 V9
46 NC_FMI0_CE6_L AG28 FMI0_CEN6 FMI2_CEN6 AA29 RST_GRAPE_L OUT 17 45
K27 V11 CHECK WITH GRAPE ON VOLTAGE FOR THESE TWO SIGNALS
46 NC_FMI0_CE7_L AM31 FMI0_CEN7 FMI2_CEN7 AB31 GRAPE_FW_DNLD_EN_L OUT 17
K34 V13
L32 V15
44 12 BI FMI0_AD<0> AG35 FMI0_IO0 FMI2_IO0 AC31 NC_FMI2_AD<0> 46
L1 V17
44 12 BI FMI0_AD<1> AF35 FMI0_IO1 FMI2_IO1 AB33 NC_FMI2_AD<1> 46
L4 V19
44 12 BI FMI0_AD<2> AH35 FMI0_IO2 FMI2_IO2 AC35 NC_FMI2_AD<2> 46
L8 V21
44 12 BI FMI0_AD<3> AH33 FMI0_IO3 FMI2_IO3 AE34 NC_FMI2_AD<3> 46
L10 V23
44 12 FMI0_AD<4> AG31 FMI0_IO4 FMI2_IO4 AD34 NC_FMI2_AD<4> 46
L12 V25 BI
44 12 BI FMI0_AD<5> AG32 FMI0_IO5 FMI2_IO5 AD32 NC_FMI2_AD<5> 46
L14 V27
44 12 BI FMI0_AD<6> AG34 FMI0_IO6 FMI2_IO6 AD35 NC_FMI2_AD<6> 46
L16 V29
44 12 FMI0_AD<7> AH32 FMI0_IO7 FMI2_IO7 AD31 NC_FMI2_AD<7> 46
L18 U34 BI
B L20
L22
V35
W1 44 12 6 OUT FMI0_ALE AE32
AF33
FMI0_ALE FMI2_ALE AB34
AB32
NC_FMI2_ALE 46 B
44 12 6 OUT FMI0_CLE FMI0_CLE FMI2_CLE NC_FMI2_CLE 46
L24 W3
44 12 6 OUT FMI0_WE_L AH34 FMI0_WEN FMI2_WEN AB35 NC_FMI2_WE_L 46
L26 W10
44 12 6 OUT FMI0_RE_N AE33 FMI0_REN FMI2_REN AD33 NC_FMI2_RE_L 46
M2 W12
44 12 OUT FMI0_DQS_P AG33 FMI0_DQS FMI2_DQS AC33 NC_FMI2_DQS 46
M3 W14
M8 W16
44 12 6 FMI1_CE0_L AJ33 FMI1_CEN0 FMI3_CEN0 W31 NC_FMI3_CE0_L 46
M9 W18 OUT
44 12 6 FMI1_CE1_L AN33 FMI1_CEN1 FMI3_CEN1 W28 NC_FMI3_CE1_L 46
M11 W20 OUT
46 NC_FMI1_CE2_L AD30 FMI1_CEN2 FMI3_CEN2 W29 NC_FMI3_CE2_L 46
M13 W22
46 NC_FMI1_CE3_L AE30 FMI1_CEN3 FMI3_CEN3 V30 NC_FMI3_CE3_L 46
M15 W24
46 NC_FMI1_CE4_L AJ31 FMI1_CEN4 FMI3_CEN4 AG30 NC_FMI3_CE4_L 46
M17 W26
46 NC_FMI1_CE5_L AJ30 FMI1_CEN5 FMI3_CEN5 AC30 NC_FMI3_CE5_L 46
M19 W34
46 NC_FMI1_CE6_L AL31 FMI1_CEN6 FMI3_CEN6 AH30 NC_FMI3_CE6_L 46
M21 Y9
46 NC_FMI1_CE7_L AK31 FMI1_CEN7 FMI3_CEN7 AE31 NC_FMI3_CE7_L 46
M23 Y11
M25 Y13
44 12 BI FMI1_AD<0> AL32 FMI1_IO0 FMI3_IO0 AA34 NC_FMI3_AD<0> 46
M27 Y15
44 12 BI FMI1_AD<1> AN35 FMI1_IO1 FMI3_IO1 W33 NC_FMI3_AD<1> 46
M30 Y17
44 12 FMI1_AD<2> AK32 FMI1_IO2 FMI3_IO2 AA33 NC_FMI3_AD<2> 46
L34 Y19 BI
44 12 BI FMI1_AD<3> AK33 FMI1_IO3 FMI3_IO3 V34 NC_FMI3_AD<3> 46
N3 Y21
44 12 BI FMI1_AD<4> AL33 FMI1_IO4 FMI3_IO4 AA30 NC_FMI3_AD<4> 46
N8 Y23
44 12 BI FMI1_AD<5> AK34 FMI1_IO5 FMI3_IO5 V31 NC_FMI3_AD<5> 46
N10 Y25
44 12 BI FMI1_AD<6> AM33 FMI1_IO6 FMI3_IO6 W32 NC_FMI3_AD<6> 46
N12 Y27
44 12 BI FMI1_AD<7> AJ35 FMI1_IO7 FMI3_IO7 Y30 NC_FMI3_AD<7> 46
N14 Y28
N16 Y31
44 12 6 OUT FMI1_ALE AN34 FMI1_ALE FMI3_ALE Y33 NC_FMI3_ALE 46
N18 Y34
FMI1_CLE AK35 W30 NC_FMI3_CLE
A N20
N22
44 12 6
44 12 6
OUT
OUT FMI1_WE_L AM35
FMI1_CLE
FMI1_WEN
FMI3_CLE
FMI3_WEN AA32 NC_FMI3_WE_L
46
46 SYNC_MASTER=MIKE SYNC_DATE=N/A A
44 12 6 FMI1_RE_N AL35 FMI1_REN FMI3_REN AA31 NC_FMI3_RE_L 46
PAGE TITLE
N24 OUT
N26 44 12 OUT FMI1_DQS_P AL34 FMI1_DQS FMI3_DQS Y32 NC_FMI3_DQS 46 AP: NAND
DRAWING NUMBER SIZE

REVISION
R
CHECK CONNECTION FOR VSSA18_TS

10.0.0
8 OF 157
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
R0910
1
0 2
45 PP1V8_DP_AVDD_AUX =PP1V8_DP_H4 35
5%
1 C0927 1 C0926 1 C0925 1 C0924 1/20W
MF
1 C0923
0.22UF 0.22UF 0.22UF 56PF 201 56PF
20% 20% 20% 5% 5%
6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 NP0-C0G 2 NP0-C0G
402 402 402 01005 01005
35 9 =PP3V0_IO_H4
=PP1V1_DP_PAD_DVDD_H4 35
1 C0953 D
D 0.01UF
10%
6.3V
1 C0909
0.1UF
10%
2 X5R 6.3V
35 =PP1V1_MIPI_H4 01005 2 X5R
201
1 C0935 1 C0908 1 C0903 R0911
1UF 0.1UF 0.1UF PP1V8_EDP_AVDD_AUX 1
0 2 =PP1V8_EDP_H4
45 35
10% 10% 10%
2 6.3V 2 6.3V 2 6.3V 5%
CERM
402
X5R
201
X5R
201 35 7 =PP3V0_VIDEO_H4
1 C0934 1 C0933 1 C0932 1 C0931 1/20W
MF
1 C0930
0.22UF 0.22UF 0.22UF 56PF 201 56PF
20% 20% 20% 5% 5%
6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 NP0-C0G 2 NP0-C0G
=PP1V8_MIPI_H4 35
1 C0951 1 C0952 402 402 402 01005 01005
1UF 0.01UF
10% 10%
45 PP0V4_MIPI1D
VOLTAGE=0.4V
1 C0907 6.3V
2 CERM
6.3V
2 X5R
MIN_LINE_WIDTH=0.2MM 0.1UF 402 01005 VOLTAGE=1.8V
MIN_NECK_WIDTH=0.1MM 10% MIN_LINE_WIDTH=0.2MM =PP1V1_EDP_PAD_DVDD_H4
6.3V
2 X5R FL0910 VOLTAGE=1.8V MIN_NECK_WIDTH=0.1MM
35
MAX_NECK_LENGTH=3MM 201 240-OHM-0.2A-0.8-OHM MIN_LINE_WIDTH=0.2MM

MAX_NECK_LENGTH=3MM
45 PP0V4_MIPI0D
VOLTAGE=0.4V
35 7 =PP3V0_VIDEO_H4 1 2 DAC_AP_COMP_FTR MAX_NECK_LENGTH=3MM 1 C0910
MIN_LINE_WIDTH=0.2MM 0201 0.1UF
MIN_NECK_WIDTH=0.1MM 10%
NET_SPACING_TYPE=PWR 2 6.3V
MIPI0D_VREG_0P4V F26
MIPI1D_VREG_0P4V F29
G24
G25
G26
G27
G28
G29
MIPI0D_VDD18 F25
MIPI1D_VDD18 F28
DAC_AVDD30A G31
DAC_AVDD30D D32
DP_PAD_AVDD_AUX D28
C26
C25
D24
D23
DP_PAD_AVDDP0 D27
DP_PAD_AVDDX B29
DP_PAD_DVDD A29
EDP_PAD_AVDD_AUX D20
B18
A18
E19
E18
EDP_PAD_AVDDP0 D19
EDP_PAD_AVDDX C21
EDP_PAD_DVDD C22
1 C0960 1 C0961 MAX_NECK_LENGTH=3MM
X5R
201
DAC_AP_OUT3 OUT 11 43
2.2NF 2.2NF DAC_AP_OUT2 11 43
10%
10V
10%
10V =PP1V8_H4
1 C0956 DAC_AP_OUT1
OUT
DP_PAD_AVDD
EDP_PAD_AVDD
2 X5R 2 X5R MIPI_VDD11 4 10 35
0.1UF OUT 11 43
201 201 10%
14MA 6.3V
1 1 1 1 2 X5R
R0930 R0931 R0932 R0933 201
1.00K 1.00K 1.00K 1.00K 1 1 1
5%
1/32W
5%
1/32W
5%
1/32W
5%
1/32W
R0955 R0956 R0957
OMIT MF MF MF MF 200 200 200
2 01005 2 01005 2 01005 2 01005 21MA 6MA 1.2MA 1% 1% 1%
U0600 4MA 332MA
2MA
5MA
172MA 5MA
1.2MA 1/20W
MF
1/20W
MF
1/20W
MF
C H4G
FCBGA
45 DAC_AP_VREF E31 DAC_VREF 5MA
OMIT 5MA
2MA
DAC_OUT3 G33
DAC_OUT2 G34
2 201 2 201 2 201
C
(6 OF 12)
DAC_AP_IREF F31 DAC_IREF U0600 DAC_OUT1 G35
46 NC_MIPI_VSYNC_H4 AD15 MIPI_VSYNC ISP0_FLASH AD17 CAM0_RESET_L 26 H4G
ISP0_PRE_FLASH AF13 TP_CAM0_1V2_VDDCORE_EN 1 C0955 1
R0950 DAC_AP_COMP E32 DAC_COMP FCBGA
(5 OF 12)
43 25 OUT MIPI0C_AP_DATA_P<0> D35 MIPI0C_DPDATA0 ISP0_SCL AK22 ISP_AP_0_SCL OUT 25 42
0.1UF 6.34K DP_HPD AL15 DP_AP_HPD IN 37 43
10% 1%
43 25 OUT MIPI0C_AP_DATA_N<0> C35 MIPI0C_DNDATA0 ISP0_SDA AF22 ISP_AP_0_SDA BI 25 42 2 6.3V
X5R 1/20W
201 MF
2 201 DP_PAD_AUXP C28 DP_AP_AUX_P OUT 28 43
43 25 OUT MIPI0C_AP_DATA_P<1> B33 MIPI0C_DPDATA1 ISP1_FLASH AF14 NC_ISP_AP_1_FLASH 46 TP_DP_AP_ANALOG_TEST F23 DP_PAD_DC_TP DP_PAD_AUXN C27 DP_AP_AUX_N OUT 28 43
43 25 OUT MIPI0C_AP_DATA_N<1> B32 MIPI0C_DNDATA1 ISP1_PRE_FLASH AE17 NC_ISP_AP_1_PRE_FLASH 46
ISP1_SCL AP24 ISP_AP_1_SCL OUT 25 42 DP_PAD_TX0P A28 DP_AP_TX_P<0> OUT 28 43
46 43 NC_MIPI0C_AP_DATA_P<2> B31 MIPI0C_DPDATA2 ISP1_SDA AN23 ISP_AP_1_SDA BI 25 42 NOTE: 0.6V ANALOG REF DP_PAD_TX0N A27 DP_AP_TX_N<0> OUT 28 43
46 43 NC_MIPI0C_AP_DATA_N<2> B30 MIPI0C_DNDATA2 AP_DP_R_BIAS E23 DP_PAD_R_BIAS

0.00 2MF R0900
SENSOR0_CLK AJ24 42 CLK_CAM_RF_R 1
0% CLK_CAM_RF 25 42 NOSTUFF 1 DP_PAD_TX1P D26 DP_AP_TX_P<1> OUT 28 43
46 43 NC_MIPI0C_AP_DATA_P<3> A31 MIPI0C_DPDATA3 SENSOR0_RST AK24

1/32W 01005
PM_REAR_CAM_SHUTDOWN 25
1 C0950 R0920 DP_PAD_TX1N D25 DP_AP_TX_N<1> OUT 28 43
A30 MIPI0C_DNDATA3 0.01UF 4.99K
46 43 NC_MIPI0C_AP_DATA_N<3> 10% 1%
0.00 2 R0940 6.3V 1/32W
SENSOR1_CLK AH24 42 CLK_CAM_FF_R 1
0% MF CLK_CAM_FF 25 42 2 X5R MF DP_PAD_TX2P B26 DP_AP_TX_P<2> OUT 28 43
1/32W 01005
43 25 MIPI0C_AP_CLK_P A33 MIPI0C_DPCLK SENSOR1_RST AL24 PM_FRONT_CAM_SHUTDOWN 25 01005 2 01005 DP_PAD_TX2N B25 DP_AP_TX_N<2> 28 43
OUT OUT
43 25 OUT MIPI0C_AP_CLK_N A32 MIPI0C_DNCLK DP LANES 2/3 ARE FOR STEVE-NOTE ONLY
MIPI1C_DPDATA0 F34 MIPI1C_AP_DATA_P<0> OUT 25 43 DP_PAD_TX3P C24 DP_AP_TX_P<3> OUT 28 43
MIPI1C_DNDATA0 E34 MIPI1C_AP_DATA_N<0> OUT 25 43 DP_PAD_TX3N C23 DP_AP_TX_N<3> OUT 28 43
MIPI1C_DPDATA1 D34 NC_MIPI1C_AP_DATA_P<1> 43 46
MIPI1C_DNDATA1 C34 NC_MIPI1C_AP_DATA_N<1> 43 46 EDP_HPD AJ15 EDP_AP_HPD IN 16 43
MIPI1C_DPCLK F35 MIPI1C_AP_CLK_P OUT 25 43 EDP_PAD_AUXP A24 EDP_AP_AUX_P OUT 16 43
B MIPI1C_DNCLK E35 MIPI1C_AP_CLK_N OUT 25 43 TP_EDP_AP_ANALOG_TEST F20 EDP_PAD_DC_TP EDP_PAD_AUXN A23 EDP_AP_AUX_N OUT 16 43
B
EDP_PAD_TX0P D22 EDP_AP_TX_P<0> OUT 16 43
NOTE: 0.6V ANALOG REF EDP_PAD_TX0N D21 EDP_AP_TX_N<0> OUT 16 43
AP_EDP_R_BIAS E20 EDP_PAD_R_BIAS

NOSTUFF 1 EDP_PAD_TX1P B22 EDP_AP_TX_P<1> OUT 16 43
1 C0957 R0921 EDP_PAD_TX1N B21 EDP_AP_TX_N<1> OUT 16 43
0.01UF 4.99K
10% 1%
1/32W
2 6.3V
X5R MF EDP_PAD_TX2P C20 EDP_AP_TX_P<2> OUT 16 43
01005 2 01005 EDP_PAD_TX2N C19 EDP_AP_TX_N<2> 16 43
OUT
EDP_PAD_TX3P A20 EDP_AP_TX_P<3> OUT 16 43
EDP_PAD_TX3N A19 EDP_AP_TX_N<3> OUT 16 43
B20 EDP_PAD_AVSS_AUX
B28 DP_PAD_AVSS_AUX
B19 EDP_PAD_AVSSP0
EDP_PAD_AVSS
B27 DP_PAD_AVSSP0
A21 EDP_PAD_AVSSX
DP_PAD_AVSS
G32 DAC_AVSS30A1
F32 DAC_AVSS30A2
D29 DP_PAD_AVSSX
A22 EDP_PAD_DVSS
D31 DAC_AVSS30D
C29 DP_PAD_DVSS
A26
A25
B24
B23
D18
C18
F19
F18
A SYNC_MASTER=JOE SYNC_DATE=01/13/2011 A
PAGE TITLE
AP: TV,DP,MIPI
DRAWING NUMBER SIZE

REVISION
R
10.0.0
TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: THE INFORMATION CONTAINED HEREIN IS THE
PART NUMBER PROPRIETARY PROPERTY OF APPLE INC.
TABLE_ALT_ITEM
132S0279 132S0154 C0960,C0961 RADAR:9624625 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
9 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DDR0_DQ<0> B14 DDR0_DQ0 DDR1_DQ0 H2 DDR1_DQ<0> DDR2_DQ<0> AB2 DDR2_DQ0 DDR3_DQ0 AP7 DDR3_DQ<0>
44 40 13
44 13
BI
BI DDR0_DQ<1> B13 DDR0_DQ1 DDR1_DQ1 H3 DDR1_DQ<1>
BI
BI
13 44
13 44
44 14
44 14
BI
BI DDR2_DQ<1> AB3 DDR2_DQ1
U0600 DDR3_DQ1 AM7 DDR3_DQ<1>
BI
BI
14 44
14 44
44 13 DDR0_DQ<2> D13 DDR0_DQ2 DDR1_DQ2 J3 DDR1_DQ<2> 13 44 44 14 DDR2_DQ<2> AC2 DDR2_DQ2

H4G DDR3_DQ2 AP8 DDR3_DQ<2> 14 44
BI BI BI FCBGA BI
44 13 DDR0_DQ<3> C12 DDR0_DQ3 DDR1_DQ3 J4 DDR1_DQ<3> 13 44 44 14 DDR2_DQ<3> AC4 DDR2_DQ3 (8 OF 12) DDR3_DQ3 AN8 DDR3_DQ<3> 14 44
BI BI BI BI
44 13 DDR0_DQ<4> D12 DDR0_DQ4 DDR1_DQ4 K2 DDR1_DQ<4> 13 44 44 14 DDR2_DQ<4> AE2 DDR2_DQ4 DDR3_DQ4 AN9 DDR3_DQ<4> 14 44
BI BI BI BI
44 13 DDR0_DQ<5> B11 DDR0_DQ5 DDR1_DQ5 L2 DDR1_DQ<5> 13 44 44 14 DDR2_DQ<5> AD3 DDR2_DQ5 DDR3_DQ5 AP10 DDR3_DQ<5> 14 44
D 44 13
BI
BI DDR0_DQ<6> C11 DDR0_DQ6
OMIT
DDR1_DQ6 K4 DDR1_DQ<6>
BI
BI 13 44 44 14
BI
BI DDR2_DQ<6> AF2 DDR2_DQ6
OMIT
DDR3_DQ6 AP11 DDR3_DQ<6>
BI
BI 14 44 D
44 13 BI DDR0_DQ<7> B10 DDR0_DQ7 U0600 DDR1_DQ7 K5 DDR1_DQ<7> BI 13 44 44 14 BI DDR2_DQ<7> AE3 DDR2_DQ7 DDR3_DQ7 AN11 DDR3_DQ<7> BI 14 44
44 13 BI DDR0_DQ<8> C9 DDR0_DQ8 H4G DDR1_DQ8 N2 DDR1_DQ<8> BI 13 44 44 14 BI DDR2_DQ<8> AG3 DDR2_DQ8 DDR3_DQ8 AN12 DDR3_DQ<8> BI 14 44
44 13 DDR0_DQ<9> D9 DDR0_DQ9 FCBGA DDR1_DQ9 P2 DDR1_DQ<9> 13 44 44 14 DDR2_DQ<9> AH2 DDR2_DQ9 DDR3_DQ9 AM10 DDR3_DQ<9> 14 44
BI BI BI BI
B8 (7 OF 12) P3 AH3 AL10
44 13 BI DDR0_DQ<10> DDR0_DQ10 DDR1_DQ10 DDR1_DQ<10> BI 13 44 44 14 BI DDR2_DQ<10> DDR2_DQ10 DDR3_DQ10 DDR3_DQ<10> BI 14 44
44 13 DDR0_DQ<11> C8 DDR0_DQ11 DDR1_DQ11 R3 DDR1_DQ<11> 13 44 44 14 DDR2_DQ<11> AF4 DDR2_DQ11 DDR3_DQ11 AP13 DDR3_DQ<11> 14 44
BI BI BI BI
44 13 BI DDR0_DQ<12> B7 DDR0_DQ12 DDR1_DQ12 U3 DDR1_DQ<12> BI 13 44 44 14 BI DDR2_DQ<12> AJ3 DDR2_DQ12 DDR3_DQ12 AP14 DDR3_DQ<12> BI 14 44
44 13 BI DDR0_DQ<13> B6 DDR0_DQ13 DDR1_DQ13 T2 DDR1_DQ<13> BI 13 44 44 14 BI DDR2_DQ<13> AJ2 DDR2_DQ13 DDR3_DQ13 AM14 DDR3_DQ<13> BI 14 44
44 40 13 BI DDR0_DQ<14> C6 DDR0_DQ14 DDR1_DQ14 U2 DDR1_DQ<14> BI 13 44 44 14 BI DDR2_DQ<14> AK3 DDR2_DQ14 DDR3_DQ14 AL14 DDR3_DQ<14> BI 14 44
44 13 DDR0_DQ<15> D7 DDR0_DQ15 DDR1_DQ15 R4 DDR1_DQ<15> 13 44 44 14 DDR2_DQ<15> AF5 DDR2_DQ15 DDR3_DQ15 AN14 DDR3_DQ<15> 14 44
BI BI BI BI
44 13 BI DDR0_DQ<16> B17 DDR0_DQ16 DDR1_DQ16 C2 DDR1_DQ<16> BI 13 44 44 14 BI DDR2_DQ<16> Y2 DDR2_DQ16 DDR3_DQ16 AP4 DDR3_DQ<16> BI 14 44
44 13 BI DDR0_DQ<17> C17 DDR0_DQ17 DDR1_DQ17 D2 DDR1_DQ<17> BI 13 44 44 14 BI DDR2_DQ<17> W2 DDR2_DQ17 DDR3_DQ17 AP3 DDR3_DQ<17> BI 14 44
44 13 DDR0_DQ<18> B16 DDR0_DQ18 DDR1_DQ18 E2 DDR1_DQ<18> 13 44 44 14 DDR2_DQ<18> Y3 DDR2_DQ18 DDR3_DQ18 AN4 DDR3_DQ<18> 14 44
BI BI BI BI
44 13 BI DDR0_DQ<19> E17 DDR0_DQ19 DDR1_DQ19 E4 DDR1_DQ<19> BI 13 44 44 14 BI DDR2_DQ<19> W4 DDR2_DQ19 DDR3_DQ19 AM4 DDR3_DQ<19> BI 14 44
44 13 BI DDR0_DQ<20> D16 DDR0_DQ20 DDR1_DQ20 E3 DDR1_DQ<20> BI 13 44 44 14 BI DDR2_DQ<20> Y4 DDR2_DQ20 DDR3_DQ20 AP5 DDR3_DQ<20> BI 14 44
44 13 DDR0_DQ<21> E16 DDR0_DQ21 DDR1_DQ21 F3 DDR1_DQ<21> 13 44 44 14 DDR2_DQ<21> AA3 DDR2_DQ21 DDR3_DQ21 AN5 DDR3_DQ<21> 14 44
BI BI BI BI
44 13 DDR0_DQ<22> C15 DDR0_DQ22 DDR1_DQ22 F4 DDR1_DQ<22> 13 44 44 14 DDR2_DQ<22> AA5 DDR2_DQ22 DDR3_DQ22 AN6 DDR3_DQ<22> 14 44
BI BI BI BI
44 13 BI DDR0_DQ<23> D15 DDR0_DQ23 DDR1_DQ23 G2 DDR1_DQ<23> BI 13 44 44 14 BI DDR2_DQ<23> AA4 DDR2_DQ23 DDR3_DQ23 AM5 DDR3_DQ<23> BI 14 44
44 13 BI DDR0_DQ<24> E6 DDR0_DQ24 DDR1_DQ24 R6 DDR1_DQ<24> BI 13 44 44 14 BI DDR2_DQ<24> AL2 DDR2_DQ24 DDR3_DQ24 AN15 DDR3_DQ<24> BI 14 44
44 13 DDR0_DQ<25> B5 DDR0_DQ25 DDR1_DQ25 T4 DDR1_DQ<25> 13 44 44 14 DDR2_DQ<25> AL3 DDR2_DQ25 DDR3_DQ25 AM15 DDR3_DQ<25> 14 44
BI BI BI BI
44 13 DDR0_DQ<26> C5 DDR0_DQ26 DDR1_DQ26 U4 DDR1_DQ<26> 13 44 44 14 DDR2_DQ<26> AL4 DDR2_DQ26 DDR3_DQ26 AP16 DDR3_DQ<26> 14 44
BI BI BI BI
44 13 DDR0_DQ<27> E5 DDR0_DQ27 DDR1_DQ27 V1 DDR1_DQ<27> 13 44 44 14 DDR2_DQ<27> AM2 DDR2_DQ27 DDR3_DQ27 AM16 DDR3_DQ<27> 14 44
BI BI BI BI
44 13 DDR0_DQ<28> C4 DDR0_DQ28 DDR1_DQ28 V2 DDR1_DQ<28> 13 44 44 14 DDR2_DQ<28> AN2 DDR2_DQ28 DDR3_DQ28 AR18 DDR3_DQ<28> 14 44
BI BI BI BI
44 13 DDR0_DQ<29> D4 DDR0_DQ29 DDR1_DQ29 V3 DDR1_DQ<29> 13 44 44 14 DDR2_DQ<29> AN3 DDR2_DQ29 DDR3_DQ29 AP17 DDR3_DQ<29> 14 44
BI BI BI BI
44 13 DDR0_DQ<30> B3 DDR0_DQ30 DDR1_DQ30 V4 DDR1_DQ<30> 13 44 44 14 DDR2_DQ<30> AL5 DDR2_DQ30 DDR3_DQ30 AN17 DDR3_DQ<30> 14 44
BI BI BI BI
44 13 DDR0_DQ<31> C3 DDR0_DQ31 DDR1_DQ31 V5 DDR1_DQ<31> 13 44 44 14 DDR2_DQ<31> AK5 DDR2_DQ31 DDR3_DQ31 AM17 DDR3_DQ<31> 14 44
BI BI BI BI
C 44 13 OUT DDR0_CA<0> G5 DDR0_CA0 DDR1_CA0 E15 DDR1_CA<0> OUT 13 44 44 14 OUT DDR2_CA<0> AL6 DDR2_CA0 DDR3_CA0 AB5 DDR3_CA<0> OUT 14 44
C
44 13 DDR0_CA<1> G6 DDR0_CA1 DDR1_CA1 F15 DDR1_CA<1> 13 44 44 14 DDR2_CA<1> AK6 DDR2_CA1 DDR3_CA1 AB6 DDR3_CA<1> 14 44
OUT OUT OUT OUT
44 13 OUT DDR0_CA<2> H5 DDR0_CA2 DDR1_CA2 F14 DDR1_CA<2> OUT 13 44 44 14 OUT DDR2_CA<2> AL7 DDR2_CA2 DDR3_CA2 AC5 DDR3_CA<2> OUT 14 44
44 13 DDR0_CA<3> H6 DDR0_CA3 DDR1_CA3 E14 DDR1_CA<3> 13 44 44 14 DDR2_CA<3> AK7 DDR2_CA3 DDR3_CA3 AC6 DDR3_CA<3> 14 44
OUT OUT OUT OUT
44 13 OUT DDR0_CA<4> J5 DDR0_CA4 DDR1_CA4 F13 DDR1_CA<4> OUT 13 44 44 14 OUT DDR2_CA<4> AL8 DDR2_CA4 DDR3_CA4 AD5 DDR3_CA<4> OUT 14 44
44 13 OUT DDR0_CA<5> M5 DDR0_CA5 DDR1_CA5 E8 DDR1_CA<5> OUT 13 44 44 14 OUT DDR2_CA<5> AL11 DDR2_CA5 DDR3_CA5 AG5 DDR3_CA<5> OUT 14 44
44 13 DDR0_CA<6> M6 DDR0_CA6 DDR1_CA6 F8 DDR1_CA<6> 13 44 44 14 DDR2_CA<6> AK11 DDR2_CA6 DDR3_CA6 AG6 DDR3_CA<6> 14 44
OUT OUT OUT OUT
44 13 OUT DDR0_CA<7> N6 DDR0_CA7 DDR1_CA7 F7 DDR1_CA<7> OUT 13 44 44 14 OUT DDR2_CA<7> AK12 DDR2_CA7 DDR3_CA7 AH6 DDR3_CA<7> OUT 14 44
44 13 DDR0_CA<8> P5 DDR0_CA8 DDR1_CA8 E7 DDR1_CA<8> 13 44 44 14 DDR2_CA<8> AL12 DDR2_CA8 DDR3_CA8 AH5 DDR3_CA<8> 14 44
OUT OUT OUT OUT
44 13 DDR0_CA<9> P6 DDR0_CA9 DDR1_CA9 F6 DDR1_CA<9> 13 44 44 14 DDR2_CA<9> AK13 DDR2_CA9 DDR3_CA9 AJ6 DDR3_CA<9> 14 44
OUT OUT OUT OUT
44 13 OUT DDR0_DM<0> E12 DDR0_DM0 DDR1_DM0 L5 DDR1_DM<0> OUT 13 44 44 14 OUT DDR2_DM<0> AD4 DDR2_DM0 DDR3_DM0 AM11 DDR3_DM<0> OUT 14 44
44 13 OUT DDR0_DM<1> E9 DDR0_DM1 DDR1_DM1 N5 DDR1_DM<1> OUT 13 44 44 14 OUT DDR2_DM<1> AG4 DDR2_DM1 DDR3_DM1 AL13 DDR3_DM<1> OUT 14 44
44 13 DDR0_DM<2> C14 DDR0_DM2 DDR1_DM2 G4 DDR1_DM<2> 13 44 44 14 DDR2_DM<2> AA6 DDR2_DM2 DDR3_DM2 AM6 DDR3_DM<2> 14 44
OUT OUT OUT OUT
44 13 OUT DDR0_DM<3> D6 DDR0_DM3 DDR1_DM3 R5 DDR1_DM<3> OUT 13 44 44 14 OUT DDR2_DM<3> AK4 DDR2_DM3 DDR3_DM3 AK14 DDR3_DM<3> OUT 14 44
44 40 13 BI DDR0_DQS_P<0> A13 DDR0_PDQS0 DDR1_PDQS0 F1 DDR1_DQS_P<0> BI 13 44 44 14 BI DDR2_DQS_P<0> AC1 DDR2_PDQS0 DDR3_PDQS0 AR6 DDR3_DQS_P<0> BI 14 44
44 40 13 DDR0_DQS_N<0> A12 DDR0_NDQS0 DDR1_NDQS0 G1 DDR1_DQS_N<0> 13 44 44 14 DDR2_DQS_N<0> AD1 DDR2_NDQS0 DDR3_NDQS0 AR7 DDR3_DQS_N<0> 14 44
BI BI BI BI
44 13 BI DDR0_DQS_P<1> A6 DDR0_PDQS1 DDR1_PDQS1 N1 DDR1_DQS_P<1> BI 13 44 44 14 BI DDR2_DQS_P<1> AK1 DDR2_PDQS1 DDR3_PDQS1 AR13 DDR3_DQS_P<1> BI 14 44
44 40 13 BI DDR0_DQS_N<1> A7 DDR0_NDQS1 DDR1_NDQS1 M1 DDR1_DQS_N<1> BI 13 44 44 14 BI DDR2_DQS_N<1> AJ1 DDR2_NDQS1 DDR3_NDQS1 AR12 DDR3_DQS_N<1> BI 14 44
44 13 BI DDR0_DQS_P<2> A16 DDR0_PDQS2 DDR1_PDQS2 C1 DDR1_DQS_P<2> BI 13 44 44 14 BI DDR2_DQS_P<2> Y1 DDR2_PDQS2 DDR3_PDQS2 AR3 DDR3_DQS_P<2> BI 14 44
44 13 DDR0_DQS_N<2> A15 DDR0_NDQS2 DDR1_NDQS2 D1 DDR1_DQS_N<2> 13 44 44 14 DDR2_DQS_N<2> AA1 DDR2_NDQS2 DDR3_NDQS2 AR4 DDR3_DQS_N<2> 14 44
BI BI BI BI
44 13 BI DDR0_DQS_P<3> A3 DDR0_PDQS3 DDR1_PDQS3 T1 DDR1_DQS_P<3> BI 13 44 44 14 BI DDR2_DQS_P<3> AN1 DDR2_PDQS3 DDR3_PDQS3 AR16 DDR3_DQS_P<3> BI 14 44
44 13 DDR0_DQS_N<3> A4 DDR0_NDQS3 DDR1_NDQS3 R1 DDR1_DQS_N<3> 13 44 44 14 DDR2_DQS_N<3> AM1 DDR2_NDQS3 DDR3_NDQS3 AR15 DDR3_DQS_N<3> 14 44
BI BI BI BI
44 13 DDR0_CK_P P4 DDR0_CK DDR1_CK F11 DDR1_CK_P 13 44 44 14 DDR2_CK_P AM13 DDR2_CK DDR3_CK AH4 DDR3_CK_P 14 44
B 44 13
OUT
OUT DDR0_CK_N N4
J1
DDR0_CKB DDR1_CKB F12
A10
DDR1_CK_N
OUT
OUT 13 44 44 14
OUT
OUT DDR2_CK_N AM12
AR10
DDR2_CKB DDR3_CKB AJ4
AF1
DDR3_CK_N
OUT
OUT 14 44 B
44 13 OUT DDR0_CKE<0> DDR0_CKE0 DDR1_CKE0 DDR1_CKE<0> OUT 13 44 44 14 OUT DDR2_CKE<0> DDR2_CKE0 DDR3_CKE0 DDR3_CKE<0> OUT 14 44
46 NC_DDR0_CKE<1> K1 DDR0_CKE1 DDR1_CKE1 A9 NC_DDR1_CKE<1> 46 46 NC_DDR2_CKE<1> AR9 DDR2_CKE1 DDR3_CKE1 AG1 NC_DDR3_CKE<1> 46
35 8 =PP1V2_S2R_H4 G11 DDR0_VDDQ_CKE DDR1_VDDQ_CKE N7 =PP1V2_S2R_H4 8 35 35 8 =PP1V2_S2R_H4 AE7 DDR2_VDDQ_CKE DDR3_VDDQ_CKE AJ12 =PP1V2_S2R_H4 8 35
44 13 OUT DDR0_CSN<0> K6 DDR0_CSN0 DDR1_CSN0 F10 DDR1_CSN<0> OUT 13 44 44 14 OUT DDR2_CSN<0> AK9 DDR2_CSN0 DDR3_CSN0 AE6 DDR3_CSN<0> OUT 14 44
46 NC_DDR0_CSN<1> J6 DDR0_CSN1 DDR1_CSN1 E13 NC_DDR1_CSN<1> 46 46 NC_DDR2_CSN<1> AK8 DDR2_CSN1 DDR3_CSN1 AD6 NC_DDR3_CSN<1> 46
45 8 PPVREF_DDR0_DQ_H4 D10 DDR0_VREF_DQ DDR1_VREF_DQ L3 PPVREF_DDR1_DQ_H4 8 45 45 8 PPVREF_DDR2_DQ_H4 AE4 DDR2_VREF_DQ DDR3_VREF_DQ AM9 PPVREF_DDR3_DQ_H4 8 45
H4G_DDR0_ZQ M4 DDR0_ZQ DDR1_ZQ E11 H4G_DDR1_ZQ H4G_DDR2_ZQ AL9 DDR2_ZQ DDR3_ZQ AE5 H4G_DDR3_ZQ
998-3125 0.5MM PT
1
R1020 1 C1020 1 C1021
1
R1021 1
R1022 1 C1023
1
R10234
240 0.22UF 240 240 1 C1022 240
1% 20% 0.22UF 1% 1% 0.22UF 1%
1/20W
6.3V
2 X5R 20% 1/20W 1/20W 0.22UF 20% 1/20W
MF 0201 2 6.3V
X5R MF MF 20%
6.3V 2 6.3V
X5R MF
2 201 0201 2 201 2 201 2 X5R 0201 2 201
0201
35 9 8 =PP1V2_VDDIOD_H4 35 9 8 =PP1V2_VDDIOD_H4
35 9 8 =PP1V2_VDDIOD_H4
35 9 8 =PP1V2_VDDIOD_H4
1 1 NOSTUFF
1
R1055 NOSTUFF R1083 NOSTUFF R1095 1
1
R1053 NOSTUFF 1 C1058 1.00K 1 C1085 1.00K C1095
1 C1057 1.00K 1% 1% 0.01UF
1.00K 0.01UF 0.01UF
A 1%
1/32W
MF
0.01UF
10%
6.3V
1%
1/32W
MF
10%
6.3V
2 X5R
1/32W
MF
2 01005
10%
6.3V
2 X5R
1/32W
MF
2 01005
10%
6.3V
2 X5R
01005
SYNC_MASTER=MIKE SYNC_DATE=N/A A
2 X5R 2 01005 01005 01005 PAGE TITLE
2 01005 01005
PPVREF_DDR2_DQ_H4 PPVREF_DDR3_DQ_H4
AP: DDR
PPVREF_DDR1_DQ_H4 8 45 8 45 DRAWING NUMBER SIZE
PPVREF_DDR0_DQ_H4
8 45
NOSTUFF VOLTAGE=0.6V
8 45
1 NOSTUFF VOLTAGE=0.6V 1 NOSTUFF VOLTAGE=0.6V
NOSTUFF VOLTAGE=0.6V 1
R1056 R1084 1 C1084 MIN_NECK_WIDTH=0.2MM R1096 1 C1096 MIN_NECK_WIDTH=0.2MM
1
R1054 1
1.00K 0.01UF
NET_SPACING_TYPE=PWR 1.00K 0.01UF
REVISION
C1054 MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM 1.00K 0.01UF
NET_SPACING_TYPE=PWR 1% 10% MAX_NECK_LENGTH=3 MM 1% 10% MAX_NECK_LENGTH=3 MM
R
10.0.0
1.00K 0.01UF NET_SPACING_TYPE=PWR 1% 10% MAX_NECK_LENGTH=3 MM 1/32W 6.3V
2 X5R 1/32W 6.3V
2 X5R
1% 10% MAX_NECK_LENGTH=3 MM 1/32W 6.3V
2 X5R MF MF NOTICE OF PROPRIETARY PROPERTY: BRANCH
1/32W 6.3V MF 01005 01005
MF 2 X5R 01005 2 01005 2 01005
01005 2 01005 THE INFORMATION CONTAINED HEREIN IS THE
2 01005 PROPRIETARY PROPERTY OF APPLE INC.
10 OF 157
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
35 9 =PPVDD_SOC_H4
U0600
U0600 35 7 =PP3V0_IO_H4 H4G =PP1V2_VDDIOD_H4
H4G FCBGA OMIT
FCBGA 1 C1142
1 C1183 1 C1184 (10 OF 12)
8 35
AA9 N23 0.22UF 0.22UF V8 VDDIO30_CFSB AA7

(9 OF 12) 56PF 20% 20%
AA11 N25 5%
6.3V 2 6.3V
X5R 2 6.3V
X5R
AF15 VDDIO30_DP_HPD AB7
2 NP0-C0G
AA13 OMIT N27 0201 0201 AJ28 VDDIO30_GPIO_3V0 160MA AC7
AA15 P10
01005
M29 AD7 C1193 1 C1191 1 C1192 1
56PF 4.3UF 10UF
AA17 P12 N28 VDDIO30_USB11 AF7 5% 20% 20%
D AB10
AB12
P14
P16 AA19
AG7
AH7
6.3V
NP0-C0G 2
01005
4V
X5R-CERM 2
0610
6.3V 2
X5R
603 D
35 =PPVDD_CPU_H4
AB14 P18 AA21 AJ7
AB16 P20 AA23 AJ8
AC9 P22 C1150 1 C1157 1 C1151 1 C1152 1 AA25 AJ9
0.01UF 10UF 56PF 56PF
AC11 P24 10% 20% 5% 5% AA27 AJ10
6.3V 2 6.3V 2 6.3V 6.3V
AD10 P26 X5R X5R NP0-C0G 2 NP0-C0G 2 AB18 AJ11
01005 603 01005 01005
AE11 R9 AB20 G7
AF10 R11 AB22 G8
AF11 R13 AB24 G9
AF12 R15 AB26 VDDIOD G10
C1195 1 C1196 C1197 1 C1190
AG10 R17 AC19
1000MA
G12 C1194 1
1 1
AG11 R19 AC21 G13 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF

20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V
AG12 R21 AC23 G14 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2
0201 0201 0201 0201 0201
AG13 R23 AC25 G15
J13 R25 C1153 1 C1154 1 C1155 1 C1156 1 C1158 1 AC26 G16
4.3UF 4.3UF 4.3UF 4.3UF 4.3UF
J15 R27 20% 20% 20% 20% 20% AC27 H7
4V 4V 4V 4V 4V
J17 T10 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 AD18 J7
0610 0610 0610 0610 0610
J19 T12 AD20 K7
=PP1V8_VDDIOD_H4 5 35
J21 T14 AD22 L7
J23 T16 AD24 M7 1 C1176 1 C1177 1 C1143
J25 T18 AD26 VDD_CPU P7 0.22UF 0.22UF
20% 20% 56PF
J27 T20 AE19 R7 6.3V 6.3V 5%
2300MA 2 X5R 2 X5R 6.3V
VDD 0201 0201 2 NP0-C0G
K12 T22 AE21
VDD 01005
K14 T24 AE23 Y8
K16 3800MA
T26
C1159 1 C1160 1 C1161 1 AE25
UART4 ?MA VDDIOD0
AH20
GPIO30-39 4MA VDDIOD1
K18 U11 0.22UF 0.22UF 0.22UF AE27 AK20
C K20 U13
20%
6.3V
X5R 2
0201
20%
6.3V
X5R 2
0201
20%
6.3V
X5R 2
0201
V18
SPI1 1MA
I2C2 1MA
VDDIOD2
VDDIOD3 AL19 =PP3V0_VDDIOD_H4 35
C
K22 U15 V20 ISP FLASH, SPI3 3MA VDDIOD4 AK30
K24 U17 V22 VDDIOD5 AH29
1 C1181 1 C1182 1 C1144
FMI2-3_CEN 2MA
0.22UF 0.22UF 56PF
K26 U19 V24 AE29 20% 20% 5%
6.3V 6.3V 6.3V
FMI0-1 88MA VDDIOD6 2 X5R 2 X5R 2 NP0-C0G
L9 U21 V26 AF29
0201 0201 01005
L11 U23 W19 AB29 NAND_IO_1V8
FMI2-3 88MA VDDIOD7
L13 U25 W21 AC29
L15 U27
C1162 1 C1163 1 C1164 1 C1165 1 C1166 1 W23 R1100
L17 V10 W25 0
VDDIO18_FUSE0_FSRC N29 1 2 =PP1V8_NAND_H4 35
L19 V12 0.22UF 0.22UF 0.22UF 0.22UF 0.22UF W27
20% 20% 20% 20% 20% VDDIO18_GPIO AJ17 5%
6.3V 6.3V 6.3V 6.3V 6.3V 1/20W
L21 V14 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 Y18 44MA AJ22 MF
0201 0201 0201 0201 0201 201
L23 V16 Y20 AJ25 NAND_IO_3V3
VDDIO18_UART1_TXD0
L25 W9 Y22 AJ26 VOLTAGE=1.8V R1101
L27 W11 Y24 MIN_LINE_WIDTH=0.2MM 0
VDDIO18_UART2_TXD T8 MIN_NECK_WIDTH=0.1MM 1 2 =PP3V3_NAND_H4 35
M10 W13 Y26 VDDIO18_XO0 V28 MAX_NECK_LENGTH=3 MM 5%
1/20W
M12 W15 MF
201
M14 W17
M16 Y10 45 6 PPIO_NAND_H4
M18 Y12
M20 Y14
1 C1170 1 C1171 1 C1172 1 C1173 1 C1174 1 C1175 1 C1145
1UF 1UF 1UF 0.22UF 0.22UF 10UF 56PF
M22 Y16 10% 10% 10% 20% 20% 20% 5%
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
M24 2 CERM 2 CERM 2 CERM 2 X5R 2 X5R 2 CERM-X5R 2 NP0-C0G
402 402 402 0201 0201 0402-1 01005
M26
N9
N11
N13
B N15
N17
B
=PP1V8_VDDIO18_H4 35
N19
N21
1 C1198 1 C1199 1 C1146
0.22UF 0.22UF
20% 20% 56PF
2 6.3V
X5R 2 6.3V
X5R
5%
6.3V
0201 0201 2 NP0-C0G
01005
35 9 =PPVDD_SOC_H4
C1101 1 C1123 1 C1102 1 C1103 1 C1121 1 C1122 1 C1124 1

C1100 1 C1117 1
10UF 10UF 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF
20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V 6.3V 4V 4V 4V 4V 4V 4V 4V
X5R 2 X5R 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2
603 603 0610 0610 0610 0610 0610 0610 0610 TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
138S0702 138S0657 C1100,C1102 QTY 17 RADAR:8837828
C1100, C1102, C1103, C1117,

C1121, C1122, C1124, C1153,
C1154, C1155, C1156, C1158,
C1191, C1615, C1621, C1715,
C1721
C1104 1 C1105 1 C1106 1 C1107 1 C1125 1 C1126 1 C1140 1 C1141 1

0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 56PF 56PF
10% 10% 10% 10% 10% 10% 5% 5%
6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 6.3V
X5R X5R X5R X5R X5R X5R NP0-C0G 2 NP0-C0G 2
01005 01005 01005 01005 01005 01005 01005 01005
PAGE TITLE
AP: POWER
DRAWING NUMBER SIZE
C1108 1 C1109 1 C1110 1 C1111 1 C1129 1 C1130 1 C1131 1 C1132 1 C1133 1 C1134 1 C1135 1 C1136 1 C1137 1 C1138 1 051-8773 D
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20%
0.22UF
20% 0.22UF Apple Inc. REVISION
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 20% R
X5R 2
0201
X5R 2
0201
X5R 2
0201
X5R 2
0201
X5R 2
0201
X5R 2
0201
X5R 2
0201
X5R 2
0201
X5R 2
0201
X5R 2
0201
X5R 2
0201
X5R 2
0201
X5R 2
0201
6.3V
X5R 2 10.0.0
0201 NOTICE OF PROPRIETARY PROPERTY: BRANCH
11 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOOT CONFIG ID
=PP1V8_H4
35 10 7 4
NOSTUFF NOSTUFF
JTAG
1 1 1 1 DEVELOPMENT_JTAG_TAP
R1200 R1201 R1202 R1203
5%
10K
1/20W
10K
5%
1/20W
10K
5%
1/20W
5%
10K
1/32W
I2C PULL-UPS R1212
0.00 2
MF MF MF MF JTAG_DAP 42 4 IN JTAG_AP_TDO 1 VIDEO_EMI_C_Y OUT 11 27 43
2 201 2 201 2 201 2 01005 0%
BOOT_CONFIG[3] (GPIO29) 5 BOOT_CONFIG_3 R1210 1/32W
100 MF
1 2 JTAG_AP_SEL OUT 4 01005
BOOT_CONFIG[2] (GPIO28) 5 BOOT_CONFIG_2
DEVELOPMENT_JTAG_TAP
D BOOT_CONFIG[1] (GPIO25) 5 BOOT_CONFIG_1 R1213

0.00 2
D
BOOT_CONFIG[0] (GPIO18) 5 BOOT_CONFIG_0 JTAG_DAP 42 4 OUT JTAG_AP_TDI 1 VIDEO_EMI_Y_PR IN 11 27 43
R1211 0%
1/32W
45 26 24 PP3V0_SENSOR_FLT 100 MF
1 2 JTAG_AP_TRST_L OUT 4 10 42 45 01005
BOOT_CONFIG[3-0] S/W READ FLOW 35 10 7 4 =PP1V8_H4 DEVELOPMENT_JTAG_TAP
1
R1214
1100 FMI0/1 2/2 CS 1. SET GPIO AS INPUT R0701 1R0702 1R0703 1R0704 1
R0705 1R0706 45 42 10 4 OUT JTAG_AP_TRST_L 1
0.00 2
VIDEO_EMI_CVBS_PB IN 11 27 43
1101 FMI0/1 4/4 CS 2. DISABLE PU AND ENABLE PD 1.00K 1.00K 1.00K 1.00K 1.00K 1.00K
5% 5% 5% 5% 5% 5% 0%
1110 FMI0/1 4/4 CS WITH TEST 3. READ 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W
MF MF MF MF MF MF MF
2 01005 2 01005 2 01005 2 01005 2 01005 2 01005
01005
42 37 22 19 5 I2C0_SDA_1V8
42 37 22 19 5 I2C0_SCL_1V8
42 25 5 I2C1_SDA_1V8 2-WIRE DAP SCAN DUMP PRODUCTION

BOARD ID 42 25 5 I2C1_SCL_1V8
35 10 7 4 =PP1V8_H4 DEVELOPMENT_JTAG DEVELOPMENT_JTAG JTAG_DAP
42 25 24 I2C2_SDA_3V0_ALS
J2A J2 DEV JTAG_DAP DEVELOPMENT_JTAG_TAP
42 25 24 I2C2_SCL_3V0_ALS
R1204 1R1205 1R1206
1
10K 10K 10K
5% 5% 5%
1/32W 1/32W 1/32W
MF MF MF
BOARD_ID[3] BOARD_ID_3 2 01005 2 01005 2 01005
BOARD_ID[2] 5 BOARD_ID_2
C BOARD_ID[3-0] S/W READ FLOW C

0000 J1 AP 1. SET GPIO AS INPUT
0001 J1 DEV 2. DISABLE PU AND ENABLE PD
0010 J2 AP 3. READ
0011 J2 DEV
0100 J2A AP
0101 J2A DEV
R1260
100K 2
1 AP_TESTMODE 4
5%
1/32W
MF
01005
NOSTUFF SHORT-01005
BOARD REVISION XW1200 1 2 AP_TST_STPCLK 4
NOSTUFF SHORT-01005
5 GPIO42_BRD_REV2
GPIO41_BRD_REV1 XW1201 1 2 AP_FAST_SCAN_CLK 4
5 NOSTUFF SHORT-01005
5 GPIO40_BRD_REV0 XW1202 1 2 AP_HOLD_RESET 4
1 1 1
NOSTUFF R1261
R1207 R1208 R1209 1
10K 2 USB_AP_VBUS1 4
10K 10K 10K
5% 5% 5% 5%
1/20W 1/20W 1/20W 1/32W
MF MF MF MF
01005
2 201 2 201 2 201
B B
BRD_REV[2-0] S/W READ FLOW
1. SET GPIO AS INPUT

000 PROTO 0
2. ENABLE PU AND DISABLE PD
001 PROTO 1 LOCAL
3. READ
010 PROTO 1 CHINA
011 PROTO 2
100 EVT
FOR REFERENCE
BOOT_CONFIG[3:0]
0000 SPI0
0001 SPI1
0010 SPI0 W/TEST
0011 SPI1 W/TEST
0100 FMI0 2CS
0101 FMI0 4CS
0110 FMI0 4CS W/TEST
0111 RESERVED
1000 FMI1 2 CS
1001 FMI1 4 CS
1010 FMI1 4CS W/TEST
A CURRENT SETTING -> 1100 FMI0/1 2/2 CS

SYNC_MASTER=ALEX SYNC_DATE=N/A A
1101 FMI0/1 4/4 CS PAGE TITLE
1110
1111
FMI0/1 4/4 CS W/TEST
RESERVED AP: MISC & ALIASES
DRAWING NUMBER SIZE

REVISION
R
10.0.0
12 OF 157
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
D D
=PP3V2_S2R_USBMUX
35
~15MA C1301 1 C1300 1

56PF 0.1UF
5% 10%
=PP3V0_VIDEO_BUF 6.3V 6.3V
35 NP0-C0G 2 X5R 2
01005 201
1 C1370
0.1UF
10%
2 6.3V
X5R
201
VA_0 C1
VA_1 C4
VDL D2
VDH E2
PORT_DOCK_VIDEO_AMP_EN IN 5 NOTE: PLACE R0960-62 NEAR U0900
JTAG_DAP
R1372 1 R1360
75
C U1300 100K
5%
1 2 VIDEO_EMI_Y_PR OUT 10 27 43
C
THS7380IZSYR 1/32W
MF
1%
1/20W
UCSP 01005 2 MF
201
CRITICAL VID_EN C3
JTAG_DAP
YIN 43 7 IN DAC_AP_OUT3 A3 CH.1_IN CH.1_OUT A2 43 BUF_Y_PR R1361
A4 75
CVBSIN 43 7 IN DAC_AP_OUT2 CH.2_IN CH.2_OUT A1 43 BUF_CVBS_PB 1 2 VIDEO_EMI_CVBS_PB OUT 10 27 43
43 7 DAC_AP_OUT1 B4 CH.3_IN CH.3_OUT B1 43 BUF_C_Y 1%

CIN IN 1/20W
MF
201
42 15 UART0_MUX_TXD D4 TX_VLOW RX_VHIGH/USB_2D+ E1 USB11_ACC_RX_P 27 42
IN OUT
E4 JTAG_DAP
42 15 OUT UART0_MUX_RXD RX_VLOW TX_VHIGH/USB_2D- D1 USB11_ACC_TX_N IN 27 42
R1362
F3 75
42 30 BI USB_BB_D_P USB_D+ USB_1D+ F2 USB11_MUX_D0_P BI 4 42 1 2 VIDEO_EMI_C_Y OUT 10 27 43
42 30 USB_BB_D_N F4 USB_D- USB_1D- F1 USB11_MUX_D0_N 4 42 1%

BI BI 1/20W
MF
SEL C2 DOCK_BB_EN 1 201
IN 37
R1315
1.00M
5%
1/32W
AGND DGND MF
1 2 01005
R1320
B2
B3
D3
E3
100K
5%
1/32W
MF
2 01005
NOTE:
DOCK_BB_EN = 1: BB USB <-> DOCK SERIAL
DOCK_BB_EN = 0: BB USB <-> H4P FS USB
H4P UART0 <-> DOCK SERIAL
B TABLE_ALT_HEAD
B
PART NUMBER
TABLE_ALT_ITEM
343S0539 343S0520 U1300 RADAR:9009078
A SYNC_MASTER=CHOPIN SYNC_DATE=12/10/2010 A
PAGE TITLE
AP: VIDEO BUFFER,BB USB MUXES

DRAWING NUMBER SIZE

REVISION
R
10.0.0
13 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R1400 NAND_IO_1V8
0
1 2 =PP1V8_NAND 35
5%
1/20W
MF
201
NAND_IO_3V3
R1401
0
1 2 =PP3V3_NAND 12 35
D 35 12 =PP3V3_NAND
5%
1/20W
D
MF 35 12 =PP3V3_NAND
201
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.2MM VOLTAGE=1.8V
MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.2MM
NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM
MAX_NECK_LENGTH=3 MM NET_SPACING_TYPE=PWR
PPVCCQ_NAND 12 45 MAX_NECK_LENGTH=3 MM
1 C1405 1 C1406 1 C1400 1 C1401 1 C1402 1 C1404 1 C1420 1 C1421 1 C1422 1 C1424 PPVCCQ_NAND 12 45
0.22UF 0.22UF 10UF 10UF 10UF 0.1UF
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
10%
6.3V
10UF 10UF 10UF 0.1UF
2 X5R 2 X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 X5R 20% 20% 20% 10%
2 6.3V 2 6.3V 2 6.3V 2 6.3V
0201 0201 0402-1 0402-1 0402-1 201 1 C1410 1 C1411 1 C1412 1 C1413 1 C1414 CERM-X5R
0402-1
CERM-X5R
0402-1
CERM-X5R
0402-1
X5R
201
0.1UF 2.2UF 10UF 0.22UF 0.22UF
10%
2 6.3V
20%
2 6.3V
20%
6.3V
20%
6.3V
20%
6.3V 1 C1425 1 C1426
1 C1430 1 C1431 1 C1432 1 C1433 1 C1434
X5R CERM 2 CERM-X5R 2 X5R 2 X5R 0.1UF 2.2UF 10UF 0.22UF 0.22UF
45 PPVDDI_NAND_U1400 201 402-LF 0402-1 0201 0201 0.22UF 0.22UF 10% 20% 20% 20% 20%
VOLTAGE=3.3V 20% 20% PPVDDI_NAND_U1410 2 6.3V
X5R 2 6.3V
CERM
6.3V
2 CERM-X5R
6.3V
2 X5R
6.3V
2 X5R
MIN_LINE_WIDTH=0.2MM 2 6.3V
X5R 2 6.3V
X5R VOLTAGE=3.3V 201 402-LF 0402-1 0201 0201
MIN_NECK_WIDTH=0.1MM MIN_LINE_WIDTH=0.2MM
1 C1451 1 C1450 NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3MM
0201 0201 1 C1471 1 C1470 MIN_NECK_WIDTH=0.1MM
1.0UF 1.0UF MAX_NECK_LENGTH=3MM
1.0UF 1.0UF 20% 20%
20% 20% 2 6.3V 2 6.3V
2 6.3V
X5R 2 6.3V
X5R
X5R
0201-MUR
X5R
0201-MUR
OB8
OC8
OD8
OE0
OF8
OA8
0201-MUR 0201-MUR
B6
F2
M6
N1
N7
G0
OB8
OC8
OD8
OE0
OF8
OA8
B6
F2
M6
N1
N7
G0
VDDI
VCC VCCQ VDDI
R1455 VCC VCCQ
G3 OMIT 1
44 12 6 BI FMI0_AD<0> IO0-0 OMIT
CE0* A5 FMI0_CE0_L FMI0_AD<0> G3 IO0-0
44 12 6 BI FMI0_AD<1> H2 IO1-0 U1400 CLE0 A3 FMI0_CLE
IN 6 44
100K
5%
44 12 6 BI
FMI0_AD<1> H2 IO1-0 U1410 CE0* A5 FMI0_CE1_L IN 6 44
R1475
FMI0_AD<2> J3 IO2-0 LGA IN 6 12 44
1/32W
44 12 6 BI
CLE0 A3 FMI0_CLE
44 12 6 BI
ALE0 C1 FMI0_ALE IN 6 12 44 MF 44 12 6 BI FMI0_AD<2> J3 IO2-0 LGA IN 6 12 44
1
K2 C1
XXNM-XGBX8-MLC-PPN1.5-ODP
44 12 6 BI FMI0_AD<3> IO3-0 2 01005 ALE0 FMI0_ALE IN 6 12 44
E3 K2 100K
XXNM-XGBX8-MLC-PPN1.5-ODP
WE0* FMI0_WE_L IN 6 12 44 44 12 6 BI FMI0_AD<3> IO3-0
L5 E3
C 44 12 6
44 12 6
BI
BI
FMI0_AD<4>
FMI0_AD<5> K6
IO4-0
IO5-0
RE0 B4
44 12 6 BI FMI0_AD<4>
FMI0_AD<5>
L5
K6
IO4-0
IO5-0
WE0* FMI0_WE_L IN 6 12 44 5%
1/32W
MF
01005 2
C
44 12 6 FMI0_AD<6> J5 IO6-0 NC 44 12 6 BI
RE0 B4
BI
RE0* C7 FMI0_RE_N IN 6 12 44 44 12 6 BI FMI0_AD<6> J5 IO6-0 NC
44 12 6 FMI0_AD<7> H6 IO7-0 RE0* C7 FMI0_RE_N 6 12 44
BI FMI0_AD<7> H6 IN
44 12 6 BI IO7-0
G1 DQS0 H4 FMI0_DQS_P IN 6 12 44
44 12 6 BI FMI1_AD<0> IO0-1 DQS0 H4 FMI0_DQS_P IN 6 12 44
J1 DQS0* F4 NC 44 12 6 BI FMI1_AD<0> G1 IO0-1
44 12 6 BI FMI1_AD<1> IO1-1 J1 DQS0* F4 NC
44 12 6 BI FMI1_AD<1> IO1-1
44 12 6 FMI1_AD<2> L1 IO2-1
BI
N3 R/B0* E5 NAND_SLOT0_RDYBSY_L 44 12 6 BI FMI1_AD<2> L1 IO2-1
44 12 6 BI FMI1_AD<3> IO3-1 N3 R/B0* E5 NAND_SLOT1_RDYBSY_L
44 12 6 BI FMI1_AD<3> IO3-1
44 12 6 FMI1_AD<4> N5 IO4-1
BI C5 FMI1_CE0_L FMI1_AD<4> N5
L7 CE1* IN 6 44 44 12 6 BI IO4-1 C5
44 12 6 BI FMI1_AD<5> IO5-1 CE1* FMI1_CE1_L IN 6 44
CLE1 C3 FMI1_CLE 6 12 44 44 12 6 FMI1_AD<5> L7 IO5-1
FMI1_AD<6> J7 IN BI C3 FMI1_CLE
44 12 6 BI IO6-1 D2 J7 CLE1 IN 6 12 44
ALE1 FMI1_ALE IN 6 12 44 44 12 6 BI FMI1_AD<6> IO6-1
44 12 6 FMI1_AD<7> G7 IO7-1 ALE1 D2 FMI1_ALE 6 12 44
BI E1 FMI1_WE_L FMI1_AD<7> G7 IN
WE1* IN 6 12 44 44 12 6 BI IO7-1 E1
WE1* FMI1_WE_L IN 6 12 44
RE1 D4 NC RE1 D4 NC
RE1* D6 FMI1_RE_N IN 6 12 44
RE1* D6 FMI1_RE_N IN 6 12 44
DQS1 M4 FMI1_DQS_P IN 6 12 44
DQS1 M4 FMI1_DQS_P IN 6 12 44
DQS1* K4 NC DQS1* K4 NC
R/B1* E7
R/B1* E7
LEAVE VREF AS TP FOR MLB
LEAVE VREF AS TP FOR MLB
VREF G5 TP_VREF_SLOT0
VREF G5 TP_VREF_SLOT1
FMI_TCKC_U1400 OA0 TCKC ZQ A1 FMI_ZQ_U1400
FMI_TCKC_U1410 OA0 TCKC ZQ A1 FMI_ZQ_U1410
FMI_TMSC_U1400 OB0 TMSC
VSS VSSQ FMI_TMSC_U1410 OB0 TMSC
1 VSS VSSQ
R1454 1
R1474
B2
F6
L3
A7
M2
OC0
OD0
OE8
OF0
G8
243
B B
B2
F6
L3
A7
M2
OC0
OD0
OE8
OF0
G8
1% 243
1/20W 1%
NOSTUFF NOSTUFF MF 1/20W
1 1 2 201 NOSTUFF NOSTUFF MF
R1452 R1453 1
R1472 1
R1473 2 201
1K 1K
5% 5% 1K 1K
1/20W 1/20W 5% 5%
MF MF 1/20W 1/20W
2 201 2 201 MF MF
2 201 2 201
TEST POINTS
DO NOT PLACE IN NAND SINGLE PCS SHIELD CAN AREA
44 12 6 FMI0_AD<0> 1 TP TP1400
44 12 6 FMI0_ALE 1 TP TP1401
44 12 6 FMI0_CLE 1 TP TP1402
44 12 6 FMI0_RE_N 1 TP TP1403
44 12 6 FMI0_WE_L 1 TP TP1404
44 12 6 FMI1_AD<0> 1 TP TP1405
44 12 6 FMI1_ALE 1 TP TP1406
44 12 6 FMI1_CLE 1 TP TP1407
44 12 6 FMI1_RE_N 1 TP TP1408
44 12 6 FMI1_WE_L 1 TP TP1409
PAGE TITLE
NAND
DRAWING NUMBER SIZE

REVISION
R
10.0.0
14 OF 157
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
44 8 DDR1_CA<0> T15 CA0_1 OMIT CA0_2 G16 DDR0_CA<0> 8 44
44 8 DDR1_CA<1> U15 CA1_1 U1600 CA1_2 G17 DDR0_CA<1> 8 44
44 8 DDR1_CA<2> U14 CA2_1 H4G-DRAM CA2_2 H17 DDR0_CA<2> 8 44
44 8 DDR1_CA<3> V14 CA3_1 XXXMB CA3_2 H18 DDR0_CA<3> 8 44

BGA
44 8 DDR1_CA<4> T13 CA4_1 CA4_2 J16 DDR0_CA<4> 8 44
SYM 1 OF 2
44 8 DDR1_CA<5> T9 CA5_1 CA5_2 N16 DDR0_CA<5> 8 44
=PP1V2_S2R_DDR
35 14 13 44 8 DDR1_CA<6> U9 CA6_1 CA6_2 N17 DDR0_CA<6> 8 44
44 8 DDR1_CA<7> U8 CA7_1 CA7_2 P17 DDR0_CA<7> 8 44

=PP1V8_S2R_DDR
35 14
1 NOSTUFF
R1605 DDR1_CA<8> V8 CA8_1 CA8_2 P18 DDR0_CA<8>
1 C1660 44 8 8 44
D 1%
2.21K
1/32W
0.01UF
10%
44 8 DDR1_CA<9> T7 CA9_1 CA9_2 R16 DDR0_CA<9> 8 44 C1601 1 C1602 1 C1603 1 C1604 1 C1605 1 A2 VDD1_0 OMIT VSS0 A16 D
MF 6.3V
2 X5R
10UF
20%
1UF
10%
1UF
10%
0.01UF
10%
0.01UF
10%
B1 VDD1_1 U1600 VSS55 A19
2 01005 01005 DDR1_CK_P U12 CK_1 CK_2 K17 DDR0_CK_P 6.3V 6.3V 6.3V 6.3V 6.3V B11 VDD1_2 H4G-DRAM VSS2 A4
44 8 8 44 X5R 2 CERM 2 CERM 2 X5R 2 X5R 2
U11 CKB_1 603 402 402 01005 01005 XXXMB
44 8 DDR1_CK_N CKB_2 L17 DDR0_CK_N 8 44
F17 VDD1_3 VSS3 A6
PPVREF_DDR0_CA 44 8 DDR1_CKE<0> V13 CKE_1 CKE_2 J18 DDR0_CKE<0> 8 44
L2 VDD1_4 BGA VSS4 B15
VDD1
13 44 45
M16 VDD1_5 SYM 2 OF 2 VSS49 C1
1 NOSTUFF VOLTAGE=0.6V T10 B9
R1606 1 C1650 MIN_NECK_WIDTH=0.2MM VDD1_6 VSS6
MIN_LINE_WIDTH=0.3MM U18
2.21K 0.01UF C11
1% 10%
MAX_NECK_LENGTH=3 MM U13 CSB_1
C1606 1 C1607 1 C1608 1 C1609 1 VDD1_7 VSS7
1/32W 6.3V
2 X5R 44 8 DDR1_CSN<0> CSB_2 J17 DDR0_CSN<0> 8 44 0.22UF 0.22UF 0.22UF 56PF V17 VDD1_8
MF 20% 20% 20% 5%
01005 6.3V 6.3V 6.3V V6 VDD1_9 VSS9 D1
2 01005 X5R 2 6.3V X5R 2 NP0-C0G 2
X5R 2 W17 D19
0201 0201 0201 01005 VDD1_10 VSS10
44 8 DDR1_DM<0> C12 DM0_1 DM0_2 K3 DDR0_DM<0> 8 44
U19 VDD1_11 VSS1 A1
44 8 DDR1_DM<1> B10 DM1_1 DM1_2 M2 DDR0_DM<1> 8 44 VSS12 E12
44 8 DDR1_DM<3> B16 DM2_1 DM2_2 G4 DDR0_DM<3> 8 44
E11 VDD2_1 VSS13 E13
=PP1V2_S2R_DDR
44 8 DDR1_DM<2> D7 DM3_1 DM3_2 T2 DDR0_DM<2> 8 44 35 14 13
E19 VDD2_2 VSS51 G5
=PP1V2_S2R_DDR
L5
35 14 13
C15 G3 C1610 1 C1611 1 C1612 1 C1613 1 M18
VDD2_3
T16
1 44 8 DDR1_DQ<0> DQ0_1 DQ0_2 DDR0_DQ<0> 8 40 44
0.22UF 0.22UF 0.22UF 0.22UF VDD2_4 VSS52
R1651 NOSTUFF 44 8 DDR1_DQ<1> D15 DQ1_1 DQ1_2 G2 DDR0_DQ<1> 8 44
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V U17 VDD2_5 VSS50 E7
2.21K X5R 2
DDR_1
DDR_2
1%
1 C1661 44 8 DDR1_DQ<2> B14 DQ2_1 DQ2_2 H5 DDR0_DQ<2> 8 44
X5R 2
0201
X5R 2
0201
X5R 2
0201 0201 T18 VDD2_6 VSS18 F16
1/32W 0.01UF DDR1_DQ<3> C14 H4 DDR0_DQ<3> V10 B19
MF 10% 44 8 DQ3_1 DQ3_2 8 44 VDD2_7 VSS48
2 01005 6.3V
2 X5R DDR1_DQ<4> D14 DQ4_1 DQ4_2 H3 DDR0_DQ<4> V16 VDD2_8 VSS20 G18
VDD2
44 8 8 44
01005
44 8 DDR1_DQ<5> E14 DQ5_1 DQ5_2 H2 DDR0_DQ<5> 8 44
V18 VDD2_9 VSS53 V1
C1615 1 C1616 C1618 1 C1619 1
VSS
PPVREF_DDR1_CA 44 8 DDR1_DQ<6> B13 DQ6_1 DQ6_2 J3 DDR0_DQ<6> 8 44 C1614 1 4.3UF
1 C1617 1 0.01UF 56PF
W5 VDD2_10 VSS22 J1
13 44 45
44 8 DDR1_DQ<7> C13 DQ7_1 DQ7_2 J2 DDR0_DQ<7> 8 44
10UF 20% 1UF 1UF 10% 5% W16 VDD2_11 VSS23 K18
NOSTUFF VOLTAGE=0.6V 20% 4V 10% 10% 10V 6.3V
1 DDR1_DQ<8> C9 N4 DDR0_DQ<8> 6.3V X5R-CERM 2 6.3V 6.3V X5R 2 NP0-C0G 2 W19 K5
R1652 1 C1652 MIN_NECK_WIDTH=0.2MM 44 8 DQ8_1 DQ8_2 8 44 X5R 2 CERM 2 CERM 2 VDD2_12 VSS24
MIN_LINE_WIDTH=0.3MM 603 0610 402 402 201 01005
2.21K 0.01UF NET_SPACING_TYPE=PWR 44 8 DDR1_DQ<9> D9 DQ9_1 DQ9_2 N3 DDR0_DQ<14> 8 40 44
W18 VDD2_13 VSS25 L18
1% 10% MAX_NECK_LENGTH=3 MM B8 P5 V19 L3
C 1/32W
MF
2 01005
6.3V
2 X5R
01005
44 8
44 8
DDR1_DQ<10>
DDR1_DQ<11> C8
DQ10_1
DQ11_1
DQ10_2
DQ11_2 P4
DDR0_DQ<10>
DDR0_DQ<11>
8 44
8 44
A3
VDD2_14
VDD2_15
VSS26
VSS27 M5 C
44 8 DDR1_DQ<12> D8 DQ12_1 DQ12_2 P3 DDR0_DQ<12> 8 44 T19 VDD2_16 VSS28 N18
44 8 DDR1_DQ<14> E8 DQ13_1 DQ13_2 P2 DDR0_DQ<13> 8 44 VSS29 N5
44 8 DDR1_DQ<13> B7 DQ14_1 DQ14_2 R4 DDR0_DQ<9> 8 44
35 14 13 =PP1V2_VDDQ_DDR H1 VDDQ27
44 8 DDR1_DQ<15> C7 DQ15_1 DQ15_2 R3 DDR0_DQ<15> 8 44 M1 VDDQ32 VSS47 A18
44 8 DDR1_DQ<24> B18 DQ16_1 DQ16_2 B2 DDR0_DQ<24> 8 44 C1623 1 C1620 1 C1621 1 C1624 1 C1625 1 C1626 1 C1622 1 W3 VDDQ31 VSS32 R18
=PP1V2_VDDQ_DDR 44 8 DDR1_DQ<25> C18 DQ17_1 DQ17_2 C2 DDR0_DQ<25> 8 44
56PF 10UF 4.3UF 0.22UF 0.22UF 0.22UF 0.01UF E1 VDDQ VSS33 R2
35 14 13
5% 20% 20% 20% 20% 20% 10%
DDR1_DQ<26> D18 DQ18_1 DQ18_2 D3 DDR0_DQ<26> 6.3V 6.3V 2 4V 6.3V 2 6.3V 2 6.3V 2 6.3V 2 U1 VDDQ1 VSS34 T1
44 8 8 44 NP0-C0G 2 X5R X5R-CERM 2 X5R X5R X5R X5R
1 DDR1_DQ<27> E18 D2 DDR0_DQ<28> 01005 603 0610 0201 0201 0201 01005 B12 T17
R1653 NOSTUFF 44 8 DQ19_1 DQ19_2 8 44 VDDQ3 VSS35
1.00K
1 C1662 44 8 DDR1_DQ<28> B17 DQ20_1 DQ20_2 E4 DDR0_DQ<27> 8 44 D4 VDDQ6 VSS36 U16
1% 0.01UF DDR1_DQ<29> D17 E3 DDR0_DQ<29> U3
1/32W 10% 44 8 DQ21_1 DQ21_2 8 44 VDDQ30
MF 6.3V
2 X5R DDR1_DQ<30> E17 DQ22_1 DQ22_2 E2 DDR0_DQ<30> A14 VDDQ23 VSS54 W2
2 01005 01005
44 8 8 44
DDR1_DQ<31> E16 F2 DDR0_DQ<31> C17 U6

DQ23_1 DQ23_2 VDDQ25 VSS39
VDDQ
44 8 8 44
44 8 DDR1_DQ<16> B6 DQ24_1 DQ24_2 T5 DDR0_DQ<16> 8 44 C19 VDDQ26 VSS40 V11

PPVREF_DDR0_DQ
13 44 45 44 8 DDR1_DQ<17> B5 DQ25_1 DQ25_2 U5 DDR0_DQ<22> 8 44 A10 VDDQ22 VSS41 V12
NOSTUFF VOLTAGE=0.6V 44 8 DDR1_DQ<18> C5 DQ26_1 DQ26_2 U4 DDR0_DQ<19> 8 44 A17 VDDQ34 VSS42 V15
1
R1654 1 C1654 MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM 44 8 DDR1_DQ<19> D5 DQ27_1 DQ27_2 U2 DDR0_DQ<18> 8 44 J5 VDDQ16 VSS43 T6
1.00K 0.01UF NET_SPACING_TYPE=PWR
DDR1_DQ<20> B4 V5 K2 V9
1% 10% MAX_NECK_LENGTH=3 MM 44 8 DQ28_1 DQ28_2 DDR0_DQ<20> 8 44 VDDQ17 VSS44
1/32W 6.3V
2 X5R
MF 44 8 DDR1_DQ<21> C4 DQ29_1 DQ29_2 V4 DDR0_DQ<17> 8 44 A8 VDDQ21 VSS45 W1
01005
2 01005 44 8 DDR1_DQ<22> B3 DQ30_1 DQ30_2 V3 DDR0_DQ<21> 8 44 N2 VDDQ19 VSS46 W4
44 8 DDR1_DQ<23> C3 DQ31_1 DQ31_2 V2 DDR0_DQ<23> 8 44 R5 VDDQ20
A13 VDDQ24
44 8 DDR1_DQS_P<0> D13 DQS0_1 DQS0_2 J4 DDR0_DQS_P<0> 8 40 44 E10 VDDQ28
44 8 DDR1_DQS_N<0> D12 DQSB0_1 DQSB0_2 K4 DDR0_DQS_N<0> 8 40 44 E15 VDDQ29
P1 VDDQ33
=PP1V2_VDDQ_DDR 44 8 DDR1_DQS_P<1> D10 DQS1_1 DQS1_2 M4 DDR0_DQS_P<1> 8 44
B 35 14 13
1
44 8 DDR1_DQS_N<1> C10 DQSB1_1 DQSB1_2 M3 DDR0_DQS_N<1> 8 40 44 35 14 13
=PP1V2_S2R_DDR F18
H16
VDDCA1 B
R1655 NOSTUFF VDDCA2
1 C1663
1.00K
1% 0.01UF
44 8 DDR1_DQS_P<3> C16 DQS2_1 DQS2_2 F4 DDR0_DQS_P<3> 8 44 C1627 1 C1628 1 C1629 1 C1630 1 C1631 1 K16 VDDCA3
DDR1_DQS_N<3> D16 DQSB2_1 DQSB2_2 F3 DDR0_DQS_N<3> 10UF 1UF 1UF 0.01UF 0.01UF L16
VDDCA
1/32W 10% 44 8 8 44
20% 10% 10% 10% 10% VDDCA4
MF 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R P16 VDDCA5
2 01005 01005 X5R 2 CERM 2 CERM 2 X5R 2 X5R 2
D6 DQS3_1 603 402 402 01005 01005
44 8 DDR1_DQS_P<2> DQS3_2 T3 DDR0_DQS_P<2> 8 44
T11 VDDCA6
44 8 DDR1_DQS_N<2> C6 DQSB3_1 DQSB3_2 T4 DDR0_DQS_N<2> 8 44
T12 VDDCA7
PPVREF_DDR1_DQ
13 44 45
T14 VDDCA8
NOSTUFF VOLTAGE=0.6V 45 44 13 PPVREF_DDR1_CA U10 VREFCA_1 VREFCA_2 M17 PPVREF_DDR0_CA 13 44 45 V7 VDDCA9
1
PPVREF_DDR1_DQ D11 VREFDQ_1 VREFDQ_2 L4 PPVREF_DDR0_DQ T8
1.00K 0.01UF
45 44 13 13 44 45
C1632 1 C1633 1 C1634 1 C1635 1 VDDCA10
1% 10% MAX_NECK_LENGTH=3 MM 0.22UF 0.22UF 0.22UF 56PF
1/32W 6.3V
2 X5R 20% 20% 20% 5%
MF 44 DDR1_ZQ U7 ZQ_1 ZQ_2 R17 44 DDR0_ZQ 6.3V 6.3V 6.3V
01005 X5R 2 6.3V X5R 2 NP0-C0G 2
2 01005 0201 X5R 2 0201 01005
0201
1 1
R1620 R1621
240 240
1% 1%
1/20W 1/20W
MF MF
2 201 2 201
A SYNC_MASTER=MIKE SYNC_DATE=06/21/2010 A
PAGE TITLE
DDR 0 AND 1
DRAWING NUMBER SIZE

REVISION
R
10.0.0
16 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
44 8 DDR3_CA<0> T15 CA0_1 OMIT CA0_2 G16 DDR2_CA<0> 8 44 =PP1V8_S2R_DDR A2 VDD1_0 OMIT VSS0 A16
44 8 DDR3_CA<1> U15 CA1_1 U1700 CA1_2 G17 DDR2_CA<1> 8 44
35 13
B1 VDD1_1 U1700 VSS55 A19
35 14 13 =PP1V2_S2R_DDR
44 8 DDR3_CA<2> U14 CA2_1 H4G-DRAM CA2_2 H17 DDR2_CA<2> 8 44
C1701 1 C1702 1 C1703 1 C1704 1 C1705 1 B11 VDD1_2 H4G-DRAM VSS2 A4
DDR3_CA<3> V14 CA3_1 XXXMB CA3_2 H18 DDR2_CA<3>
44 8
BGA
8 44
10UF 1UF 1UF 0.01UF 0.01UF F17 VDD1_3 XXXMB VSS3 A6
44 8 DDR3_CA<4> T13 CA4_1 CA4_2 J16 DDR2_CA<4> 8 44
20% 10% 10% 10% 10%
1 NOSTUFF SYM 1 OF 2 6.3V 6.3V 6.3V 6.3V 6.3V L2 BGA B15
R1705 T9 N16 X5R 2 CERM 2 CERM 2 X5R 2 X5R 2 VDD1_4 VSS4
VDD1
1 C1760 44 8 DDR3_CA<5> CA5_1 CA5_2 DDR2_CA<5> 8 44
D 2.21K
1%
1/32W
0.01UF
10%
44 8 DDR3_CA<6> U9
U8
CA6_1 CA6_2 N17
P17
DDR2_CA<6> 8 44
603 402 402 01005 01005 M16
T10
VDD1_5
VDD1_6
SYM 2 OF 2 VSS49
VSS6
C1
B9
D
MF 6.3V 44 8 DDR3_CA<7> CA7_1 CA7_2 DDR2_CA<7> 8 44
2 X5R U18 VDD1_7 VSS7 C11
2 01005 01005 44 8 DDR3_CA<8> V8 CA8_1 CA8_2 P18 DDR2_CA<8> 8 44
V17 VDD1_8
44 8 DDR3_CA<9> T7 CA9_1 CA9_2 R16 DDR2_CA<9> 8 44
V6 D1
PPVREF_DDR2_CA C1706 1 C1707 1 C1708 1 C1709 1
W17
VDD1_9 VSS9
D19
14 45
U12 CK_1 0.22UF 0.22UF 0.22UF 56PF VDD1_10 VSS10
44 8 DDR3_CK_P CK_2 K17 DDR2_CK_P 8 44 20% 20% 20% 5% U19 A1
1 NOSTUFF VOLTAGE=0.6V 6.3V 2 6.3V 2 6.3V 2 6.3V VDD1_11 VSS1
R1706 1 DDR3_CK_N U11 CKB_1 CKB_2 L17 DDR2_CK_N X5R X5R NP0-C0G 2
C1750 MIN_NECK_WIDTH=0.2MM
44 8 8 44
0201 X5R
0201 0201 01005 VSS12 E12
2.21K 0.01UF NET_SPACING_TYPE=PWR 44 8 DDR3_CKE<0> V13 CKE_1 CKE_2 J18 DDR2_CKE<0> 8 44
1% 10% MAX_NECK_LENGTH=3 MM E11 VDD2_1 VSS13 E13
1/32W 6.3V
MF 2 X5R E19 VDD2_2 VSS51 G5
01005
2 01005 L5 VDD2_3
=PP1V2_S2R_DDR
35 14 13 M18 VDD2_4 VSS52 T16
44 8 DDR3_CSN<0> U13 CSB_1 CSB_2 J17 DDR2_CSN<0> 8 44
U17 E7
C1710 1 C1711 1 C1712 1 C1713 1 T18
VDD2_5 VSS50
F16
0.22UF 0.22UF 0.22UF 0.22UF VDD2_6 VSS18
20% 20% 20% 20%
6.3V 2 V10 VDD2_7 VSS48 B19
DDR3_DM<0> C12 K3 DDR2_DM<0> 6.3V 6.3V 6.3V X5R
44 8 DM0_1 DM0_2 8 44 X5R 2 X5R 2 X5R 2 V16 G18
35 14 13 =PP1V2_S2R_DDR 0201 VDD2_8 VSS20
VDD2
44 8 DDR3_DM<1> B10 DM1_1 DM1_2 M2 DDR2_DM<1> 8 44
0201 0201 0201
V18 VDD2_9 VSS53 V1
DDR3_DM<3> B16 DM2_1 DM2_2 G4 DDR2_DM<3>
VSS
44 8 8 44
1 NOSTUFF W5 VDD2_10 VSS22 J1
R1751 1 DDR3_DM<2> D7 DM3_1 DM3_2 T2 DDR2_DM<2>
2.21K C1761 44 8 8 44
W16 VDD2_11 VSS23 K18
0.01UF
1%
1/32W
MF
10%
6.3V DDR3_DQ<0> C15 DQ0_1 DQ0_2 G3 DDR2_DQ<0>
C1714 1 C1715
4.3UF
1
C1716 1 C1717 1 C1718 1 C1719
0.01UF 56PF
1
W19 VDD2_12 VSS24 K5
2 X5R 44 8 8 44
10UF 1UF 1UF W18 VDD2_13 VSS25 L18
2 01005 01005 44 8 DDR3_DQ<1> D15 DQ1_1 DQ1_2 G2 DDR2_DQ<1> 8 44
20% 20%
4V 10% 10% 10%
10V
5%
6.3V
6.3V X5R-CERM 2 6.3V 6.3V X5R 2 NP0-C0G 2 V19 L3
DDR_1
DDR_2
B14 H5 X5R 2 CERM 2 CERM 2 VDD2_14 VSS26
44 8 DDR3_DQ<2> DQ2_1 DQ2_2 DDR2_DQ<2> 8 44
603 0610 402 402 201 01005
A3 VDD2_15 VSS27 M5
PPVREF_DDR3_CA 44 8 DDR3_DQ<3> C14 DQ3_1 DQ3_2 H4 DDR2_DQ<3> 8 44
14 45
T19 VDD2_16 VSS28 N18
44 8 DDR3_DQ<4> D14 DQ4_1 DQ4_2 H3 DDR2_DQ<4> 8 44
NOSTUFF VOLTAGE=0.6V VSS29 N5
1 DDR3_DQ<5> E14 DQ5_1 DQ5_2 H2 DDR2_DQ<5>
44 8 8 44
H1 VDDQ27
2.21K 0.01UF NET_SPACING_TYPE=PWR 44 8 DDR3_DQ<6> B13 DQ6_1 DQ6_2 J3 DDR2_DQ<6> 8 44
1% 10% MAX_NECK_LENGTH=3 MM =PP1V2_VDDQ_DDR M1 VDDQ32 VSS47 A18
C13 J2
C 1/32W
MF
2 01005
6.3V
2 X5R
01005
44 8
44 8
DDR3_DQ<7>
DDR3_DQ<8> C9
DQ7_1
DQ8_1
DQ7_2
DQ8_2 N4
DDR2_DQ<7>
DDR2_DQ<8>
8 44
8 44
35 14 13
W3
E1
VDDQ31
VDDQ
VSS32
VSS33
R18
R2
C
44 8 DDR3_DQ<9> D9 DQ9_1 DQ9_2 N3 DDR2_DQ<15> 8 44 C1723 1 C1720 1 C1721 1 C1724 1 C1725 1 C1726 1 C1722 1 U1 VDDQ1 VSS34 T1
44 8 DDR3_DQ<10> B8 DQ10_1 DQ10_2 P5 DDR2_DQ<10> 8 44
56PF 10UF 4.3UF 0.22UF 0.22UF 0.22UF 0.01UF
5% 20% 20% 20% 20% 20% 10% B12 VDDQ3 VSS35 T17
DDR3_DQ<11> C8 P4 DDR2_DQ<11> 6.3V 6.3V 4V 6.3V 6.3V 6.3V 6.3V
44 8 DQ11_1 DQ11_2 8 44 NP0-C0G 2 X5R 2 X5R-CERM 2 X5R 2 X5R 2 X5R 2 X5R 2 D4 U16
D8 P3 01005 603 0610 0201 0201 0201 01005 VDDQ6 VSS36
44 8 DDR3_DQ<12> DQ12_1 DQ12_2 DDR2_DQ<12> 8 44
U3 VDDQ30
44 8 DDR3_DQ<13> E8 DQ13_1 DQ13_2 P2 DDR2_DQ<13> 8 44
A14 VDDQ23 VSS54 W2
=PP1V2_VDDQ_DDR 44 8 DDR3_DQ<14> B7 DQ14_1 DQ14_2 R4 DDR2_DQ<14> 8 44 C17
VDDQ25 VSS39 U6
VDDQ
35 14 13
44 8 DDR3_DQ<15> C7 DQ15_1 DQ15_2 R3 DDR2_DQ<9> 8 44
C19 VDDQ26 VSS40 V11
1 NOSTUFF DDR3_DQ<24> B18 DQ16_1 DQ16_2 B2 DDR2_DQ<24>
R1753 44 8 8 44
A10 VDDQ22 VSS41 V12
1.00K
1 C1762 44 8 DDR3_DQ<25> C18 DQ17_1 DQ17_2 C2 DDR2_DQ<25> 8 44
1% 0.01UF A17 VDDQ34 VSS42 V15
1/32W 10% 44 8 DDR3_DQ<26> D18 DQ18_1 DQ18_2 D3 DDR2_DQ<26> 8 44
MF 6.3V J5 VDDQ16 VSS43 T6
2 X5R DDR3_DQ<27> E18 DQ19_1 DQ19_2 D2 DDR2_DQ<27>
2 01005 01005
44 8 8 44
K2 VDDQ17 VSS44 V9
44 8 DDR3_DQ<28> B17 DQ20_1 DQ20_2 E4 DDR2_DQ<30> 8 44
A8 VDDQ21 VSS45 W1
44 8 DDR3_DQ<29> D17 DQ21_1 DQ21_2 E3 DDR2_DQ<29> 8 44
PPVREF_DDR2_DQ N2 VDDQ19 VSS46 W4
14 45 44 8 DDR3_DQ<30> E17 DQ22_1 DQ22_2 E2 DDR2_DQ<28> 8 44
R5 VDDQ20
NOSTUFF VOLTAGE=0.6V 44 8 DDR3_DQ<31> E16 DQ23_1 DQ23_2 F2 DDR2_DQ<31> 8 44
1 A13
MIN_LINE_WIDTH=0.3MM 44 8 DDR3_DQ<16> B6 DQ24_1 DQ24_2 T5 DDR2_DQ<16> 8 44
VDDQ24
1.00K 0.01UF NET_SPACING_TYPE=PWR E10 VDDQ28
1% 10% MAX_NECK_LENGTH=3 MM 44 8 DDR3_DQ<17> B5 DQ25_1 DQ25_2 U5 DDR2_DQ<20> 8 44
1/32W 6.3V E15 VDDQ29
MF 2 X5R 44 8 DDR3_DQ<18> C5 DQ26_1 DQ26_2 U4 DDR2_DQ<18> 8 44
01005 P1 VDDQ33
2 01005 44 8 DDR3_DQ<19> D5 DQ27_1 DQ27_2 U2 DDR2_DQ<19> 8 44
44 8 DDR3_DQ<20> B4 DQ28_1 DQ28_2 V5 DDR2_DQ<23> 8 44 =PP1V2_S2R_DDR

35 14 13 F18 VDDCA1
44 8 DDR3_DQ<21> C4 DQ29_1 DQ29_2 V4 DDR2_DQ<21> 8 44
H16 VDDCA2
DDR3_DQ<22> B3 DQ30_1 DQ30_2 V3 DDR2_DQ<22>
44 8
DDR3_DQ<23> C3 DQ31_1 DQ31_2 V2 DDR2_DQ<17>

8 44
C1727 1 C1728 1 C1729 1 C1730 1 C1731 1 K16 VDDCA3
44 8 8 44
10UF 1UF 1UF 0.01UF 0.01UF L16
VDDCA
20% 10% 10% 10% 10% VDDCA4
6.3V 2 6.3V 6.3V 2 6.3V 2 6.3V 2 P16 VDDCA5
D13 DQS0_1 X5R CERM 2 CERM X5R X5R
=PP1V2_VDDQ_DDR 44 8 DDR3_DQS_P<0> DQS0_2 J4 DDR2_DQS_P<0> 8 44
B 35 14 13
1
44 8 DDR3_DQS_N<0> D12 DQSB0_1 DQSB0_2 K4 DDR2_DQS_N<0> 8 44
603 402 402 01005 01005 T11
T12
VDDCA6
VDDCA7
B
R1755 NOSTUFF T14
1 C1763 D10 DQS1_1 VDDCA8
1.00K 44 8 DDR3_DQS_P<1> DQS1_2 M4 DDR2_DQS_P<1> 8 44
V7
1% 0.01UF C10 DQSB1_1 VDDCA9
1/32W 10% 44 8 DDR3_DQS_N<1> DQSB1_2 M3 DDR2_DQS_N<1> 8 44
T8
MF
2 01005
6.3V
2 X5R C1732 1 C1733 1 C1734 1 C1735 1 VDDCA10
01005
C16 DQS2_1 0.22UF 0.22UF 0.22UF 56PF
44 8 DDR3_DQS_P<3> DQS2_2 F4 DDR2_DQS_P<3> 8 44 20% 20% 20% 5%
6.3V 6.3V 2 6.3V 6.3V
44 8 DDR3_DQS_N<3> D16 DQSB2_1 DQSB2_2 F3 DDR2_DQS_N<3> 8 44 X5R 2 X5R 2 NP0-C0G 2
PPVREF_DDR3_DQ 0201 X5R 0201 01005
0201
14 45
NOSTUFF VOLTAGE=0.6V 44 8 DDR3_DQS_P<2> D6 DQS3_1 DQS3_2 T3 DDR2_DQS_P<2> 8 44

1
MIN_LINE_WIDTH=0.3MM 44 8 DDR3_DQS_N<2> C6 DQSB3_1 DQSB3_2 T4 DDR2_DQS_N<2> 8 44
1.00K 0.01UF NET_SPACING_TYPE=PWR
1% 10% MAX_NECK_LENGTH=3 MM
1/32W 6.3V
2 X5R
MF 45 14 PPVREF_DDR3_CA U10 VREFCA_1 VREFCA_2 M17 PPVREF_DDR2_CA 14 45
01005
2 01005 45 14 PPVREF_DDR3_DQ D11 VREFDQ_1 VREFDQ_2 L4 PPVREF_DDR2_DQ 14 45
44 DDR3_ZQ U7 ZQ_1 ZQ_2 R17 44 DDR2_ZQ
1 1
R1720 R1721
240 240
1% 1%
1/20W 1/20W
MF MF
2 201 2 201
PAGE TITLE
DDR 2 AND 3
DRAWING NUMBER SIZE

REVISION
R
10.0.0
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D D
WIFI ALIASES
C 42 40 4
42 40 4
HSIC1_WLAN_DATA1
HSIC1_WLAN_STB1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
HSIC_DATA_4330 31 33
HSIC_STROBE_4330 31 33
C
42 5 HSIC_HOST_READY_WLANMAKE_BASE=TRUE WLAN_GPIO1 31 33
42 5 HSIC_WLAN_RDY MAKE_BASE=TRUE HSIC_DEVICE_READY 31

45 37 RST_WLAN_L MAKE_BASE=TRUE WLAN_ENABLE 31 33
37 PM_WLAN_HOST_WAKE MAKE_BASE=TRUE WLAN_GPIO0 31 33
45 37 RST_BT_L MAKE_BASE=TRUE BT_RESET_N 31 33
37 PM_BT_HOST_WAKE MAKE_BASE=TRUE BT_HOST_WAKE 31 33
5 PM_BT_WAKE MAKE_BASE=TRUE BT_WAKE 31 33
42 5 UART3_BT_RXD MAKE_BASE=TRUE BT_UART_TXD 31 33
42 5 UART3_BT_TXD MAKE_BASE=TRUE BT_UART_RXD 31 33
42 5 UART3_BT_CTS_L MAKE_BASE=TRUE BT_UART_RTS_N 31 33
42 5 UART3_BT_RTS_L MAKE_BASE=TRUE BT_UART_CTS_N 31 33
42 37 CLK_32K_WLAN MAKE_BASE=TRUE CLK32K 32 33
42 19 5 I2S2_VSP_BCLK MAKE_BASE=TRUE BT_PCM_CLK 31
42 19 5 I2S2_VSP_DOUT MAKE_BASE=TRUE BT_PCM_DIN 31
42 19 5 I2S2_VSP_DIN MAKE_BASE=TRUE BT_PCM_DOUT 31
42 19 5 I2S2_VSP_LRCK MAKE_BASE=TRUE BT_PCM_SYNC 31
42 5 UART6_WLAN_RXD MAKE_BASE=TRUE WLAN_GPIO4 31 33
42 5 UART6_WLAN_TXD MAKE_BASE=TRUE WLAN_GPIO3 31 33
B B
UART ALIASES
42 5 UART0_AP_RXD MAKE_BASE=TRUE UART0_MUX_RXD 11 42
42 5 UART0_AP_TXD MAKE_BASE=TRUE UART0_MUX_TXD 11 42
OBSOLETE ALIASES
NC_EXT_SMPS_REQ MAKE_BASE=TRUE EXT_SMPS_REQ
NC_EXT_PWM_REQ MAKE_BASE=TRUE EXT_PWM_REQ
NC_BT_GPIO5 MAKE_BASE=TRUE BT_GPIO5 31
TP_WLAN_GPIO5 MAKE_BASE=TRUE WLAN_GPIO5 31
45 30 5 GSM_TXBURST_IND MAKE_BASE=TRUE LED_DRIVE_GSMB
A NEED TO DOUBLE CHECK IF WE NEED THIS IN IPAD, OR IF THIS MIGHT BE A PHONE SPECIFIC ISSUE
SYNC_MASTER=ALEX SYNC_DATE=09/30/2010 A
PAGE TITLE
MLB ALIASES/CONNECTIONS
DRAWING NUMBER SIZE

REVISION
R
10.0.0
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SIA413DJ
MOSFET
CHANNEL
RDS(ON)
IMAX
SIA413DJ
P-TYPE
100MOHM @-1.5V
3 A
EDP CONNECTOR PART NUMBER
376S0903
ALTERNATE FOR
PART NUMBER
376S0796
BOM OPTION REF DES
Q2200
L2242,L5500,L5501,L5600,L5601,L5620
COMMENTS:
RADAR:8379470
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
155S0667 155S0583 RADAR:8616060, RADAR: 9015335

VGS MAX +/- 8V
CRITICAL
D Q2200 VOLTAGE=3.3V
MIN_LINE_WIDTH=0.30 MM
CRITICAL
L2201
D
SIA413DJ MIN_NECK_WIDTH=0.20 MM
FERR-120-OHM-1.5A
SC70-6L
45 16 PP3V3_S0_LCD_FERR 1 2
7
35 16 =PP3V3_LCD
S
0402B
D
4
1
1 NOSTUFF 1 C2203 1 C2202
1
R2290 1 C2230
1 C2232 1 C2206
1 C2240 1 C2241 R2210 1
R2203 47K 82PF 1000PF
10K 0.1UF 1UF 82PF 5% 10%
G
82PF 82PF 5%
1% 39K 10% 10% 1/20W 5% 2 25V 16V
2 X7R
5% 5% 1/20W 1% 2 6.3V 2 6.3V MF 2 25V CERM
=PP3V3_LCD 25V 25V X5R CERM CERM 0201 201
3
35 16 2 CERM 2 CERM MF 1/20W 201 402 2 201 0201
0201 0201 2 201 MF
NOSTUFF 2 201 C2204
R22111 R2204 R2250 0.015UF
21.5K2 0
10K 1 1 2 1 2
1% R2250_1
1/20W LCDVDD_PWREN_L 1% 5% LCDVDD_PWREN_L_R
MF 1/20W 1/20W 10%
201 2 MF MF 6.3V VOLTAGE=3.3V
D 3 201 201 X5R MIN_LINE_WIDTH=0.30 MM
0201
MIN_NECK_WIDTH=0.20 MM 45 PP3V3_LCDVDD_SW_F
Q2201
6 PM_LCDVDD_PWREN 1 2N7002TXG
IN
G SOT-523-3
1
R2205 S 2
100K
1%
1/20W
MF
2 201 45 16 PP3V3_S0_LCD_FERR
518S0827
CRITICAL
EDP_AP_HPD OUT
1
R2240 J2200 7 43
100K 502250-8051 1
1%
1/32W F-RT-SM R2242
MF 54 100K
C 43 7 IN EDP_AP_AUX_N C2250
1 20.1UF
43 EDP_EMI_AUX_N
2 01005
2 TCM0605-1 3 EDP_AUX_CONN_N 16 43
52 1%
1/32W
MF
C
201 6.3V 10% X5R 2 01005
1
2
EDP_AP_AUX_P C2251
1 0.1UF
2 EDP_EMI_AUX_P 1 4 EDP_AUX_CONN_P 3
43 7 IN 43 16 43 NC 4
201 6.3V 10% X5R SYM_VER-2
90-OHM-50MA 5
6
1
R2241 L2242 7
8
NC
100K 43 16 EDP_AUX_CONN_P 9
10
1% EDP_AUX_CONN_N 16 43
1/32W 11
MF 12 EDP_DATA_CONN_N<0> 16 43
13
2 01005 NC 14 EDP_DATA_CONN_P<0> 16 43
15
16 EDP_DATA_CONN_N<1> 16 43
17
NC 18 EDP_DATA_CONN_P<1> 16 43
19
21
43 7 EDP_AP_TX_N<0> C2242
1 20.1UF 43 EDP_EMI_TX_N<0> EDP_DATA_CONN_N<0> 16 43
NC 22 EDP_DATA_CONN_P<2> 16 43
IN 2 3 23
201 6.3V 10% X5R 24 EDP_DATA_CONN_N<3> 16 43
25
0.1UF NC 26 EDP_DATA_CONN_P<3> 16 43
43 7 IN EDP_AP_TX_P<0> C2243
1 2 43 EDP_EMI_TX_P<0> 1 4
EDP_DATA_CONN_P<0> 16 43 27
28
201 6.3V 10% X5R TCM0806-4SM
SYM_VER-2
29
12-OHM-100MA-8.5GHZ 30 LED_IO_6_B 37 43
31 IN
LED_IO_5_B
L2212 43 37
43 37
IN
LED_IO_3_B 33
32 LED_IO_4_B IN 37 43
IN 34 LED_IO_2_B IN 37 43
43 37 IN LED_IO_1_B 35
36
43 7 EDP_AP_TX_N<1> C2244
1 20.1UF 43 EDP_EMI_TX_N<1> EDP_DATA_CONN_N<1> 16 43 43 37 LED_IO_6_A 37
IN 2 3 IN 38 LED_IO_5_A IN 37 43
201 6.3V 10% X5R 43 37 LED_IO_4_A 39
IN 40 LED_IO_3_A IN 37 43
0.1UF LED_IO_2_A 41
43 7 IN EDP_AP_TX_P<1> C2245
1 2 43 EDP_EMI_TX_P<1>
1 4
EDP_DATA_CONN_P<1> 16 43
43 37 IN
43
42 LED_IO_1_A IN 37 43
SYM_VER-2
TCM0806-4SM
201 6.3V 10% X5R 44
12-OHM-100MA-8.5GHZ 45 NC
46
L2222 NC 47
48
B 43 7 IN EDP_AP_TX_N<2> C2246
1
201 6.3V
20.1UF
10% X5R
43 EDP_EMI_TX_N<2>
2 3
EDP_DATA_CONN_N<2> 16 43
49
51
50
NC B
EDP_AP_TX_P<2> C2247
1 0.1UF
2 43 EDP_EMI_TX_P<2> EDP_DATA_CONN_P<2> 53
43 7 IN 16 43
1 SYM_VER-2
4
201 6.3V 10% X5R TCM0806-4SM 55
12-OHM-100MA-8.5GHZ
L2232
43 7 EDP_AP_TX_N<3> C2248
1 20.1UF 43 EDP_EMI_TX_N<3> EDP_DATA_CONN_N<3> 16 43
IN 2 3
201 6.3V 10% X5R
EDP_AP_TX_P<3> C2249
1 0.1UF
2 43 EDP_EMI_TX_P<3> EDP_DATA_CONN_P<3>
43 7 IN 16 43
1 SYM_VER-2
4
201 6.3V 10% X5R TCM0806-4SM
12-OHM-100MA-8.5GHZ
R2280 L2202
1.00M2
01005
R2281 CRITICAL
1.00M2
1 EDP_DATA_CONN_P<0>
L2210
16 43 FERR-240-OHM-25%-300MA
01005
35 =PPLED_REG_B 1 2 45 PPLED_BACK_REG_B
R2282 VOLTAGE=20.4V
MIN_LINE_WIDTH=0.6 MM 0402
1.00M2 MIN_NECK_WIDTH=0.2 MM
1 EDP_DATA_CONN_N<1> 16 43 NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM
1 C2253 1 C2270
01005 100PF 820PF
5% 10%
R2283 2 50V
2 50V
CERM
1.00M2 CERM
402 402
1 EDP_DATA_CONN_P<1> 16 43
01005
R2284
1.00M2
1 EDP_DATA_CONN_N<2>
A 01005
16 43
CRITICAL
L2200 SYNC_MASTER=JOE SYNC_DATE=01/19/2011 A
R2285 FERR-240-OHM-25%-300MA PAGE TITLE
1.00M2
1 EDP_DATA_CONN_P<2> 16 43
35 =PPLED_REG_A 1 2 45 PPLED_BACK_REG_A
VIDEO: EDP CONNECTOR
01005 VOLTAGE=20.4V DRAWING NUMBER SIZE
MIN_LINE_WIDTH=0.6 MM 0402
R2286 MIN_NECK_WIDTH=0.2 MM
NET_SPACING_TYPE=PWR 1 C2233 1 C2220 Apple Inc. 051-8773 D
1
1.00M2 EDP_DATA_CONN_N<3> MAX_NECK_LENGTH=3 MM 100PF 820PF REVISION
16 43 R
01005 2
5%
50V
10%
50V
2 CERM
10.0.0
CERM
R2287 402 402 NOTICE OF PROPRIETARY PROPERTY: BRANCH
1.00M2
1 EDP_DATA_CONN_P<3> THE INFORMATION CONTAINED HEREIN IS THE
16 43 PROPRIETARY PROPERTY OF APPLE INC.
01005
22 OF 157
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8 7 6 5 4 3 2 1
=PP3V0_GRAPE 17 18 35
45 17 PP18V_GRAPE
=PP3V0_GRAPE_MARIO1 35
C3005 1 C3007 1 C3053 1

1 C3006
1
R3025
0.1UF 0.1UF 0.1UF 10K
10% 10% 10% 0.1UF 5%
25V 2 25V 2 25V 2 10% 1/20W
X5R X5R X5R 6.3V
TABLE_5_HEAD
402 402 402 2 X5R MF
F3
E9
B6
A6
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 201 2 201
TABLE_5_ITEM
343S0525 1 IC,ASIC,GROUNDHOG B0,120B BGA U3003 CRITICAL VCC_DIG

VDDH
SPI1_GRAPE_SCLK MAKE_BASE=TRUE GRAPE_SCLK
42 17 5 IN OUT 18
CONNECTORS TO GRAPE FLEX U3003 42 17 5

SPI1_GRAPE_CS_L MAKE_BASE=TRUE GRAPE_CS_L 18
MUX_IN<0> B1 GROUNDHOG A1 MT_PANEL_OUT<0> 17

IN OUT
18 MUX0 BGA VSTM0
D R3070
0
18 MUX_IN<1> C1
E1
MUX1
CRITICAL
VSTM1 B2
C2
MT_PANEL_OUT<1> 17 D
17 AG_SHLD_TST_FLEX 1 2 AG_SHLD_TST 18 18 MUX_IN<2> MUX2 VSTM2 MT_PANEL_OUT<2> 17
MUX_IN<3> F2 OMIT D1 MT_PANEL_OUT<3> 17 SPI1_GRAPE_MOSI MAKE_BASE=TRUE GRAPE_MOSI
5% 18 MUX3 VSTM3 42 17 5 IN OUT 18
1/20W RST_GRAPE_L RST_GRAPE_Z1_L
MF 18 MUX_IN<4> H1 MUX4 VSTM4 D2 MT_PANEL_OUT<4> 17 45 6 18
201 IN OUT
R3071
MUX_IN<5> J1 VSTM5 E2 MT_PANEL_OUT<5> 17

2
18 MUX5 MAKE_BASE=TRUE
1 C3070 J2 F1
1/20W
MUX_IN<6> MUX6 VSTM6 MT_PANEL_OUT<6> 17

0.1UF 18
201
5%
MF
0
10% MUX_IN<7> J3 G1 MT_PANEL_OUT<7> 17 TO Z2

25V 18 MUX7 VSTM7
2 X5R K4 G2 RST_GRAPE_Z2_L
NOSTUFF 18 MUX_IN<8> MUX8 VSTM8 MT_PANEL_OUT<8> 17 18
1
402 OUT
18 MUX_IN<9> H5 MUX9 VSTM9 I1 MT_PANEL_OUT<9> 17
18 MUX_IN<10> I5 MUX10 VSTM10 H2 MT_PANEL_OUT<10> 17
18 MUX_IN<11> J8 MUX11 VSTM11 I2 MT_PANEL_OUT<11> 17
18 MUX_IN<12> J9 MUX12 VSTM12 K1 MT_PANEL_OUT<12> 17
18 MUX_IN<13> K8 MUX13 VSTM13 K2 MT_PANEL_OUT<13> 17
18 MUX_IN<14> J10 MUX14 VSTM14 I3 MT_PANEL_OUT<14> 17
CRITICAL 18 MUX_IN<15> I10 MUX15 VSTM15 K3 MT_PANEL_OUT<15> 17
MUX_IN<16> H10 MUX16 VSTM16 J4 MT_PANEL_OUT<16> 17
P/N 518S0828 18
18 MUX_IN<17> F11 MUX17 VSTM17 I4 MT_PANEL_OUT<17> 17

42 17 5
SPI1_GRAPE_MISO GRAPE_MISO 18
41 MUX_IN<18> C11 K6 MT_PANEL_OUT<18> 17 OUT IN
18 MUX18 VSTM18
39 E10 H6 MAKE_BASE=TRUE
18 MUX_IN<19> MUX19 VSTM19 MT_PANEL_OUT<19> 17
A11 MUX20 VSTM20 K5 MT_PANEL_OUT<20> 17
17 MT_PANEL_OUT<36> NC
37 MT_PANEL_OUT<37> 17
B4 MUX21 VSTM21 J5 MT_PANEL_OUT<21> 17
36 NC
MT_PANEL_OUT<39> A5 MUX22 VSTM22 I7 MT_PANEL_OUT<22> 17
34 17
NC
33 A2 MUX23 VSTM23 K9 MT_PANEL_OUT<23> 17
18 MT_PANEL_IN<29> 32 NC
31 MT_PANEL_IN<28> 18 VSTM24 I8 MT_PANEL_OUT<24> 17
18 MT_PANEL_IN<27> 30 18 Z1_BON_L<0> C7 BON_L0
29 MT_PANEL_IN<26> 18 VSTM25 K10 MT_PANEL_OUT<25> 17 =PP3V0_GRAPE 17 18 35
18 MT_PANEL_IN<25> 28 18 Z1_BON_L<1> A7 BON_L1
27 MT_PANEL_IN<24> VSTM26 I6 MT_PANEL_OUT<26> 17
26 18
B7
18 MT_PANEL_IN<23>
25 MT_PANEL_IN<22>
18 Z1_BON_L<2> BON_L2 J7 MT_PANEL_OUT<27> 17
1
R3030 1R3031 1 C3030 1 C3031 1R3032 1R3033
C 18
18
MT_PANEL_IN<21>
MT_PANEL_IN<19>
23
24
22
MT_PANEL_IN<20>
18
18
40 18
18 Z1_BON_L<3>
Z1_BON_L<4>
B8
A8
BON_L3
BON_L4
VSTM27
VSTM28 K11 MT_PANEL_OUT<28> 17
10K
5%
1/20W
5%
10K
1/20W
0.1UF
10%
2 6.3V
0.1UF
10%
2 6.3V
5%
3.3K
1/20W
10K
5%
1/20W
C
21 MT_PANEL_IN<18> VSTM29 I9 MT_PANEL_OUT<29> 17 X5R CRITICAL X5R
2
20 18 MF MF 201 201 MF MF
MT_PANEL_IN<17> Z1_BON_L<5> C8 BON_L5
18
19 MT_PANEL_IN<16>
40 18
VSTM30 J11 MT_PANEL_OUT<30> 17 2 201 2 201 2 201 2 201
MT_PANEL_IN<15> 18 18 VCCA VCCB
18 17 MT_PANEL_IN<14> C6 VSTM31 I11 MT_PANEL_OUT<31> 17
18 MT_PANEL_IN<13> 16 18
NC U3007
15 MT_PANEL_IN<12> 18 D3 VSTM32 H11 MT_PANEL_OUT<32> 17 DIR_U3007 PQFP1
MT_PANEL_IN<11> 14 NC
SN74AVCH4T245RSV
18 13 SPI1_GRAPE_SCLK Z1_SCLK
MT_PANEL_IN<10> D4 VSTM33 G11 MT_PANEL_OUT<33> 17 6 1A1 1B1 15
18 MT_PANEL_IN<9> 12 18
NC 42 17 5 IN OUT 18
11 MT_PANEL_IN<8> D5 VSTM34 G10 MT_PANEL_OUT<34> 17 SPI1_GRAPE_CS_L 8 2A1 2B1 13 Z2_H_CS_L
18 MT_PANEL_IN<7> 10 18
NC 42 17 5 IN OUT 17 18
9 MT_PANEL_IN<6> D6 VSTM35 F10 MT_PANEL_OUT<35> 17 TO Z1/Z2
MT_PANEL_IN<5> 8 18
NC 4 1DIR
18 7 MT_PANEL_IN<4> D8 VSTM36 C10 MT_PANEL_OUT<36> 17
18 MT_PANEL_IN<3> 6 18
NC 1 1OE*
5 MT_PANEL_IN<2> D9 VSTM37 D10 MT_PANEL_OUT<37> 17
18 MT_PANEL_IN<1> 4 18
NC
3 MT_PANEL_IN<0> E4 VSTM38 E11 MT_PANEL_OUT<38> 17 SPI1_GRAPE_MOSI 7 1A2 1B2 14 Z1_MISO
17 AG_SHLD_TST_FLEX 2 18
NC 42 17 5 IN
Z1_CS_OE
OUT 18 40
1 E8 VSTM39 D11 MT_PANEL_OUT<39> 17 9 2A2 2B2 12
NC OUT 17 18
F4 VSTM40 B11
NC NC 5 2DIR
38 F5 VSTM41 B10
NC NC GRAPE_FW_DNLD_EN_L 16 2OE*
40 F8 NC C4 6 IN APN:311S0485
NC VSTM42 NC
F9 VSTM43 A4 (A -> B)
NC NC
G3 VSTM44 B5
NC NC GND
F-RT-SM G4 VSTM46 A3
NC NC
10
11
502250-8037 G9 VSTM45 C5
NC NC
H3 VSTM47 B3
J3010 NC
H4
NC
NC A_AD_R0 A10 Z1_B_ADR<0> 18 40
MATES WITH LEFTMOST GRAPE FLEX TAIL NC
H7
A_AD_R1 B9 Z1_B_ADR<1> 18 40
CRITICAL H8
NC A_AD_R2 A9 Z1_B_ADR<2> 18 40
41 H9
NC
39 J6
NC
K7
NC
B 17 MT_PANEL_OUT<1>
37
35
36
MT_PANEL_OUT<0>
MT_PANEL_OUT<2>
17
GND
=PP3V0_GRAPE
B
G8
G7
G6
G5
F7
F6
E7
E6
E5
E3
D7
C9
17 17 18 35
17 MT_PANEL_OUT<5> 32 1 C3041
17 MT_PANEL_OUT<7> 30 =PP3V0_GRAPE 0.1UF
17 18 35
10%
17 MT_PANEL_OUT<9> 28 CRITICAL 2 6.3V
1 C3050 X5R
MT_PANEL_OUT<11> 26 CRITICAL 201
6
17
25
24
MT_PANEL_OUT<12> 17
0.1UF
10%
U3009
17 MT_PANEL_OUT<13> VCC SN74LVC1G125DRYR-M
6.3V
2 X5R LLP 6
22 Z1_MOSI
17
17
MT_PANEL_OUT<15>
MT_PANEL_OUT<17>
21
19
20
MT_PANEL_OUT<16> 17 BOOST CONVERTOR MIN_NECK_MIDTH SHOULD BE 0.4MM
U3010
SN74LVC1G126DRYR-M
201 42 17 5 OUT
SPI1_GRAPE_MISO 4
2 IN 18
MT_PANEL_OUT<18> CRITICAL LLP NC 5

17 MT_PANEL_OUT<19> 18 17
MIN_LINE_WIDTH=0.2MM CRITICAL
MIN_LINE_WIDTH=0.6MM LOAD CURRENT ~ 153UA Z1_CS_OE OE* NC
17 MT_PANEL_OUT<20> L3000 1 OE 3
MT_PANEL_OUT<21> 16 17 MIN_NECK_WIDTH=0.2MM
D3000 MIN_NECK_WIDTH=0.25MM 18 17 IN
17
4.7UH-700MA-280MOHM MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.2MM SOD-323
VOLTAGE=18V
R3066 1
MT_PANEL_OUT<23> 14 45 PP18V_R_GRAPE 0.1
17 13 MT_PANEL_OUT<24> 45 VR_BOOST_L 1 2 45 VR_BOOST_SW 1 2 1 2 PP18V_GRAPE Z2_H_CS_L 2 A Y 4 Z1_CS_L
12 17 17 45 18 17 IN OUT 18
17 MT_PANEL_OUT<25> MIN_LINE_WIDTH=0.6MM Z1_CS_OE
11 MT_PANEL_OUT<26> VLF 1%
MT_PANEL_OUT<27> 10 17
1/20W
MIN_NECK_WIDTH=0.2MM 18 17 IN
17
C3009 B0520WSXG MF
VOLTAGE=18V
NET_SPACING_TYPE=PWR GND NC
8 C3000
17 MT_PANEL_OUT<29>
7 =PP3V0_GRAPE 1 2 C3008 1 R3009 1 1 201
5
MT_PANEL_OUT<30> 17 35 18 17
1UF
MT_PANEL_OUT<31> 6 1M
17
5 MT_PANEL_OUT<32> 33PF 1% 10%
17 MT_PANEL_OUT<33> 4 17
0.1UF 5% 1/16W 2 25V NC
3 MT_PANEL_OUT<34> 25V X5R
MT_PANEL_OUT<35> 2 17
10% NP0-C0G 2 MF-LF 603-1
17 1 16V 201 402 2
2 X5R
CRITICAL 402
38 VIN
40
1 L U3000 FB 4 VR_BOOST_FBK
F-RT-SM TPS61045
QFN-1 1
502250-8037 NC 3 DO CTRL 5 PM_BOOST_EN 18 R3012
1 C3002 71.5K
J3011
A 1 C3001 SW 8 470PF
10%
1%
1/20W
MF SYNC_MASTER=RAMSIN SYNC_DATE=12/17/2010 A
PGND
MATES WITH RIGHTMOST GRAPE FLEX TAIL 2.2UF 16V

2 201
GND
10% THRML 2 X5R-X7R PAGE TITLE

2 6.3V PAD
X5R
603
9 7 6
201
GRAPE: GROUNDHOG,CONN,BOOST
TABLE_ALT_HEAD
DRAWING NUMBER SIZE

45 AGND_U3000 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
2 TABLE_ALT_ITEM
REVISION
311S0523 311S0485 U3007 R
XW3000 TABLE_ALT_ITEM
10.0.0
SM 311S0524 311S0533 U3009 NOTICE OF PROPRIETARY PROPERTY: BRANCH
1 TABLE_ALT_ITEM

311S0525 311S0532 U3010 PROPRIETARY PROPERTY OF APPLE INC.
30 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ZEPHYR 1+ ASIC
35 =PP3V0_GRAPE_Z1 ARM9 MCU (Z2 BASED)
1 C3102 45 18 Z1_1V8_OUT =PP3V0_GRAPE_Z2
0.1UF 45 Z2_VDDCORE 35
10% VOLTAGE=1.8V
6.3V
VOLTAGE=3.0V
2 X5R
201 1 C3101 MIN_LINE_WIDTH=0.5MM
1 C3111 1 C3109 1 C3105 1 C3107
R3101 MIN_NECK_WIDTH=0.2MM
10UF 0.1UF 0.1UF 4.7UF
NET_SPACING_TYPE=PWR 2.2UF NET_SPACING_TYPE=PWR 20% 10% 10% 20%
1
4.7 2
20% 2 6.3V 2 6.3V 2 6.3V 6.3V
2 X5R-CERM1
45 MT_3V3_INT 2 4V CERM-X5R X5R X5R
X5R VDDANA AND VDDCORE 0402-1 201 201 402
D
5%
1/20W
MF
1 C3104
2.2UF
1 C3103
0.1UF
402
=PP3V0_GRAPE
ARE EACH GENERATED WITHIN
Z2 AND BYPASSED OUTSIDE D
201 17 18 35 VOLTAGE=1.8V
20% 10%
4V 6.3V NET_SPACING_TYPE=PWR
2 X5R 2 X5R 45 Z2_VDDANA MIN_LINE_WIDTH=0.6MM R3190
402 201 VOLTAGE=1.8V
MIN_NECK_WIDTH=0.2MM 45 Z2_3V3_1V8_IN
1
1.00 2 Z1_1V8_OUT
1 18 45
R3155 MIN_NECK_WIDTH=0.1MM
NET_SPACING_TYPE=PWR MIN_LINE_WIDTH=0.6MM
100K 1 C3110 1% MIN_NECK_WIDTH=0.25MM
1/20W
5% 1 C3112 0.1UF 1 C3108 MF VOLTAGE=1.8V
1/20W
MF 2.2UF 10% 1 C3106 1 C3191 1 C3192 201 NET_SPACING_TYPE=PWR
0.1UF
K10
C10
20% 6.3V
0.1UF 10UF 10UF MIN_NECK_MIDTH SHOULD BE 0.4MM
2 201 2 X5R
G6
G7
G8
K4
C5
C9
B6
4V 10% 20% 20%
2 X5R 201 10%
402 2 6.3V
X5R 2 6.3V
6.3V
2 CERM-X5R 2 6.3V
CERM-X5R
VDDDIG V18 201 X5R 0402-1 0402-1
17 MT_PANEL_IN<0>
H2 IN0 SCLK A11 Z1_SCLK 17 18 201
VDDANA IN
G2 CRITICAL VDDIO B10
17 MT_PANEL_IN<1> IN1 CS* Z1_CS_L IN 17
17 MT_PANEL_IN<2> D7 IN2 U3100 MISO B9 Z1_MISO IN 17 18 40
D2
E1
G8
H2
J5
E2
E3
17 MT_PANEL_IN<3> C1 IN3 BCM5973 MOSI B8 Z1_MOSI OUT 17 18
R3120
F1 BGA 0
17 MT_PANEL_IN<4> IN4 5%
VDDANA VDDCORE VDDIO VDDLDO 1/20W
17 MT_PANEL_IN<5> J1 IN5 GO A8 Z1_GO 18 MF
201
17 MT_PANEL_IN<6> D2 IN6 DONE B7 Z1_DONE A9
IN0_0 B_ADR0 F9 1 2 Z1_CS_OE IN
18
NC 17
17 MT_PANEL_IN<7> D1 IN7 B9 IN0_1 B_ADR1 F8 Z1_PCLK Z2 - PRODUCT STRAP OPTIONS

NC 18
17 MT_PANEL_IN<8> K7 IN8 PCLK A12 Z1_PCLK 18 B_ADR2 G9

A7 IN1_0 CRITICAL BON_L5 BON_L4 BON_L3 MODE
17 MT_PANEL_IN<9> H1 IN9 NC
A8 IN1_1 BON_L0 J8 Z1_CS_OE_R
17 MT_PANEL_IN<10> E1 IN10 STMOUT A10 NC U3101 LOW X X K48
Z1_STMIN BON_L1 H9 NC_BON_L1 46
17 MT_PANEL_IN<11> E2 IN11 STMIN A13 NC
B8 IN2_0 BCM5974CKFBGH J9
FBGA BON_L2 AG_SHLD_TST 17 FLOAT FLOAT FLOAT K94
17 MT_PANEL_IN<12> J2 IN12 C8 IN2_1
NC BON_L3 H7 NC_BON_L3 46
17 MT_PANEL_IN<13> G1 IN13 B_ADR0 A5 Z1_B_ADR<0> 17 40 FLOAT LOW FLOAT J2
B7 IN3_0 BON_L4 J7
17 MT_PANEL_IN<14> F2 IN14 B_ADR1 B5 Z1_B_ADR<1> 17 40
NC
C7 IN3_1 BON_L5 H5 NC_BON_L5 ALL OTHER STRAPS CRITICAL ERROR
17 MT_PANEL_IN<15> J7 IN15 B_ADR2 A6 Z1_B_ADR<2> 17 40
NC 46
17 MT_PANEL_IN<16> K2 IN16 A6
IN4_0 GPIO0 J2 IRQ_GRAPE_HOST_INT_L DEFAULT J2
NC OUT 5
17 MT_PANEL_IN<17> N4 IN17 BON_L0 A2 Z1_BON_L<0> B6 IN4_1 GPIO1 J3 PM_BOOST_EN

17
NC OUT 17
C 17 MT_PANEL_IN<18>
17 MT_PANEL_IN<19>
M5
N5
IN18 BON_L1 A1
A3
Z1_BON_L<1>
Z1_BON_L<2>
17
NC
C6 IN5_0 GPIO2 H4
J6
Z1_GO
Z1_DONE
18
1
C
IN19 BON_L2 17
C5 IN5_1 GPIO3 18 R3160
17 MT_PANEL_IN<20> M6 IN20 BON_L3 A4 Z1_BON_L<3> 17
NC GPIO4 G3 GRAPE_CS_L IN 17 100K
B5 IN6_0 F3 5%
17 MT_PANEL_IN<21> N3 IN21 BON_L4 B4 Z1_BON_L<4> 17 40 GPIO5 GRAPE_MOSI 17 1/20W
NC IN
MF
17 MT_PANEL_IN<22> M3 IN22 BON_L5 B3 Z1_BON_L<5> A5 IN6_1 GPIO6 F4 GRAPE_MISO
17 40
NC OUT 17 2 201
17 MT_PANEL_IN<23> L1 IN23 GPIO7 H6 GRAPE_SCLK 17
A4 IN
K1 NC IN7_0
17 MT_PANEL_IN<24> IN24 TM A9 U3100_TM
B4 IN7_1 G6
CFG1 CFG0 MODE JTAG_TCK TP_U3101_TCK
17 MT_PANEL_IN<25> L2 IN25 NC
JTAG_TDI E8 TP_U3101_TDI
17 MT_PANEL_IN<26> N6 IN26 RESET* A7 RST_GRAPE_Z1_L 0 0 DEPENDENT 1 A3 IN8_0
17
NC JTAG_TDO E9 TP_U3101_TDO
17 MT_PANEL_IN<27> M2 IN27 B3 IN8_1
0 1 DEPENDENT 2 NC JTAG_TMS F7 TP_U3101_TMS
17 MT_PANEL_IN<28> M4 IN28 =PP3V0_GRAPE 17 18 35
C2 IN9_0
17 MT_PANEL_IN<29> M1 IN29 R3181 1 0 AUTONOMOUS NC
A2 IN9_1 H_CS* H1 Z2_H_CS_L
IN 17 1
N2 100 NC J1 Z1_SCLK R3107
17 MUX_IN<0> IN30 1 2 H_SCLK IN 17 18
N1 1 1 SLAVE B2 H3 Z1_MISO 100K
17 MUX_IN<1> IN31 5% IN10_0 H_SDI 5%
1/32W NC IN 17 18 40
1/20W
17 MUX_IN<2> N13 IN32 MF C1 IN10_1 H_SDO J4 Z1_MOSI 17 18 MF
01005 NC OUT
17 MUX_IN<3> N12 IN33 K48 USES DEPENDENT 2 MODE 2 201
B1
IN11_0 A_CS* F1 Z2_A_CS_L
17 MUX_IN<4> M10 IN34 NC TP_Z2_A_SCLK
A1 IN11_1 G1
17 MUX_IN<5> M13 IN35 NC A_SCLK
F2 TP_Z2_A_SDI
R3180
N8 E6 A_SDI 100
17 MUX_IN<6> IN36 ARMTAPMD* 1 2
NC A_SDO G4 TP_Z2_A_SDO
17 MUX_IN<7> M12 IN37 5%
BOOT_CFG0_R F6 BOOT_CFG0 1/32W
17 MUX_IN<8> K13 IN38 TM0 E7 TP_U3101_TM0 MF
BOOT_CFG1_R D3 BOOT_CFG1 01005
17 MUX_IN<9> L13 IN39 TM1 D4 U3101_TM1
17 MUX_IN<10> L12 IN40 G5 FLOO
NC CLKIN E5 HOST_REFCLK CLK_32K_PMU IN 37 42
17 MUX_IN<11> M11 IN41 1 F5 LFOO
R3173 NC CLKOUT E4 MAKE_BASE=TRUE
17 MUX_IN<12> N11 IN42 0 NC
5% G7 EXTFLLIN
17 MUX_IN<13> M8 IN43 1/20W NC INTERNAL PU RESET* D5 RST_GRAPE_Z2_L IN 17
MF
B 17 MUX_IN<14>
17 MUX_IN<15>
N9
M9
IN44
IN45
2 201 R3171 GND B
17 MUX_IN<16> N10
0
C3
C4
D6
D7
D8
C9
D9
G2
D1
H8
IN46 1 2
17 MUX_IN<17> K12 IN47
17 MUX_IN<18> J13 IN48
17 MUX_IN<19> F12 IN49 35 18 17
G13 IN50 =PP3V0_GRAPE
NC
J12 IN51
NC
E12 IN52
NC
E13 IN53
NC
H13 IN54
NC
N7 IN55
NC
D13 IN56
NC
D12 IN57
NC
H12 IN58
NC
F13 IN59
NC
NC C13 IN60
E7 IN61
NC
M7 IN62
NC
G12 IN63
NC
A SYNC_MASTER=RAMSIN SYNC_DATE=12/17/2010 A
GNDANA PAGE TITLE
GNDDIG GNDIO
GRAPE: Z1, Z2
B1
B2
B12
B13
C2
C3
C6
C7
C8
C11
C12
D3
D11
F7
H7
L3
L4
L5
L6
L7
L8
L9
L10
L11
C4
B11
DRAWING NUMBER SIZE

REVISION
R
10.0.0
31 OF 157
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
L63B AUDIO CODEC

APN:338S0940
D 35 22 20 =PPVCC_MAIN_AUDIO =PP1V7_VA_VCP 35 D
35 =PP1V8_AUDIO
1 C3605 1 C3606 1 C3607 1

27PF 10UF 0.1UF C3608
5% 20% 20% 4.7UF
16V 4V 4V 20%
2 NP0-C0G 2 X5R 2 X5R
01005 402 2 4V
01005 TANT
C3600 1 C3601 1 C3602 1 C3603 1 1 C3604
402-3
1000PF 0.1UF 0.1UF
10%
6.3V
20% 20% 10UF 0.1UF
4V 4V 20% 10%
X5R-CERM 2 X5R 2 X5R 2 6.3V 6.3V
01005 01005 01005 CERM-X5R 2 2 X5R GND_AUDIO_CODEC
0402-1 19 21 45
201
XW3600
VL C11
VD B11
VCP D11
VP F5
VA G2
SM
1 2
42 37 22 10 5 IN I2C0_SCL_1V8 XW3601
CRITICAL SM
42 37 22 10 5 BI I2C0_SDA_1V8 1 2
U3600
5 OUT IRQ_CODEC_L CS42L63B XW3602
WLCSP-1 SM MIN_LINE_WIDTH=1.0MM
45 37 RST_L63_L 1 2 MIN_NECK_WIDTH=0.2MM GND_AUDIO_HP_AMP 21 22 45
IN
I2C ADDRESS: 1001010X??
C6 SCL HP_DETECT E9 HP_DET 23
IN
C7 SDA HPOUTB G9 HP_R OUT 21 43
E4 INT* HPOUTA G10 HP_L OUT 21 43
E5 RESET* HPOUT_REF F9 HP_REF 21 22

IN
37 AUD_MIK_HS1_INT_L E3 WAKE* LINEOUT1B G8 CODEC_LINE_OUT_R OUT 21 40

OUT
LINEOUT1A F8 CODEC_LINE_OUT_L OUT
C 42 5 IN I2S0_ASP_MCK_R B9 MCLK
LINEOUT1_REF E8 CODEC_LINE_OUT_REF IN
21 40
21 40
C
42 5 I2S0_ASP_LRCK C8 ASP_LRCLK
IN
B7 ASP_SCLK LINEOUT2A D7 LEFT_CH_OUT_P OUT 20 43
42 5 IN I2S0_ASP_BCLK
B8 ASP_SDIN LINEOUT2A_REF E7 LEFT_CH_OUT_REF IN 20 43
42 5 IN I2S0_ASP_DOUT
42 5 I2S0_ASP_DIN R3601 5%
1 2 22 42 I2S_L63_ASP_SDOUT A9 ASP_SDOUT LINEOUT2B F7 RIGHT_CH_OUT_P OUT 20 43
OUT MF
1/32W 01005
C9 VSP_LRCLK LINEOUT2B_REF G7 RIGHT_CH_OUT_REF IN 20 43
42 15 5 IN I2S2_VSP_LRCK
42 15 5 I2S2_VSP_BCLK C10 VSP_SLCLK EAROUT+ G3 NC_EAROUT_AP 46
IN
42 15 5 I2S2_VSP_DOUT A11 VSP_SDIN EAROUT- F3 NC_EAROUT_AN 46
IN
42 15 5 I2S2_VSP_DIN R36025%1 2 22 42 I2S_L63_VSP_SDOUT A10 VSP_SDOUT
OUT MF SPEAKEROUTA+ F6 NC
1/32W 01005
I2S3_XSP_LRCK B6 XSP_LRCLK SPEAKEROUTA- G6
42 5 IN NC
42 5 I2S3_XSP_BCLK A6 XSP_SCLK
IN
A8 XSP_SDIN/DAC2B_MUTE SPEAKEROUTB+ F4 NC
42 5 IN I2S3_XSP_DOUT
22 A7 XSP_SDOUT SPEAKEROUTB- G4 NC
42 5 OUT I2S3_XSP_DIN R36035%1 2
MF
42 I2S_L63_XSP_SDOUT
R36082 22 1/32W 01005
B5 DMIC_SCLK FLYP E11 VHP_FLYP 1 C3617
26 DMIC_SCLK_SENSOR 1 DMIC_SCLK_CODEC
OUT 5% MF
DMIC_SD_CODEC A5 DMIC_SD 2.2UF
1/32W 01005 20%
10V
C5 LINEINA 2 X5R-CERM
46 NC_LINE_IN1_CODEC FLYC F11 402
C4 LINEINA_REF VHP_FLYC
46 NC_LINE_IN1_REF_CODEC 1 C3618
46 NC_LINE_IN2_CODEC D6 LINEINB 2.2UF
R36212 22 D5 LINEINB_REF FLYN G11 VHP_FLYN 20%
10V
26 DMIC_SD_SENSOR 1 46 NC_LINE_IN2_REF_CODEC 2 X5R-CERM
IN 5% MF
1/32W 01005 D4 MIC1_BIAS SPEAKER_VQ E6 SPKR_VQ 402
NOT USING SPEAKER AMPLIFIER WITH SPEAKER LOAD.
46 NC_MIC1_BIAS_CODEC
A3 MIC1 FILT+ G1 FILT_POS
46 NC_MIC1P_CODEC
46 NC_MIC1N_CODEC B3 MIC1_REF
B 46 NC_MIC1_FILT_CODEC E2 MIC1_BIAS_FILT
B
22
EXT_MIC_BIAS C2 MIC2_BIAS
OUT
R3604 1.00K
D3 MIC2_DETECT
43 22 HSMIC_C_P 1 2 MIC2_DET
IN 1% MF
1/32W 01005
43 22
EXT_MIC_P B1 MIC2
IN
43 22 EXT_MIC_REF B2 MIC2_REF
IN
R3605 1.00K MIC2_DET_REF C3 MIC2_DETECT_REF
43 22 IN HSMIC_C_N 1 2
1%
1/32W MIC2_BIAS_FILTC1 MIC2_BIAS_FILT +VCP_FILT D10 VHPPFILT
MF
01005 D2 MIC3A_BIAS -VCP_FILT F10 VHPNFILT
NC
A1 MIC3A
NC
A2 MIC3A_REF 2.2UF
NC RECOMMENDED
D1 MIC3A_BIAS_FILT C3614 1 CRITICAL
NC 1 C3616
10UF
F1 MIC3B_BIAS 20% 4.7UF
NC 6.3V 20%
CERM-X5R 2
A4 MIC3B 0402-1 CRITICAL 2 6.3V
X5R-CERM1
NC 402
1 C3615
B4 MIC3B_REF 4.7UF
NC 1 C3613 20%
E1 MIC3B_BIAS_FILT 10UF 2 6.3V
C3611 1
NC 20%
X5R-CERM1
402
4.7UF 6.3V
E10 GNDCP
20% 2 CERM-X5R
B10 GNDD
F2 GNDA
G5 GNDP
GND
6.3V 0402-1
X5R-CERM1 2
402
A A
D8
D9
C3609 1
SYNC_MASTER=KAVITHA SYNC_DATE=02/03/2011
4.7UF PAGE TITLE
20%
6.3V
X5R-CERM1 2
402
AUDIO: L63B CODEC
DRAWING NUMBER SIZE

REVISION
45 21 19 GND_AUDIO_CODEC R
10.0.0
MIN_NECK_WIDTH=0.2MM NOTICE OF PROPRIETARY PROPERTY: BRANCH
36 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GAIN VDD GND

D 12DB NC SHORT
D
9DB NC 100K
SPEAKER AMPLIFIER 6DB
3DB
SHORT
100K
NC
NC
APN:353S3317) 0DB NC NC
TURN ON TIME: 3.5MS
75HZ +/- XXX% TURN ON DELAY: ?MS
XW3701
SM
35 22 20 19 =PPVCC_MAIN_AUDIO 1 2 MIN_NECK_WIDTH=0.20MM 40 AUD_SPKR_AMP1_PBUS
LEFT CHANNEL IS INVERTED TO FIX CODEC BUG ON LINEOUT2

R37031 1 C3704
A3
CRITICAL C3703 1
0.00 10UF
0.1UF 20%
C3701 10% PVDD 0%
1/32W 2 10V
X5R
0.015UF 6.3V
X5R 2 U3700 MF 0603-1
01005 2
LEFT_CH_OUT_REF 1 2 43 MAX983X4_L_IN_N 201
NDIFPR_BADTERM MAX98304C
43 19 OUT
WLP MIN_LINE_WIDTH=0.50MM
10% CRITICAL C3 IN+ OUT+ A2 SPKRAMP_L_OUT_P MIN_NECK_WIDTH=0.20MM 20 43
6.3V OUT
X5R C2 IN- OUT- A1 SPKRAMP_L_OUT_N
R3701 0201 C3702 MIN_LINE_WIDTH=0.50MM OUT 20 43
LEFT_CH_P 0.015UF MAX983X4_L_IN_P CRITICAL MIN_NECK_WIDTH=0.20MM

100 43 43
C1 SHDN*
43 19 IN LEFT_CH_OUT_P 2 1 1 2 GAIN B3
1%
10% B2 NC MAX983X4_L_GAIN
1/32W
MF 6.3V NC
01005 X5R
0201
C 20 5 IN AUD_SPKRAMP_MUTE_L PGND C
B1
1 R37001 GAIN:6DB L3700
R3702 100K 240-OHM-0.2A-0.8-OHM
0.00 5%
0% 1/32W 6 OUT SPK_ID 1
0201
2 SPK_ID_FILT
1/32W MF
MF 01005 2 XW3700
01005 2 SM MAY NEED TUNING FOR THESE FILTERS
1 2 45 GND_SPKR_AMP1
1 C3700 SPEAKER CONNECTOR
MIN_LINE_WIDTH=0.30MM 27PF APN 518S0672
MIN_NECK_WIDTH=0.20MM 5%
25V
2 NP0-C0G CRITICAL
0201 J3700
78171-6006
M-RT-SM
7
43 20 SPKRAMP_L_OUT_P 1
43 20 SPKRAMP_L_OUT_N 2
3
4
L63 LINEOUT2A IS CONNECTED TO U3700 43 20 SPKRAMP_R_OUT_P 5
L63 LINEOUT2B IS CONNECTED TO U3710 43 20 SPKRAMP_R_OUT_N 6
NOSTUFF NOSTUFF
CRITICAL CRITICAL 8
1 C3750 1 C3752
XW3711 100PF 100PF
5% 5%
SM 16V 16V
MIN_LINE_WIDTH=0.30MM 2 NP0-C0G 2 NP0-C0G
35 22 20 19 =PPVCC_MAIN_AUDIO 1 2 40 AUD_SPKR_AMP2_PBUS MIN_NECK_WIDTH=0.20MM 01005 01005
NOSTUFF NOSTUFF
1 CRITICAL CRITICAL
R3713 C3751 1 C3753 1
B 0.00 1 C3714 B
A3
C3713 1 0% 100PF 100PF
1/32W 10UF 5% 5%
0.1UF PVDD MF 20% 16V
2
16V
2
CRITICAL 10%
6.3V 01005 2 2 10V
X5R
NP0-C0G
01005
NP0-C0G
01005
2
C3711 X5R
201
U3710 0603-1
R3711 0.015UF MAX98304C
100 WLP MIN_LINE_WIDTH=0.50MM
43 19 RIGHT_CH_OUT_P 2 1 43 RIGHT_CH_P 1 2 43 MAX983X4_R_IN_P C3 IN+ OUT+ A2 SPKRAMP_R_OUT_P MIN_NECK_WIDTH=0.20MM 20 43
IN OUT
1% CRITICAL C2 IN- OUT- A1 SPKRAMP_R_OUT_N 20 43
1/32W 10% OUT
6.3V MIN_LINE_WIDTH=0.50MM
MF
01005 X5R C3712 C1 SHDN*
CRITICAL MIN_NECK_WIDTH=0.20MM
0201 0.015UF GAIN B3 MAX983X4_R_GAIN
43 19 OUT RIGHT_CH_OUT_REF 1 2 43 MAX983X4_R_IN_N B2 NC
NC
10%
6.3V
X5R
0201 PGND
20 5 AUD_SPKRAMP_MUTE_L
B1
GAIN:6DB
R37121
0.00
0% XW3710
1/32W SM
MF MIN_LINE_WIDTH=0.30MM
01005 2 1 2 MIN_NECK_WIDTH=0.20MM 45 GND_SPKR_AMP2
A SYNC_MASTER=KAVITHA SYNC_DATE=02/03/2011 A
PAGE TITLE
AUDIO: SPEAKER AMP

DRAWING NUMBER SIZE

REVISION
R
10.0.0
37 OF 157
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
HEADPHONE OUTPUT ZOBEL NETWORK

XW3851
D 43 19 IN
HP_L 1
SM
2 AUD_HP1_MLBCON_L OUT 23 43
D
XW3850
SM
HP_R 1 2 AUD_HP1_MLBCON_R
43 19 IN OUT 23 43
R38501 1
R3851
100 100
1% 1%
1/32W 1/32W
MF
01005 2
MF
2 01005
1 C3853 1 C3852
27PF 27PF
5% 5%
2 16V 16V
HP_ZL
2 NP0-C0G
HP_ZR
NP0-C0G
01005 01005
C3850 1 1 C3851
33000PF 33000PF
10% 10%
6.3V 2 2 6.3V
X5R X5R
201 201
45 22 19 GND_AUDIO_HP_AMP
22 19 OUT HP_REF IN
C 1 C3854
C
27PF
5%
16V
2 NP0-C0G
01005
DOCK LINE OUTPUT

XW3800
SM MIN_LINE_WIDTH=0.1MM
40 19 CODEC_LINE_OUT_REF 1 2 MIN_NECK_WIDTH=0.07MM AV_EMI_DIFF_SENSE 27
OUT IN
R3800
100 MIN_LINE_WIDTH=0.1MM
40 19 IN CODEC_LINE_OUT_L 2 1 MIN_NECK_WIDTH=0.07MM AUDIO_EMI_LO_L OUT 27
MIN_NECK_WIDTH=0.07MM 01005
B B
R3801 MIN_LINE_WIDTH=0.1MM
CODEC_LINE_OUT_R 2
100 1 MIN_NECK_WIDTH=0.07MM AUDIO_EMI_LO_R
40 19 IN OUT 27
MIN_NECK_WIDTH=0.07MM 01005
1 C3801
15PF
CODEC 5%
16V
2 NP0-C0G-CERM
C3803
15PF
1
DOCK
01005 5%
16V
NP0-C0G-CERM 2
01005
C3802 1
15PF
5%
16V
NP0-C0G-CERM 2
01005
XW3803
SM
MIN_LINE_WIDTH=0.6MM GND_AUDIO_PT_DK
45 19 GND_AUDIO_CODEC 1 2 MIN_NECK_WIDTH=0.2MM IN 27 45
PAGE TITLE
AUDIO: HEADPHONE OUT

DRAWING NUMBER SIZE

REVISION
R
10.0.0
38 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
EXTERNAL (HEADSET) MIC INPUT CIRCUITRY

NOSTUFF
R4211
=PP3V0_S2R_HALL_CHSW 1
0 2
35
5%
1/20W
MF
201
PPVDD_CHSW
1 C4200 NET_SPACING_TYPE=PWR
R4210 0.1UF VOLTAGE=4.6V
10%
=PPVCC_MAIN_AUDIO 0 2 6.3V CHS_CLAMPI
A1
35 20 19 1 2 X5R
201
5%
1/20W
MF VDD
201
U4200 R4203 R4202 R4201
2.2K 2 2.2K 2 1K
TS3A8235YFP 1 1 1 2 EXT_MIC_BIAS IN 19
WCSP 1% 1% 1%
C RAMPI D4
1/20W
MF
201
1/20W
MF
201
1/20W
MF
201 HSMIC_C_P OUT 19 43
C
CRITICAL
RAMPO D3 C4211 R4212
CLAMPI C4 0.1UF 470
1 2 43 HSMIC_R_P 1 2 EXT_MIC_P OUT 19 43
40 23 IN AUD_HS_MIC1_HI 1%
CLAMPO B4 CHS_CLAMPO 10% 1/20W
NOSTUFF 6.3V MF
(HSMIC_C_P)
X5R
201
201 1 C4217
B1 MIC1 MIC D2 1 C4202 1 C4201 1000PF
10%
FROM HEADSET
C4216 1
33PF
C4212
15PF
1 C1 MIC2 REF D1 (HSMIC_C_N) 10UF
20%
6.3V
10UF
20%
6.3V
2 16V
X7R
201
TO CODEC
5% 5% 2 CERM-X5R 2 CERM-X5R
16V 16V
NP0-C0G-CERM 2 NP0-C0G-CERM 2 SCL A3 0402-1 0402-1 C4213
01005 01005 A4 0.1UF R4213
SDA
1 2 43 HSMIC_R_N 1
470 2 EXT_MIC_REF
ADDR A2 OUT 19 43
40 23 IN AUD_HS_MIC2_HI R4204NOSTUFF 1%
10% 1/20W
0
GND2
GND1
6.3V MF
CHS_CAP_REF
1 2 X5R
GND 201
201
5%
1/20W HSMIC_C_N OUT 19 43
MF
C3
B3
B2
C2
201
40 23 AUD_HS_MIC2_RET I2C0_SCL_1V8 5 10 19 37 42
IN
I2C0_SDA_1V8 5 10 19 37 42
40 23
AUD_HS_MIC1_RET
IN
R4205
GND_AUDIO_HP_AMP 1
0 2
45 21 19
5%
EXT MIC LPF FC = 677KHZ
1/20W
MF
201
B B
XW4200
SM
HP_REF
1 2 19 21
OUT
PAGE TITLE
AUDIO: DETECT/MIC BIAS

DRAWING NUMBER SIZE

REVISION
R
10.0.0
42 OF 157
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
D D
HEADPHONE JACK CONNECTION IS ON FRONT PANEL FLEX, CSA 55/PDF 29
PLACE ALL COMPONENTS NEAR J5401

L4307
30-OHM-1.7A
40 24 CONN_AUD_HEADSET_CHS_MIC2 1 2 AUD_HS_MIC2_HI 22 40
IN OUT
MIN_LINE_WIDTH=0.1MM 0402 MIN_LINE_WIDTH=0.1MM
MIN_NECK_WIDTH=0.05MM CRITICAL MIN_NECK_WIDTH=0.05MM
L4308
30-OHM-1.7A
40 24 CONN_AUD_HEADSET_CHS_RET2 1 2 AUD_HS_MIC2_RET 22 40
IN OUT
MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM
L4301
30-OHM-1.7A
24 CONN_AUD_HEADSET_CHS_MIC1 1 2 AUD_HS_MIC1_HI 22 40
IN OUT
L4302
30-OHM-1.7A
24 CONN_AUD_HEADSET_CHS_RET1 1 2 AUD_HS_MIC1_RET 22 40
IN OUT
L4303
240-OHM-0.2A-0.8-OHM
C 40 24 IN CONN_AUD_HEADSET_DET 1
0201
2 AUD_HP1_DET_H OUT 23 40
C
CRITICAL
L4304
30-OHM-1.7A
43 24 CONN_AUD_HEADSET_RIGHT 1 2 AUD_HP1_MLBCON_R 21 43
OUT IN
L4306
30-OHM-1.7A
43 24 CONN_AUD_HEADSET_LEFT 1 2 AUD_HP1_MLBCON_L 21 43
OUT IN
HEADSET JACK INSERTION DETECT

R4312
B 40 23 IN AUD_HP1_DET_H 1
3.3K 2
HP_DET OUT 19 B
5%
1/32W
NOSTUFF
MF
01005
1 C4310
4700PF
10%
2 10V
X7R
201
PAGE TITLE
AUDIO: HP/MIC FILTERS

DRAWING NUMBER SIZE

REVISION
R
10.0.0
43 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
APN: 518S0828
CRITICAL
J5400
502250-8037
F-RT-SM
40
38
25 PM_REAR_CAM_SHUTDOWN_FILT 1
2 PM_FRONT_CAM_SHUTDOWN_FILT 25
42 25 10 I2C2_SCL_3V0_ALS 3
4 I2C2_SDA_3V0_ALS 10 25 42
5
6 IRQ_ALS_INT_CONN_L 25
42 25 I2C1_SCL_1V8_CONN 7
8 I2C1_SDA_1V8_CONN 25 42
26 DMIC_DATA_CONN 9
10 DMIC_CLK_CONN 26
42 25 ISP_CAM_0_SCL 11
12 ISP_CAM_0_SDA 25 42
25 CONN_IRQ_HALL 13
14 PP3V0_S2R_HALL_FLT 26 45
15
16 CAM0_RESET_L_FLT 26
17
NC 18
19 NC
NC 20
21 NC
NC 22
23 NC
24 PP3V0_SENSOR_FLT 10 26 45
25
26 PP1V8_SENSOR_FLT 26 45
27
28 PP2V85_CAM_FLT 26 45
29
30
C 43 25 MIPI0C_CAM_DATA_P<0>
31
33
32
CLK_CAM_RF_CONN
MIPI0C_CAM_DATA_N<0>
25 42
25 43
CAM CLOCK 0
C
34
43 25 MIPI0C_CAM_DATA_N<1> 35
36 MIPI0C_CAM_DATA_P<1> 25 43
37
39
41
APN: 518S0828
CRITICAL
J5401
502250-8037
F-RT-SM
40
38
1
NC 2
3 NC
4
NC
B 43 25 MIPI0C_CAM_CLK_N
NC
5
7
6
8
B
MIPI0C_CAM_CLK_P 25 43
9
10 CLK_CAM_FF_CONN 25 42 CAM CLOCK 1
42 25 ISP_CAM_1_SCL 11
12 ISP_CAM_1_SDA 25 42
13
14 MIPI1C_CAM_CLK_P 25 43
43 25 MIPI1C_CAM_CLK_N 15
16
43 25 MIPI1C_CAM_DATA_N<0> 17
18 MIPI1C_CAM_DATA_P<0> 25 43
19
20 CONN_IRQ_GYRO_INT2 26
26 CONN_IRQ_PROX_INT_L 21
22 SRL_L 5 37
37 5 ONOFF_L 23
24 AUD_VOL_UP_L 5
5 AUD_VOL_DOWN_L 25
26
27 NC
NC 28 CONN_IRQ_ACCEL_INT2_L 26
26 CONN_IRQ_ACCEL_INT1_L 29
30 CONN_IRQ_GYRO_INT1 26
40 23 CONN_AUD_HEADSET_DET 31
32 CONN_AUD_HEADSET_LEFT 23 43
43 23 CONN_AUD_HEADSET_RIGHT 33
34 CONN_AUD_HEADSET_CHS_RET1 23
40 23 CONN_AUD_HEADSET_CHS_MIC2 35
36 CONN_AUD_HEADSET_CHS_RET2 23 40
23 CONN_AUD_HEADSET_CHS_MIC1 37
39
41
A SYNC_MASTER=MARK SYNC_DATE=01/11/2011 A
PAGE TITLE
CONNECTOR: SENSOR
DRAWING NUMBER SIZE

REVISION
R
10.0.0
54 OF 157
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
R5510
1 2
0 NOSTUFF
5% MF
R5620
1 2
0 NOSTUFF
1/20W 201
D
5%
1/20W
MF
201 L5500
90-OHM-50MA
D
TCM0605-1
L5620 SYM_VER-1
90-OHM-50MA
TCM0605-1
SYM_VER-1
43 7 IN MIPI1C_AP_CLK_P 1 4 MIPI1C_CAM_CLK_P OUT 24 43
43 7 MIPI0C_AP_DATA_N<1> 1 4 MIPI0C_CAM_DATA_N<1> 24 43
BI BI
43 7 IN MIPI1C_AP_CLK_N 2 3 MIPI1C_CAM_CLK_N OUT 24 43
MIPI0C_AP_DATA_P<1> 2 3 MIPI0C_CAM_DATA_P<1>
43 7 BI BI 24 43
R5511
1 2
0
R5621
1 2
0 5% MF
1/20W 201 NOSTUFF
5% MF
1/20W 201 NOSTUFF
R5512
1
0
2
NOSTUFF
R5610
1 2
0 NOSTUFF 5% MF
1/20W 201
5% MF
1/20W 201
L5501
90-OHM-50MA
L5600 TCM0605-1
90-OHM-50MA SYM_VER-1
TCM0605-1
SYM_VER-1
43 7 BI MIPI1C_AP_DATA_P<0> 1 4 MIPI1C_CAM_DATA_P<0> BI 24 43
43 7 MIPI0C_AP_DATA_N<0> 1 4 MIPI0C_CAM_DATA_N<0> 24 43
BI BI
43 7 BI MIPI1C_AP_DATA_N<0> 2 3 MIPI1C_CAM_DATA_N<0> BI 24 43
43 7 MIPI0C_AP_DATA_P<0> 2 3 MIPI0C_CAM_DATA_P<0> 24 43
BI BI
R5611
1 2
0 R5513
1
02
5% MF 5% MF
1/20W 201 NOSTUFF 1/20W 201 NOSTUFF
R5612
1 2
0 NOSTUFF
5% MF
1/20W 201
C L5601
90-OHM-50MA
C
TCM0605-1
SYM_VER-1
43 7 MIPI0C_AP_CLK_N 1 4 MIPI0C_CAM_CLK_N 24 43
IN OUT
43 7 MIPI0C_AP_CLK_P 2 3 MIPI0C_CAM_CLK_P 24 43
IN OUT
R5613
1 2
0
5% MF
1/20W 201 NOSTUFF
800MHZ-100MA-27PF
U5500
0603
5 OUT IRQ_ALS_INT_L 1 IN1 OUT1 5 IRQ_ALS_INT_CONN_L IN 24
42 5 IN I2C2_SCL_3V0 2 IN2 OUT2 6 I2C2_SCL_3V0_ALS OUT 10 24 42
42 5 BI I2C2_SDA_3V0 3 IN3 OUT3 7 I2C2_SDA_3V0_ALS BI 10 24 42
4 IN4 OUT4 8 CLK_CAM_FF_CONN OUT 24 42

R5600 R5602 GND
22 22
42 7 IN CLK_CAM_FF 1 2 42 CLK_CAM_FF_C 1 2 42 CLK_CAM_FF_FILT
9
10
5% NOSTUFF 5%
1/16W 1/16W
22 OHM MF-LF MF-LF
402 1 C5500 402
B PLACE IT NEAR H4
5%
100PF
25V
B
2 CERM
U5502
800MHZ-100MA-27PF
201
0603
42 10 5 IN I2C1_SCL_1V8 1 IN1 OUT1 5 I2C1_SCL_1V8_CONN OUT 24 42
42 10 5 BI I2C1_SDA_1V8 2 IN2 OUT2 6 I2C1_SDA_1V8_CONN BI 24 42
NC 3 IN3 OUT3 7 NC
NC 4 IN4 OUT4 8 NC
GND
9
10
35 25 =PP1V8_CAM
NOSTUFF
1
35 25 =PP1V8_CAM R5501
NOSTUFF 100K
1
5%
1/20W
U5501
800MHZ-100MA-27PF
R5502 MF
2 201
0603
100K
5% 37IRQ_HALL
OUT 1 IN1 OUT1 5 CONN_IRQ_HALL OUT 24
1/20W
MF U5503 42 7 BI ISP_AP_1_SDA 2 IN2 OUT2 6 ISP_CAM_1_SDA BI 24 42
2 201 800MHZ-100MA-27PF 7 PM_FRONT_CAM_SHUTDOWN 3 IN3 OUT3 7 PM_FRONT_CAM_SHUTDOWN_FILT 24
0603 IN OUT
42 7 IN ISP_AP_1_SCL 4 IN4 OUT4 8 ISP_CAM_1_SCL OUT 24 42
42 7 BI ISP_AP_0_SDA 1 IN1 OUT1 5 ISP_CAM_0_SDA BI 24 42
7 IN PM_REAR_CAM_SHUTDOWN 2 IN2 OUT2 6 PM_REAR_CAM_SHUTDOWN_FILT OUT 24

GND
ISP_AP_0_SCL 3 OUT3 7 ISP_CAM_0_SCL
9
10
42 7 IN IN3 OUT 24 42
4 IN4 OUT4 8 CLK_CAM_RF_CONN BI 24 42
R5601 R5603 GND

A CLK_CAM_RF 1
22 2 CLK_CAM_RF_C 1
22 2 CLK_CAM_RF_FILT SYNC_MASTER=MARK SYNC_DATE=01/11/2011 A
9
10
42 7 42 42
IN
5% 5% PAGE TITLE
1/16W 1/16W
MF-LF
402
MF-LF
402
SENSOR PANEL FILTERS 1
22 OHM DRAWING NUMBER SIZE
NOSTUFF
PLACE IT NEAR H4
1 C5501 REVISION
100PF R
10.0.0
5%
2 25V
CERM TABLE_ALT_HEAD
201
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: THE INFORMATION CONTAINED HEREIN IS THE
PART NUMBER PROPRIETARY PROPERTY OF APPLE INC.
TABLE_ALT_ITEM
155S0643 155S0373 ?
U5502,U5503,U5500,U5501,U5600,U5601
RADAR:8376668 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
55 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U5600
800MHZ-100MA-27PF
D 19 IN DMIC_SCLK_SENSOR 1 IN1
0603
OUT1 5 DMIC_CLK_CONN OUT 24
D
19 OUT DMIC_SD_SENSOR 2 IN2 OUT2 6 DMIC_DATA_CONN IN 24
7 IN CAM0_RESET_L 3 IN3 OUT3 7 CAM0_RESET_L_FLT OUT 24
5 OUT IRQ_PROX_INT_L 4 IN4 OUT4 8 CONN_IRQ_PROX_INT_L IN 24
GND
9
10
U5601
800MHZ-100MA-27PF
0603
5 OUT IRQ_GYRO_INT2 1 IN1 OUT1 5 CONN_IRQ_GYRO_INT2 IN 24
5 OUT IRQ_GYRO_INT1 2 IN2 OUT2 6 CONN_IRQ_GYRO_INT1 IN 24
5 OUT IRQ_ACCEL_INT1_L 3 IN3 OUT3 7 CONN_IRQ_ACCEL_INT1_L IN 24
5 OUT IRQ_ACCEL_INT2_L 4 IN4 OUT4 8 CONN_IRQ_ACCEL_INT2_L IN 24
GND
9
10
C C
L5610
240-OHM-0.2A-0.8-OHM
35 =PP3V0_S2R_HALL 1 2 PP3V0_S2R_HALL_FLT 24 45
0201 VOLTAGE=3.0V
MIN_LINE_WIDTH=0.6 mm
1 C5601 1 C5602 1 C563 MIN_NECK_WIDTH=0.2 mm
82PF 1UF 1000PF MAX_NECK_LENGTH=3 MM
5% 10% 10%
25V
2 CERM 2 10V 2 16V
X5R X7R
0201 402-1 201
L5611
240-OHM-25%-400MA
35 =PP1V8_SENSOR 1 2 PP1V8_SENSOR_FLT 24 45
B 0402
DCR 0.31 1 C5612 1 C5613 1 C5620
VOLTAGE=1.8V
MIN_NECK_WIDTH=0.2 mm
B
82PF 1UF 1000PF NET_SPACING_TYPE=PWR
5% MAX_NECK_LENGTH=3 MM
10% 10%
25V
2 CERM
10V
2 X5R
16V
2 X7R
0201 402-1 201
L5613
240-OHM-25%-400MA
35 =PP2V85_CAM 1 2 PP2V85_CAM_FLT 24 45
0402 VOLTAGE=2.85V
DCR 0.31 1 C5617 1 C5618 1 C5621 MIN_LINE_WIDTH=0.6 mm
82PF 1UF 1000PF NET_SPACING_TYPE=PWR
5% 10% 10% MAX_NECK_LENGTH=3 MM
25V
2 CERM 10V
2 X5R 2 16V
X7R
0201 402-1 201
L5612
240-OHM-25%-400MA
35 =PP3V0_OPTICAL 1 2 PP3V0_SENSOR_FLT 10 24 45
0402 VOLTAGE=3.0V
DCR 0.31 MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
1 C5614 1 C5615 1 C5616 1 C5623 NET_SPACING_TYPE=PWR
82PF 1UF 0.1UF 1000PF
5% 10% 10% 10%
2 25V 10V 2 6.3V 16V
A CERM
0201
2 X5R
402-1
X5R
201
2 X7R
201 SYNC_MASTER=MARK SYNC_DATE=01/11/2011 A
PAGE TITLE
SENSOR PANEL FILTERS 2

DRAWING NUMBER SIZE

REVISION
R
10.0.0
56 OF 157
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
VOLTAGE=5.0V
L5757
USB MIN_LINE_WIDTH=4.1MM
FERR-70-OHM-4A
JTAG
35 PPVBUS_USB_EMI 1 2 MAX_NECK_LENGTH=3 MM
PPVBUS_USB_PT_DK_CON 29 45
ANALOG VIDEO FL5711 DEVELOPMENT_JTAG (JTAG_TCK)
0603 80-OHM-0.2A-0.4-OHM 42 4 JTAG_AP_TCK R5730 1 2 0 PT_DK_CON_P14 28
2 IN
1 C5721 1 C5722 1
R5790 DZ5760 1 C5750 1 C5783 43 11 10 IN VIDEO_EMI_CVBS_PB 1 2 VIDEO_PT_DK_CON_CVBS_PB 27 28 43 42 4 IN JTAG_AP_TMS R5731 1 2 0 PT_DK_CON_P17 28
27PF 12PF 100K 27V-100PF 27PF 0.01UF 0201 DEVELOPMENT_JTAG (JTAG_TMS)
5% 5% 5% 0402 5% 10%
2 25V
NP0-C0G 2 25V
NP0-C0G-CERM 1/20W 2 25V
NP0-C0G 2 25V
X7R FL5707
0201 0201 MF 0201 402 80-OHM-0.2A-0.4-OHM DEVELOPMENT_JTAG
2 201 1 1
43 11 10 IN VIDEO_EMI_C_Y 1 2 VIDEO_PT_DK_CON_C_Y 27 28 43
R5795 DEVELOPMENT_JTAG
0201
523K
1%
1/32W U5730
L5716 NOTE: MAX CONTINUOUS VOLTAGE IS 19V - SPEC IS 16V FL5708 MF MAX9061
D 35-OHM-50MA
TCM0605
80-OHM-0.2A-0.4-OHM
1 2 39 35 5
=PP1V8_S2R_MISC 2 01005
B1 REF
UCSP D
SYM_VER-1 43 11 10 IN VIDEO_EMI_Y_PR VIDEO_PT_DK_CON_Y_PR 27 28 43
42 4 USB_DK_D0_P 1 4 USB_PT_DK_CON_D_P 29 42
0201 U5730_IN A2 IN OUT A1 RST_AP_L 4 30 37 45
BI OUT
DEVELOPMENT_JTAG
VIDEO_PT_DK_CON_Y_PR 27 28 GND
USB_DK_D0_N 2 3 USB_PT_DK_CON_D_N VIDEO_PT_DK_CON_C_Y
43 1 C5730
B2
42 4 BI 29 42 27 28
0.1UF DEVELOPMENT_JTAG
43
10% 1
D5703_6 VIDEO_PT_DK_CON_CVBS_PB 27 28
43 2 6.3V
X5R
R5796
AV_PT_DK_CON_RET 29 201 1.00M
1%
6 1/32W
VBUS NOSTUFF NOSTUFF MF
IO 4 OMIT U5700 1 C5705 1 C5707 2 01005
NUP412VP5XXG 27PF 27PF
5 IO NC 3 1 C5703 XW5700 SOT953 5% 5% NOTE:
27PF SM 25V 25V
2 NC 2 NP0-C0G 2 NP0-C0G JTAG_AP_TMS = 3.3V: U5730’S IN = 2.13V
5% 27 AUDIO_PT_DK_RET 1 2 1 5
2 25V 0201 NOSTUFF 0201 NOSTUFF JTAG_AP_TMS = 1.8V: U5730’S IN = 1.16V
D5703 NP0-C0G
0201
RCLAMP0502N 2 1 C5706 1 C5708
1 27PF 27PF
SLP1210N6
1
GND
NOTE: R5700 ADDED TO PROVIDE R5700 3 4 5% 5%
0.200 2 25V
NP0-C0G 2 25V
NP0-C0G
SEPARATION BETWEEN AUDIO AND 1%
VIDEO RETURN CURRENT
1/20W
MF
0201 0201
LINEOUT
2 201
L5760 MIN_LINE_WIDTH=0.1MM
FERR-120-OHM-1.5A MIN_NECK_WIDTH=0.07MM
AUDIO_EMI_LO_L 1 2 AUDIO_PT_DK_CON_LO_L
ACCESSORY 21 IN
0402A
29
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.3MM 2 NOSTUFF
L5714 MIN_NECK_WIDTH=0.1MM
DZ5710 1 C5710
FERR-120-OHM-1.5A MAX_NECK_LENGTH=3 MM
UCLAMP0511Z 27PF
35 =PP3V3_PORT_ACC 1 2 ACC_PT_DK_CON_PP3V3 29 45 0201 5%
25V
0402A 2 NP0-C0G
C 0.095 OHM DCR

2
DZ5790 1 C5751 1 C5782 DISPLAYPORT
1 0201
C
8V-100PF 27PF 0.01UF
0201 5% 10%
2 25V 2 10V
NP0-C0G
0201
X5R
201
L5700
12-OHM-100MA-8.5GHZ
1
TCM0806-4SM L5761 MIN_LINE_WIDTH=0.1MM
SYM_VER-1
FERR-120-OHM-1.5A MIN_NECK_WIDTH=0.07MM
43 28 DP_EMI_TX_P<0> 1 4 DP_PT_DK_CON_TX_P<0> 29 43
IN AUDIO_EMI_LO_R 1 2 AUDIO_PT_DK_CON_LO_R
21 IN 29
35 =PPVCC_MAIN_DOCK 0402A
43 28 DP_EMI_TX_N<0> 2 3 DP_PT_DK_CON_TX_N<0> 29 43 2 NOSTUFF

IN
1
R5750 D5700_6 DZ5711 1 C5711
220K UCLAMP0511Z 27PF
5% 0201 5%
1/20W 6 25V
MF 2 NP0-C0G
VBUS 1 0201
2 201
IO 4 1 C5700
R5751 5 IO NC 3 5%
27PF
1
10K 2 ACC_PT_DK_CON_DET_L 2 NC 25V
37 OUT PORT_DOCK_ACC_DET_L 29 2 NP0-C0G
5% 0201
1/20W 2 D5700 L5762 MIN_LINE_WIDTH=0.1MM
MF 1 C5752 RCLAMP0502N 22-OHM-25%-900MA MIN_NECK_WIDTH=0.07MM
201 DZ5753 27PF SLP1210N6 GND
6.8V-100PF 5%
1 21 IN AV_EMI_DIFF_SENSE 1 2 AV_PT_DK_CON_DIFF_SENSE 29
0201 2 25V
NP0-C0G 0201
0201
1
2
NOSTUFF
1 C5712
DZ5712 27PF
L5701 6.8V-100PF 5%
25V 1
R5752
12-OHM-100MA-8.5GHZ
TCM0806-4SM
0201 2 NP0-C0G
0201
R5740
PLACE BY PMU SYM_VER-1
1 150
PMU_ADC_REF
100K 2 1 4 5%
37 1 43 28 IN DP_EMI_TX_P<1> DP_PT_DK_CON_TX_P<1> 29 43 1/20W
MF
1/20W 201
2 201
B R5753
MF 1%
43 28 IN DP_EMI_TX_N<1> 2 3 DP_PT_DK_CON_TX_N<1> 29 43
B
10K D5701_6
L5763
1 2 ACC_PT_DK_CON_ID 30-OHM-1.7A
37 OUT PORT_DOCK_ACCID 29
5% C 45 21 GND_AUDIO_PT_DK 1 2 AUDIO_PT_DK_RET 27
1/20W 0201-1 6 IN
1 MIN_LINE_WIDTH=0.6MM
MF
201
C5760 14.2V-6PF 1 C5753 VBUS 0402
0.01UF DZ5752 27PF IO 4
2 10%
16V A
5%
2 25V 5 IO NC 3
1 C5701
X5R-CERM NP0-C0G 27PF
0201 0201 2 NC 5%
2 25V
NP0-C0G
D5701 0201
RCLAMP0502N
SLP1210N6 GND
1
FIREWIRE DETECT/ DISPLAYPORT HPD
R5720 R5710
0
42 11 IN USB11_ACC_TX_N 1 2 ACC_PT_DK_CON_TX 29 42
1
47K 2
37 OUT FW_ZENER_PWR FW_PT_DK_CON_PWR 29
5% NOSTUFF
1/20W 5%
MF 1 C5754 1/20W 1 C5780
201
27PF L5702 2 MF
0.01UF
A1 B1 35-OHM-50MA 201
5%
25V TCM0605 DZ5720 10%
50V
2 NP0-C0G SYM_VER-1 GDZT2R5.1B 2 X7R
DZ5751 0201 43 28 IN DP_EMI_AUX_P 1 4 DP_PT_DK_CON_AUX_P 29 43 1
GDZ-0201 402
USBULC6-2F3
BGA
43 28 DP_EMI_AUX_N 2 3 DP_PT_DK_CON_AUX_N 29 43
A2 B2 IN
D5702_6
TABLE_ALT_HEAD

R5721 6 PART NUMBER
0
A VBUS
A
TABLE_ALT_ITEM
42 11 USB11_ACC_RX_P 1 2 ACC_PT_DK_CON_RX 29 42 377S0090 377S0081 DZ5751 RADAR:8972666

OUT IO 4 SYNC_MASTER=JOE SYNC_DATE=01/19/2011
5%
1/20W
NOSTUFF 5 IO NC 3
1 C5702 DZ5710,DZ5711 TABLE_ALT_ITEM
PAGE TITLE
27PF 377S0111 377S0099 RADAR:8849707
MF
201
1 C5755 2 NC 5% IO FLEX: DOCK COMPONENTS
27PF
TABLE_ALT_ITEM
D5700,D5701,D5702,D5703
25V
5% 2 NP0-C0G 377S0107 377S0066 RADAR:8947642
DRAWING NUMBER SIZE
2 25V D5702 0201 TABLE_ALT_ITEM
NP0-C0G
0201 RCLAMP0502N 155S0625 155S0559 L5700,L5701 RADAR:8423156
SLP1210N6 GND TABLE_ALT_ITEM
REVISION
1 377S0116 377S0108 DZ5760 RADAR:8370432 R
TABLE_ALT_ITEM
10.0.0
155S0725 155S0276 FL0600, FL5707, FL5708, FL5711 QTY 4 RADAR:9625553 NOTICE OF PROPRIETARY PROPERTY: BRANCH
TABLE_ALT_ITEM

155S0513 155S0320 L5762 RADAR:9625601 PROPRIETARY PROPERTY OF APPLE INC.
57 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PLACEMENT NOTE: NEAR U0600

DISPLAYPORT AC COUPLING
DP_AP_TX_P<0> OUT 7 28 43
DP_AP_TX_N<0> OUT 7 28 43
43 28 7 IN DP_AP_TX_P<0> C5802 1 2 DP_EMI_TX_P<0> OUT 27 43

DP_AP_TX_P<1> OUT 7 28 43 10% 6.3V X5R 201 35 6 =PP3V0_IO_MISC
0.1UF
DP_AP_TX_N<1>OUT 7 28 43
43 28 7 IN DP_AP_TX_N<0> C5803 1 2 DP_EMI_TX_N<0> OUT 27 43
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY 10% 6.3V X5R 201
NOSTUFF NOSTUFF NOSTUFF NOSTUFF 0.1UF
1
R1250 1
R1251 1
R1252 1
R1253 43 28 7 IN DP_AP_TX_P<1> C5804 1 2 DP_EMI_TX_P<1> OUT 27 43
1
R5820
10% 6.3V X5R 201
D 5%
150
1/20W
5%
150
1/20W
150
5%
1/20W
150
5%
1/20W 43 28 7 IN DP_AP_TX_N<1>
0.1UF
C5805 1 2 DP_EMI_TX_N<1> OUT 27 43
100K
1%
1/32W
D
MF MF MF MF 10% 6.3V X5R 201 MF
0.1UF
2 201 2 201 2 201 2 201 2 01005
DP_TERM_C1250 DP_TERM_C1251
43 7 IN DP_AP_TX_N<2> C5808 1 2 DP_PT_DK_CON_TX_N<2> OUT 28 43
DP_EMI_AUX_N
10% 6.3V X5R 201 43 28 27
0.1UF
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
NOSTUFF NOSTUFF
DP_AP_TX_P<2> C5809 1 2 DP_PT_DK_CON_TX_P<2>
1 C1250 1 C1251 43 7 IN
0.1UF
10% 6.3V X5R 201
OUT 28 43
43 28 27 DP_EMI_AUX_P
100PF 100PF
5% 5%
25V
2 CERM
25V
2 CERM 43 7 IN DP_AP_TX_N<3> C5810 1 2 DP_PT_DK_CON_TX_N<3> OUT 28 43
1
201 201 0.1UF
10% 6.3V X5R 201 R5823
100K
1%
43 7 IN DP_AP_TX_P<3> C5811 1 2 DP_PT_DK_CON_TX_P<3> OUT 28 43 1/32W
10% 6.3V X5R 201 MF
0.1UF
2 01005
STUFFING OPTIONS FOR DP LANES 2, 3 FOR STEVENOTE.
ALTERNATE PINOUT FOR JTAG R5911 ALTERNATE PINOUT FOR JTAG R5913 43 7 BI DP_AP_AUX_P C5806 1 2 DP_EMI_AUX_P BI 27 28 43
2
0 1 2
0 1
10% 6.3V X5R 201
29 PT_DK_CON_P15_R 29 PT_DK_CON_P16_R 0.1UF
1/20W 5% MF 201 1/20W 5% MF 201 43 7 BI DP_AP_AUX_N C5807 1 2 DP_EMI_AUX_N BI 27 28 43
10% 6.3V X5R 201
SNOTE SNOTE 0.1UF
PLACE NEAR J5900. PLACE NEAR J5900.
R59101 R59121 C
C 5%
0
5%
0
1/20W 1/20W
MF MF
201 2 201 2
DEVELOPMENT_JTAG DEVELOPMENT_JTAG
R5900 R5902
0 0 PT_DK_CON_P17
29 PT_DK_CON_P14_R 2 1 PT_DK_CON_P14 27 29 PT_DK_CON_P17_R 2 1 27
1/20W 5% MF 201 1/20W 5% MF 201

R5901 R5903
2
0 1
DP_PT_DK_CON_TX_N<2>
2
0 1
DP_PT_DK_CON_TX_P<2>
28 43 28 43
1/20W 5% MF 201 1/20W 5% MF 201

SNOTE PLACE NEAR R5901 SNOTE
PLACE NEAR R5903
1 NO_XNET_CONNECTION=TRUE 1
NO_XNET_CONNECTION=TRUE R5914 SIGNAL_MODEL=EMPTY
STUFF FOR STEVENOTE R5915
45.3 45.3
SIGNAL_MODEL=EMPTY 1% SUPPORT ON MLB ONLY 1%
1/20W 1/20W
MF MF
2 201 2 201 FL5750
120-OHM-200MA
29 HOME_L 1 2 HOME_EMI_L 5 37
IN OUT
0201
2
DZ5750 1 C5765 1 C5766

6.8V-100PF 27PF 27PF
0201 5% 5%
B 1
25V
2 NP0-C0G
0201
25V
2 NP0-C0G
0201 B
R5904 R5906
0 0
43 29 VIDEO_PT_DK_CON_Y_PR_R 2 1 VIDEO_PT_DK_CON_Y_PR 27 43 43 29 VIDEO_PT_DK_CON_CVBS_PB_R 2 1 VIDEO_PT_DK_CON_CVBS_PB 27 43
1/20W 5% MF 201 1/20W 5% MF 201

R5905 R5907
2
0 1
DP_PT_DK_CON_TX_P<3>
2
0 1
DP_PT_DK_CON_TX_N<3>
28 43 28 43
1/20W 5% MF 201 1/20W 5% MF 201

SNOTE
PLACE NEAR R5905 SNOTE
PLACE NEAR R5907
1 1
NO_XNET_CONNECTION=TRUE R5916 NO_XNET_CONNECTION=TRUE R5917
45.3 45.3
SIGNAL_MODEL=EMPTY 1% SIGNAL_MODEL=EMPTY 1%
1/20W 1/20W
MF MF
2 201 2 201
R5908
0
43 29 VIDEO_PT_DK_CON_C_Y_R 2 1 VIDEO_PT_DK_CON_C_Y 27 43
1/20W 5% MF 201
A FOR STEVENOTE ON MLB, STUFF ALL OF THE R59091

0
5% SNOTE
SYNC_MASTER=JOE SYNC_DATE=01/19/2011 A
SNOTE BOM OPTIONS. NOSTUFF R5902, R5900,R5908 1/20W PAGE TITLE
R5904, R5906, R5914, R5915, R5916, AND R5917.

MF
201 2 DISPLAY PORT MISC
DRAWING NUMBER SIZE
FOR DEV BOARD, STUFF R5918 AND NOSTUFF R5903. Apple Inc. 051-8773 D
REVISION
R
10.0.0
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8 7 6 5 4 3 2 1
D D
PN 516S0542 (PLUG - MALE)

CRITICAL
J5900
CPB6450-0101F
M-ST-SM
53 51
2 1
4 3 FW_PT_DK_CON_PWR 27 (DP_HPD)
OUT
6 5 ACC_PT_DK_CON_ID 27
OUT
45 27 PPVBUS_USB_PT_DK_CON
8 7
10 9 USB_PT_DK_CON_D_N 27 42
BI
12 11 USB_PT_DK_CON_D_P 27 42
BI
14 13
C 16 15 C
18 17 DP_PT_DK_CON_TX_P<0> 27 43
IN
20 19 DP_PT_DK_CON_TX_N<0> 27 43
IN
22 21
24 23
26 25 DP_PT_DK_CON_TX_P<1> 27 43
IN
(JTAG_TCK_BACKUP) 28 PT_DK_CON_P15_R 28 27 DP_PT_DK_CON_TX_N<1> 27 43
IN IN
(JTAG_TMS_BACKUP) 28 PT_DK_CON_P16_R 30 29
IN
43 28 VIDEO_PT_DK_CON_Y_PR_R 32 31 AV_PT_DK_CON_DIFF_SENSE 27
IN OUT
43 28 VIDEO_PT_DK_CON_C_Y_R 34 33 AUDIO_PT_DK_CON_LO_L 27
IN IN
43 28 VIDEO_PT_DK_CON_CVBS_PB_R 36 35 AUDIO_PT_DK_CON_LO_R 27
IN IN
45 27 ACC_PT_DK_CON_PP3V3 38 37 AV_PT_DK_CON_RET 27
OUT
40 39 ACC_PT_DK_CON_DET_L 27
OUT
(JTAG_TCK) 28 PT_DK_CON_P14_R 42 41 DP_PT_DK_CON_AUX_P 27 43
IN BI
(JTAG_TMS) 28 PT_DK_CON_P17_R 44 43 DP_PT_DK_CON_AUX_N 27 43
IN BI
42 27 ACC_PT_DK_CON_RX 46 45
OUT
42 27 ACC_PT_DK_CON_TX 48 47 HOME_L 28
IN OUT
50 49
54 52
B B
PAGE TITLE
IO FLEX: B2B CONNECTOR

DRAWING NUMBER SIZE

REVISION
R
10.0.0
59 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
X26 CELLULAR/GPS CONNECTOR

OMIT
998-3732
J6000
HOT-BAR-PADS
HB-SM
1
NC
SNSV_BATT_POS_ACF 2
35 =BATT_POS_F_3G 3
4
5
1
R6100 6
255K
C 1%
1/32W
MF
7
8
C
9
2 01005 NC
10
NC
45 37 27 4 OUT RST_AP_L 11
37 OUT ADC_IN7
5 IN PM_RADIO_ON 12
45 37 IN RST_BB_PMU_L 13
NOSTUFF 45 15 5 OUT GSM_TXBURST_IND 14
1
R6101 45 5 RST_BB_L 15
1 C6100 255K
IN
RST_DET_L 16
0.01UF 1%
45 5 OUT
10% 1/32W 17
6.3V
2 X5R MF
01005 2 01005 42 5 IN HSIC_HOST_RDY 18
NOTE FOR SPI2_IPC_SRDY (GPIO12):
42 5 OUT SPI2_IPC_SRDY 19
- BB_DIAGS_READY (RADAR #9179861)
42 5 IN SPI2_IPC_SCLK 20
- BB -> H4G
42 5 IN SPI2_IPC_MOSI 21
42 5 OUT SPI2_IPC_MISO 22
5 OUT BB_EMERGENCY_DWLD 23
37 OUT PM_BB_HOST_WAKE 24
25
37 IN BB_VBUS_DET 26
42 11 BI USB_BB_D_P 27
42 11 BI USB_BB_D_N 28
29
42 5 OUT UART1_BB_RXD 30
42 5 IN UART1_BB_TXD 31
42 5 OUT UART1_BB_CTS_L 32
42 5 UART1_BB_RTS_L 33
B IN
34 NOTE FOR IPC_GPIO_X26 (GPIO24): B
5 BI IPC_GPIO_X26 35 - AP_MODEM_WAKE (RADAR #9179861)
42 5 IN HSIC_BB_RDY 36 - H4G -> BB
37
42 4 BI HSIC0_BB_STB1 38
39
42 4 BI HSIC0_BB_DATA1 40
41
42
NC
PAGE TITLE
CONNECTOR: X26
DRAWING NUMBER SIZE

REVISION
R
10.0.0
60 OF 157
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WWW.AliSaler.Com
8 7 6 5 4 3 2 1
WLAN/BT POWER WLAN/BT BASEBAND

NOSTUFF CRITICAL
XW1
SHORT-0402
SDIO NOT WIRED UP
U4
35 33 BATT_VCC 1 2 33 32 31 BATT_VDD_4330 BCM4330XKUBG
PWR500 1 C1
PWR1000 1
C2 1 C3 USED FOR BOOTSTRAPPING OPTIONS WLBGA
4.7UF 4.7UF 1000PF M6 SYM 3 OF 3 E6
20% 31 SDIO_DATA0_4330 SDIO_DATA_0 BT_UART_RXD BT_UART_RXD IN 15 33
20% 10% SR_VLX
6.3V 6.3V 16V M8 D6
WLAN SDIO
PWR1000 CRITICAL SDIO_DATA1_4330 SDIO_DATA_1 BT_UART_TXD BT_UART_TXD
UART
2 X5R 2 X5R 2 X7R 31 OUT 15 33
603 603 201 U4 31 SDIO_DATA2_4330 M5 SDIO_DATA_2 BT_UART_RTS* F6 BT_UART_RTS_N OUT 15 33
L1 BCM4330XKUBG L8 G6
SDIO_DATA3_4330 BT_UART_CTS_N
D
2.2UH-1.3A-0.1OHM
1 2 VDD_CBUCK_1V5
WLBGA
SYM 1 OF 3
31
31 SDIO_CLK_4330 M7
SDIO_DATA_3
SDIO_CLK
BT_UART_CTS*
BT_TM0 G11
IN 15 33
D
PWR1000 31 SDIO_CMD_4330 L7 SDIO_CMD TEST
L9
(NEAR E1)
CRITICAL 1008 WL_REG_ON WLAN_ENABLE 15 31 33
1 1 K12 IN H7
C58 C82 SR_VDDBAT1_0 K10 M2 BT_I2S_DO NC
FM I2S
BT_REG_ON HSIC_STROBE_4330 HSIC_STROBE
HSIC
4.7UF 0.1UF L12 SR_VDDBAT1_1
33 15 IN
BT_I2S_DI G7
20% 10% BT_RST* G10 BT_RESET_N 15 33
R10 HSIC_DATA_4330 L2 HSIC_DATA NC FM I2S NOT WIRED UP
6.3V 2 2 6.3V K11 SR_VDDBAT2 SR MISC
IN
49.9332 15 BI
BT_I2S_CLK H8
WLAN LOGIC
BT/FM LOGIC
X5R X5R
EXT_PWM_REQ J10 1 HSIC_RREF J1 HSIC_RREF NC
603 201 M12 SR_VLX NC BT_I2S_WS G8
EXT_SMPS_REQ K9 1% NC
31 VDD_LNLDO_1V2 PWR100 NC 1/20W 2G_TSSI E4 WRF_GPIO_OUT
L10 VOUT_LNLDO1 MF
32 IN
BT_PCM_CLK H6 BT_PCM_CLK
1 C48 R16 201 IN 15
M9 H4 J6
PCM
31 VDD_CORE_1V2 PWR100 VOUT_CLDO 10K HOST WAKE WLAN_GPIO0 WL_GPIO_0 BT_PCM_IN BT_PCM_DIN
4.7UF JTAG_SEL F5 1 2
33 15 OUT IN 15
20% 1 M10 JTAG G5 J5
WLAN GPIO
6.3V C49 VIN_LDO JTAG_SEL HSIC HOST RDY / JTAG TMS 33 15 IN WLAN_GPIO1 WL_GPIO_1 BT_PCM_OUT BT_PCM_DOUT OUT 15
2 X5R 5%
4.7UF 31VDD_LDO_2V5 PWR100 J11 VOUT_3P1 LDO 1/20W HSIC DEV RDY / JTAG TCK 33 31 IN WLAN_GPIO2 H5 WL_GPIO_2 BT_PCM_SYNC K6 BT_PCM_SYNC IN 15
603 20% MF
6.3V 1 C50 33 32 31 VDD_LDO_3V3 PWR100 J12 201 WLAN_GPIO3 D5
2 X5R VOUT_3P3 UART RX / JTAG TDI 33 15 IN WL_GPIO_3 F9 BT_WAKE
603 1UF 1 C70 E1 PULL DOWN FOR GPIO WLAN_GPIO4 J8 BT_GPIO_0 IN 15 31 33
10% WRF_VDD_VCOLDO_IN_1P8 UART TX / JTAG TDO 33 15 OUT WL_GPIO_4
BT_GPIO_1 D9 BT_HOST_WAKE
6.3V
2 CERM 4.7UF VDD_VCO_1V2 F2 WRF_VCOLDO_OUT_1P2 WRF_VCO_GND F1
JTAG TRST_N 15 IN WLAN_GPIO5 L6 WL_GPIO_5 H10
OUT 15 33
GPIO
20% BT_GPIO_2
D8 NC
(NEAR M9)
402 2 6.3V WLAN_GPIO6 WL_GPIO_6

1 C86 X5R 1 C52 33 32 31 BATT_VDD_4330 A4 WRF_VDDPA WRF_PA_GND0 B2 (UNUSED) 31 OUT
BT_GPIO_3 H9
603 NC
0.1UF 0.1UF WRF_PA_GND1 B4 BT_GPIO_4 H12
10% 10% NC
6.3V
2 X5R
6.3V
2 X5R WRF_PA_GND2 B6 BT_GPIO_5 J9 BT_GPIO5 15
33 32 31 BATT_VDD_4330 BI
201 201 C3 WRF_PADRV_VDD WRF_PADRV_GND C4
1 C85 1 C29 B7 WRF_VDDLNA_1P2_2G C7 BT_CLK_REQ_IN D7 NC
10PF 0.22UF WRF_GNDLNA_2G
5% 20% H3 WRF_XTAL_VDD1P2 H2 BT_CLK_REQ_MODE E9 NC
31 VDD_XTAL_1V2 WRF_XTAL_GND
1 2 25V
NPO 2 6.3V
X5R 1 D2 WRF_LOGEN_A_VDD1P2 D3
C17 201 0201 C54 WRF_LOGEN_A_GND RF GUYS HATE MULTIPLE GROUND PLANES
1UF 220PF 31 VDD_LNLDO_1V2 G4 WRF_VDDAFE_1P2 WRF_AFE_GND F4
10% 10% WLAN
6.3V
2 CERM
25V
2 X7R-CERM 31 VDD_WRF_1V2 D1 WRF_VDDANA_1P2 WRF_ANA_GND C1 WE HAVE 500MILIAMP BURST RETURN CURRENTS TO BATTERY
402 201 1 1 K1 WL_VDDC0 K2
C56 C79 WL_VSS_0 GET RFDESIGN OK FOR ANY SEPARATION
0.1UF
10%
6.3V
5%
100PF
25V
K7 WL_VDDC1
E7 WL_VDDC2
WL_VSS_1 L5
E5
BOOTSTRAPPING OPTIONS
2 X5R 2 CERM CKPLUS_WAIVE=PWRTERM2GND WL_VSS_2
GPIO6 SDIO_DATA2 SDIO_DATA1 MODE DEF.ARM STATE
C 201 201 F3 WRF_TCXO_VDD
E12
GND
WRF_GND C5
E11
C
FM_RFVDD1P2 FM_RXVSS 0 X X SDIO RESET
31 VDD_CORE_1V2 E10 FM_VDDPLL1P2 FM_PLLVSS F10
F12 FM F11
31 VDD_LDO_2V5 FM_VDD2P5 FM_VSSVCO 1 0 X GSPI RESET
31 VDD_BT_1V2 D10 FM_VDDAUDIO FM_VSSAUDIO C11
B9 BT_RFVDD1P2 BT_RFVSS B10 1 1 0 HSIC RUNNING

B8 BT_IFVDD1P2 BT_IFVSS C8
B11 BT_PLLVDD1P2 BT_PLLVSS C10 1 1 1 BOOTLOADERLESS HSIC RUNNING
K8 BT_VDDC0 BT BT_VSSC F8
31 VDD_BTCORE_1V2 E8 BT_VDDC1
33 32 31 VDD_LDO_3V3 A8 BT_PAVDD3P3 BT_FEVSS A10
31 VDD_BT_1V2 A11 BT_VCOVDD1P2 BT_VSS C9
1 C53
5%
10PF
25V
1 C55
0.1UF
1 C78
10PF
31 VDD_CORE_1V2 L1
L3
HSIC_AVDD12 HSIC_AVSS M1 PULL-UP/DOWN RESISTORS BOOTSTRAP RESISTORS
2 NPO 33 32 31 VDD_LDO_3V3 VDDIO_RF
201
10% 5%
M3 PMU_AVSS L11
2 6.3V
X5R 2 25V
NPO 35 33 31 VDD_IO_1V8 WL_VDDIO MISC
F7 VDD_IO_1V8 VDD_IO_1V8
SR_PVSS M11
201 201 35 33 31 35 33 31 IN
BT_VDDIO
1 C57 1
0.1UF R35 1 1
10% 1 C59 100K R11 R4
6.3V 10K 10K
2 X5R 0.1UF 5%
201 10% 1/20W 5% 5%
6.3V MF 1/20W 1/20W
2 X5R 2 201 MF MF
201 31 SDIO_CMD_4330 NOSTUFF 2 201 2 201
33 31 15 BT_WAKE
31 BI WLAN_GPIO6
1
R31
SDIO_DATA0_4330 100K SDIO_DATA2_4330
B 31
31 SDIO_DATA3_4330
1
R34
5%
1/20W
MF
31
31 SDIO_DATA1_4330
B
100K 2 201
ALTERNATE PARTS AVAILABLE: SUPPLY FILTERING 31 SDIO_CLK_4330 1
R33
100K
5%
1/20W
MF 1
R5
TABLE_ALT_HEAD
5% 2 201 10K
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 1 1/20W 5%
PART NUMBER R32 MF 1/20W
100K 2 201 MF
TABLE_ALT_ITEM
FL2 5% 2 201
311S0548 311S0398 ANDGATE_TI U8 TI 120-OHM-200MA 35 33 31 VDD_IO_1V8 1/20W
MF
2 201
TABLE_ALT_ITEM
155S0657 155S0537 FERRITE_TY FL2,FL4 TAIYO YUDEN 31 VDD_LNLDO_1V2 1 2 VDD_BT_1V2 31

1
TABLE_ALT_ITEM
PWR100 0201 PWR100 R12
155S0337 155S0444 FERRITE_TDK FL6,FL9 TDK 100K
5%
1/20W
120-OHM-200MA
FL4
MF
2 201 HSIC READY KLUDGE
1 2 VDD_WRF_1V2 31 33 31 WLAN_GPIO2
IN VDD_IO_1V8
PWR100 0201 PWR100 35 33 31
1 C80
1
R26 0.1UF
0 10%
6.3V
5%
1/20W
2 X5R U8
MF
201 74AUP1G08GF
6
SOT891
2 201 R28
VCC 0
WLAN_GPIO2_R 2 A Y 4 HSIC_DEVICE_READY_R 1 2 HSIC_DEVICE_READY
R27 OUT 15 31
2.2M 2 1 B
5%
33 31 15 IN WLAN_ENABLE 1 WLAN_ENABLE_RC 1/20W
MF
FL9 5%
5 NC
201
600-OHM-150MA 1/20W
MF NC
201 1 C81 GND
VDD_CORE_1V2 1 2 VDD_BTCORE_1V2
0.1UF
3
31 31
PWR100 PWR100 DEVICE READY DE-ASSERTS WHEN:
A 0201
SET TAU = 200MILISEC
10%
6.3V
2 X5R
201
WLAN RESET FALLS A
SW-DEFINED GPIO2 FALLS PAGE TITLE
600-OHM-150MA
FL6
R76
WLAN BB & POWER
0 DRAWING NUMBER SIZE
VDD_WRF_1V2 1 2 VDD_XTAL_1V2 WLAN_GPIO2 HSIC_DEVICE_READY
31
PWR100 0201 PWR100
31 33 31 1 2 15 31
5%
1/20W REVISION
R
MF
201 10.0.0
NOSTUFF NOTICE OF PROPRIETARY PROPERTY: BRANCH
61 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
RF I/O PLAN
RF_SW_CTRL_0: 2G_CTRL_BT
WLAN TRANSCEIVER
RF_SW_CTRL_1: 2G_CTRL_RX
RF_SW_CTRL_2: 2G_CTRL_TX
CRITICAL
RF_SW_CTRL_3: 2G_CTRL_PA_EN U4
RF_SW_CTRL_4: 5G_CTRL_RX BCM4330XKUBG
RF_SW_CTRL_5: 5G_CTRL_TX WLBGA
RF_SW_CTRL_6: 5G_CTRL_LNA_EN SYM 2 OF 3
RF_SW_CTRL_7: 5G_CTRL_PA_EN RF / CLOCKS R1
15K
D 32
32
OUT 2G_CTRL_BT
2G_CTRL_RX
K5
J2
RF_SW_CTRL_0
RF_SW_CTRL_1
WRF_RES_EXT E3 WLAN_RBIAS_4330 1
1%
2 D
WRF_RFIN_5G B1
OUT 5G_RF_IN_4330 1/20W
50_OHM 50_OHM
WLAN RF
L4 IN 33
32 OUT 2G_CTRL_TX RF_SW_CTRL_2 MF
M4 WRF_RFOUT_5G A2 50_OHM 50_OHM 5G_RF_OUT_4330 33 201
RF
2G_CTRL_PA_EN OUT
32 OUT RF_SW_CTRL_3
33 5G_CTRL_RX K3 RF_SW_CTRL_4 WRF_RFOUT_2G A6 50_OHM 50_OHM 2G_RF_OUT_4330 32
OUT OUT
J4 WRF_RFIN_2G A7
37.4MHZ-18PF-10PPM
33 OUT 5G_CTRL_TX RF_SW_CTRL_5 50_OHM 50_OHM 2G_RF_IN_4330 IN 32
33 5G_CTRL_LNA_EN J3 RF_SW_CTRL_6
OUT
K4 WRF_A_TSSI_IN D4 5G_TSSI IN 33
1
33 OUT 5G_CTRL_PA_EN RF_SW_CTRL_7 C46
A12 WRF_XTAL_OP G1 WLAN_XTAL_P_4330 33PF CRITICAL
FM_AOUT1 5%
NC WRF_XTAL_ON H1 WLAN_XTAL_N_4330 25V
CLOCKS
1
B12 FM_AOUT2 NP0-C0G 2
NC
SM-2
201
FM
Y1
2
C12 WRF_TCXO_IN G3
FM_TX
4
NC
3
D11 LPO J7 CLK32K IN 15 33
1
NC FM_RXP C47
D12 FM_RXN BT_RF A9 50_OHM 50_OHM 2G_RF_BT_4330 33PF
NC 32
R9
BT
OUT 5%
220 25V
2
BT_CLK_REQ_OUT G12 NC 1 2 NP0-C0G
201
1% WLAN_XTAL_N_XTAL
1/20W
MF
201 FORM GROUND ISLAND FOR XTAL CKT BACK TO BUMP H4
C C
2.4GHZ TX 2.4GHZ RX + T/R SWITCH L2

3.3NH+/-0.1NH-0.45A
1 2 VDD_LDO_3V3 31 33
PWR100 PWR100
2G_SP3T_VDD
0201
C65 CRITICAL
8.2PF 1 C89 1 C6
32 IN 2G_RF_BT_4330 1 2 0.1UF 10PF
50_OHM 10% 5%
6.3V 25V
C63 1 50_OHM+/-0.1PF% C67 1 2 X5R 2 NPO
1.8PF 1.8PF
25V
SP3T+LNA 201 201
10
33 31 BATT_VDD_4330 2G_CTRL_PA_EN IN 32
+/-0.1PF CER +/-0.1PF
25V 0201 25V
1 C41 1 C43 C0G 2 C0G 2 0201 2.4GHZ BPF 0201
2
1 201 201 VDD CER CER
1 0.1UF 10PF CRITICAL 25V 25V
1/20W
C38 NOSTUFF NOSTUFF FL1 CRITICAL
47
R2
U3
201
10% 5% +/-0.1PF% +/-0.1PF%
1%
MF
4.7UF 2 6.3V 2 25V SKY65513-11
20% L17 X5R NPO
QFN
C18 2.45GHZ-2.4DB C20
6.3V 201 201
8.2PF 0805 8.2PF
X5R 2 4.3NH-3%-0.35A
1
603 0201 ANT 2 2G_RF_SP3T_ANT 1 2 2G_RF_BPF2_IN1 3 2G_RF_BPF2_OUT
1 2 2G_RF BI 32
CRITICAL 50_OHM 50_OHM 50_OHM 50_OHM
C66 50_OHM 50_OHM 50_OHM 50_OHM 50_OHM
50_OHM
3.3NH+/-0.1NH-0.45A
2
2
2G_TSSI OUT
8.2PF 50_OHM 2G_RF_BT_SP3T12 BT VC1 1 2G_CTRL_BT IN 32
31 50_OHM
2G_PA_VCC2
2G_PA_VCRL
2G_PA_VDET
1 2 2G_RF_RX_SP3T 8 VC2 11
32 OUT 2G_RF_IN_4330 RX 2G_CTRL_RX IN 32
201 2
C42 1
6.8NH-5%-0.3A
2
50_OHM
R14
2.2K
1%
1/20W
MF
33PF C64 1 50_OHM+/-0.1PF% C68 1 2G_RF_TX_SP3T 4 TX VC3 3 2G_CTRL_TX IN 32
2
1
1/20W
10K
R15
C39 1.8PF 1.8PF 50_OHM
201
5% 25V
1%
MF
0.1UF 25V +/-0.1PF CER +/-0.1PF 50_OHM
NP0-C0G 2
NOSTUFF
NOSTUFF
10% 25V 2 0201 25V 2 5 SW_OUT/NC LNA_IN/NC 6 1 C4 1 C5 1 C69
6.3V 201 C0G C0G
VCC1 3
VCC2 2
VCTRL 5
VDET 6
L23
2 X5R
0201
0201
100PF 100PF 100PF
1
201 201
L5
201 5% 5% 5%
B CRITICAL
NOSTUFF NOSTUFF GND 2 25V
CERM
201
2 25V
CERM
201
2 25V
CERM
201
B
9
7
FL8 CRITICAL CRITICAL
L16 L24
1
C37 2450MHZ-3.50DB 1.2NH+/-0.1NH-0.75A U6 1.2NH+/-0.1NH-0.75A
8.2PF LFB182G45CG3C179 LLP
32 IN 2G_RF_OUT_4330 2 1 2G_RF_BPF1_IN 1 3 2G_RF_BPF1_OUT 2 1 2G_RF_PA_IN 4 RFIN RFOUT 1 2G_RF_PA_OUT 1 2
50_OHM 50_OHM 50_OHM 50_OHM 50_OHM 50_OHM 0201 50_OHM 50_OHM 0201
+/-0.1PF% 50_OHM MF2425PL-DL0767 50_OHM 1 1 L43
C44 C45 3.3NH+/-0.1NH-0.45A
2
25V 1 1 CRITICAL 1 THRM_PAD

CER 1.8PF 1.8PF
7
0201 +/-0.1PF +/-0.1PF 1 2

25V 25V
C0G 2 C0G 2 2G_RF_SP3T_LNA1 0201 2G_RF_SP3T_LNA2
L14 L15 L20 201 201
4.7NH-3%-0.35A 1.2NH+/-0.1NH-0.75A 4.7NH-3%-0.35A NOSTUFF
NOSTUFF NOSTUFF
CRITICAL 0201 0201 0201
NOSTUFF CRITICAL VCTL1 VCTL2 VCTL3 MODE
1 0 0 BT TX/RX
2 2 2
0 1 0 WLAN RX
0 0 0 LNA BYPASS
0 0 1 WLAN TX
2.4GHZ/5GHZ DIPLEXER CONDUCTED TEST PORT ANTENNA CONNECTOR

FL10 CRITICAL J1
2.4-5.0GHZ
0805 MM8030-2600RK0
F-ST-SM
LOW(2.4GHZ) 6 2G_RF BI 32 CRITICAL
A HIGH(5.0GHZ) 4 5G_RF BI
C21
33
CRITICAL CRITICAL
R3 MM4829-2702
J2
F-ST-SM
A
4.7PF PAGE TITLE
0.00 2
ANT(COMMON) 2 RF_CAL_MATCH
50_OHM
50_OHM
1 2 RF_CAL 1
50_OHM IN OUT
2 RF_ANT_MATCH1
50_OHM
1
1%
RF_ANT
50_OHM
1
WLAN 2.4GHZ AND ANT
GND 1 +/-0.1PF 1 50_OHM 50_OHM
1/20W 1 50_OHM DRAWING NUMBER SIZE
25V
4
3
2
COG-CERM GND 1 C11
MF
0201
5
3
1
0201
3
4
L6 L7 1.0PF L9 REVISION
+/-0.1PF
5.6NH
0201
5.6NH
0201
25V
2 C0G 5.6NH
0201
R
10.0.0
NOSTUFF NOSTUFF 201 NOSTUFF NOTICE OF PROPRIETARY PROPERTY: BRANCH
NOSTUFF THE INFORMATION CONTAINED HEREIN IS THE
2 2 2 PROPRIETARY PROPERTY OF APPLE INC.
62 OF 157
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5GHZ FRONT-END CONTROL

VCRL1 VCTL2 PA_EN LNA_EN MODE
1 0 0 1 RX SUPERBYPASS MODE -- 26DB GAIN STEP
0 1 0 1 RX
1 0 1 0 TX
D D
5GHZ LNA
1.0NH+/-0.1NH-0.75A
VDD_LDO_3V3 31 32
5GHZ T/R SWITCH
2
1 C7 1 C87
0.01UF 4.7PF CRITICAL
10% +/-0.1PF
L46
0201
10V 25V
2 X5R 2 COG-CERM
201 0201
5G_CTRL_RX IN 32
5G_CTRL_TX IN
1
32
5G_LNA_CHOKE 1 1
C76 C75
100PF 100PF
6
5% 5%
25V 25V
VCC CERM 2 2 CERM
U1
CRITICAL 5GHZ BPF 201 201
SKY65404-31
CRITICAL
QFN
CRITICAL FL7 CRITICAL CRITICAL CRITICAL CRITICAL
C61 50_OHM V_ENABLE 1 5G_CTRL_LNA_EN IN C77 5.0GHZ-1.7DB C72 U9 C84
2.0PF 50_OHM
32
2.0PF5G_RF_RX_BPF_OUT DEA165375BT 2.0PF UPG2185T6R 2.0PF
TSSON
32 5G_RF_IN_4330 1 2 5G_RF_LNA_OUT 4 RF_OUT RF_IN 3 5G_RF_LNA_IN 1 2 1 3 5G_RF_RX_BPF_IN 1 2 5G_RF_RX 1 OUTPUT1 INPUT 5 5G_RF_TRSW 1 2 5G_RF 32
OUT BI
50_OHM 1 1 C62 50_OHM 50_OHM 50_OHM 50_OHM 50_OHM 50_OHM
50_OHM C60 50_OHM 50_OHM 50_OHM C71 1 1 C73 50_OHM 3 OUTPUT2 50_OHM 50_OHM
1.0NH+/-0.1NH-0.75A
+/-0.1PF +/-0.1PF +/-0.1PF +/-0.1PF
0.6PF 0.6PF 0.6PF 0.6PF
2
4
25V 1 C8 25V 1 C10 25V 25V
+/-0.10PF C0G-CERM +/-0.10PF C0G-CERM +/-0.05PF C0G-CERM +/-0.05PF C0G-CERM
25V 0201 2 25V THRM 100PF 0201 0.6PF 25V 0201 2 25V 0201
C CERM 2
201
CERM
201
PAD
GND
5%
25V
+/-0.10PF
25V
CERM 2
0201
CERM
0201
6 VCONT1
C
2
7 2 CERM 2 CERM 4 VCONT2
5
2
NOSTUFF NOSTUFF 201 201 NOSTUFF
NOSTUFF
NOSTUFF GND
L22
0201
2
NEED DC BLOCKING ON ALL PORTS
1
5GHZ PA
33 32 31 BATT_VDD_4330
1 C32 1 C34
B 20%
4.7UF
2 6.3V
X5R
603
5%
25V
2 NPO
201
10PF
TEST POINTS B
TEST AND PROBE POINTS
R29 R13
62 2.2K 2 TP11 WLAN_ENABLE TP21 BT_RESET_N TP15
1 BATT_VCC
IN 5G_CTRL_PA_EN 5G_PA_VCTL 5G_PA_VDET 5G_TSSI
1 2 1
32 OUT 32
A 15 31
A 15 31
A 31 35
5% 1 C36 1% 1 TP-P6 TP-P6 TP-1P0-TOP

1/20W 1 C74 1/20W R7 NOSTUFF NOSTUFF NOSTUFF
MF 27PF MF 10K TP16
201 100PF 5% 201 1% TP26 1 BATT_VDD_4330
5% 2 25V 1/20W TP71 WLAN_GPIO0 1 BT_UART_TXD A 31 32 33
2 25V NP0-C0G MF A 15 31
TP-1P0-TOP
CERM 0201 A 15 31
TP-P6 NOSTUFF
201 2 201 TP-P6
NOSTUFF
NOSTUFF TP17
1 VDD_IO_1V8
TP27 A 31 35
1 BT_UART_RXD TP-1P0-TOP
TP31 WLAN_GPIO1 A 15 31
NOSTUFF
TP-P6 TP18
A 15 31
NOSTUFF 1
TP-P6 A
VCC12 6
VCC3 7
NOSTUFF TP28 TP-1P0-TOP

1 BT_UART_RTS_N NOSTUFF
A 15 31
TP19
CRITICAL TP41 WLAN_GPIO2 TP-P6 1
NOSTUFF A
A 31
TP-1P0-TOP
CRITICAL CRITICAL CRITICAL TP-P6 TP29 NOSTUFF
U10 NOSTUFF 1 BT_UART_CTS_N
C33 C35 C83 A 15 31
2.0PF MF5060PK-DL0967 2.0PF 2.0PF TP-P6

1 2 5 LGA 1 1 2 5G_RF_TX_MATCH 1 2 TP51 WLAN_GPIO3 NOSTUFF
32 IN 5G_RF_OUT_4330 5G_RF_PA_IN RFIN RFOUT 5G_RF_PA_OUT 5G_RF_TX A 15 31
50_OHM 50_OHM 50_OHM 50_OHM 50_OHM TP-P6 TP81 BT_HOST_WAKE
50_OHM 50_OHM 4 50_OHM 50_OHM 50_OHM A
VDET 8
15 31
+/-0.1PF VCTL +/-0.1PF +/-0.1PF NOSTUFF
1.0NH+/-0.1NH-0.75A
1.0NH+/-0.1NH-0.75A
1.0NH+/-0.1NH-0.75A
25V 25V 25V TP-P6

1.0NH+/-0.1NH-0.75A
C0G-CERM C0G-CERM C0G-CERM NOSTUFF

0201 0201 0201
NC/GND
NC/GND
TP10
1 WLAN_GPIO4
A 15 31 TP91 BT_WAKE
THRM
PAD
A 15 31
2
TP-P6
2
TP-P6
A NOSTUFF
NOSTUFF
A
NOSTUFF
NOSTUFF
NOSTUFF
NOSTUFF
2
3
TP61 CLK32K
L10
L11
L21
0201
0201
0201
PAGE TITLE
L12
0201
A 15 32
TP-P6
NOSTUFF
WLAN 5GHZ AND TEST POINTS
DRAWING NUMBER SIZE
051-8773 D
1
PP29 Apple Inc.

1
P4MM REVISION
SM R
PP
1 HSIC_DATA_4330 15 31 10.0.0
PP30
P4MM
SM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
1 HSIC_STROBE_4330
PP 15 31
63 OF 157
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D D
C C
CRITICAL
35 =BATT_POS_CONN
J7500
TP7500 BATT-J2
1 F-RT-SMTH
A
B FL7500
TP-P55
NOSTUFF
7
6
B
240-OHM-0.2A-0.8-OHM
37 5 BI BATTERY_SWI 1 2 BATT_SWI_CONN 1 HDQ
0201 BATT_NTC_CONN 2 THERM
NET_SPACING_TYPE=ANLG
3 PACK_NEG
R7541 4 PACK_POS
0 1 1 1 1 5
37 BI BATTERY_NTC 1 2 C7522 C7523 C7524 C7525 SENSE
5% MF 33PF 33PF 1000PF 82PF
1/20W 201 5% 5% 10% 5%
25V 25V 16V 25V 8
NOTE: GET RID OF THE NP0-C0G 2 NP0-C0G 2 X7R 2 CERM 2
201 201 201 0201
RES AFTER BRINGUP
MIN_NECK_MIDTH SHOULD BE 0.2MM

36 BATT_SNS
MIN_LINE_WIDT=0.25MM
APN:516S0926
MIN_NECK_WIDT=0.15MM
TP7501
1
A
TP-P55
NOSTUFF
TP7502
1
A
A TP-P55
NOSTUFF SYNC_MASTER=MADHAVI SYNC_DATE=01/13/2011 A
PAGE TITLE
TP7503
1 POWER: BATTERY CONNECTOR
A
TP-P55 DRAWING NUMBER SIZE
NOSTUFF
REVISION
R
10.0.0
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POWER CONN / ALIAS

D LDO RAILS D
PROGRAMMABLE ON/OFF BUCK RAILS CHARGER MAIN
LDO1 45 36 PP3V0_GRAPE
MAKE_BASE=TRUE
=PP3V0_GRAPE 17 18
BUCK0 45 36 PP1V25_CPU =PPVDD_CPU_H4 9 45 37 36 PPVCC_MAIN
VOLTAGE=3.0V =PP3V0_GRAPE_MARIO1 17 MAKE_BASE=TRUE MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM VOLTAGE=1.25V VOLTAGE=4.7V =PPVCC_MAIN_LED 37
MIN_NECK_WIDTH=0.2MM =PP3V0_GRAPE_Z1 18 MIN_LINE_WIDTH=0.6 MM MIN_LINE_WIDTH=0.6MM
NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.1MM =PPVCC_MAIN_AUDIO 19 20 22
MAX_NECK_LENGTH=3 MM =PP3V0_GRAPE_Z2 18 NET_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR
MAX_NECK_LENGTH=3 MM MAX_NECK_LENGTH=3 MM =PPVCC_MAIN_DOCK 27
LDO2 45 40 36 PP1V7_VA_VCP
MAKE_BASE=TRUE
=PP1V7_VA_VCP 19
BUCK2 45 36 PP1V2_SOC =PPVDD_SOC_H4 9
VOLTAGE=1.7V MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6MM VOLTAGE=1.2V
MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6 MM
NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.25 MM
LDO3 45 36 PP3V0_VIDEO
MAKE_BASE=TRUE
=PP3V0_VIDEO_H4 7
VOLTAGE=3.0V
BUCK3 45 36 PP1V8_S2R
MAKE_BASE=TRUE
=PP1V8_S2R_MISC 5 27 39
VOLTAGE=1.8V VDD_IO_1V8 31 33
LDO4 45 36 PP3V0_OPTICAL
MAKE_BASE=TRUE
=PP3V0_OPTICAL 26 MIN_NECK_WIDTH=0.15 MM
=PP1V8_S2R_DDR 13 14 BATTERY
VOLTAGE=3.0V MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2 mm 45 39 36 PPBATT_VCC =BATT_POS_F_3G 30
NET_SPACING_TYPE=PWR MAKE_BASE=TRUE
MAX_NECK_LENGTH=3 MM VOLTAGE=4.2V =BATT_POS_CONN 34
MIN_NECK_WIDTH=0.20 MM BATT_VCC 31 USED BY WIFI_BT
NET_SPACING_TYPE=PWR 33
LDO5 45 36 PP3V2_LDO5
MAKE_BASE=TRUE
=PP3V2_LDO5
CPU1V8_SW 36 PP1V8 =PP1V8_CAM 25
C VOLTAGE=3.2V
(BUCK3)
45 MAKE_BASE=TRUE
VOLTAGE=1.1V
=PP1V8_SENSOR
=PP1V8_DP_H4
26
7
C
MAX_NECK_LENGTH=3 MM =PP1V8_AUDIO 19
=PP1V8_H4 4 7 10
LDO6 45 36 PP3V3_ACC
MAKE_BASE=TRUE
=PP3V3_PORT_ACC 27 =PP1V8_NAND_H4 9
VOLTAGE=3.3V =PP1V8_MIPI_H4 7
MIN_NECK_WIDTH=0.2MM =PP1V8_NAND 12
MAX_NECK_LENGTH=3 MM =PP1V8_VDDIO18_H4 9
=PP1V8_EDP_H4 7
=PP1V8_VDDIOD_H4 5 9
LDO7 45 36 PP3V0_VIDEO_BUF
MAKE_BASE=TRUE
=PP3V0_VIDEO_BUF 11 =PP1V8_VDDA18_TS 5 USB POWER INPUT
VOLTAGE=3.0V
MAX_NECK_LENGTH=3 MM WDIG_SW 45 36 PP1V8_GRAPE
MAKE_BASE=TRUE
=PP1V8_GRAPE
(BUCK3) VOLTAGE=1.8V
27 PPVBUS_USB_EMI PPVBUS_USB_DCIN
MAKE_BASE=TRUE
36 45
LDO8 45 36 PP3V2_S2R_USBMUX
MAKE_BASE=TRUE
=PP3V2_S2R_USBMUX 11 NET_SPACING_TYPE=PWR
VOLTAGE=3.2V
LDO9 45 36 PP3V0_IO
MAKE_BASE=TRUE
=PP3V0_IO_MISC 6 28
VOLTAGE=3.0V
=PP3V0_IO_H4 7 9 BUCK4 45 36 PP1V2_S2R
MAKE_BASE=TRUE
=PP1V2_S2R_H4 8
=PP3V0_VDDIOD_H4 9 VOLTAGE=1.2V
=PP1V2_S2R_DDR 13 14 LCM_BOOST
MAX_NECK_LENGTH=3 MM MIN_NECK_WIDTH=0.25 MM
B 45 37 PP5V25_VLCM2
MAKE_BASE=TRUE
VOLTAGE=5.25V
=PP5V25_GRAPE_VDDH
B
LDO10 45 36 PP3V0_S2R_HALL
MAKE_BASE=TRUE
=PP3V0_S2R_HALL 26
BUCK4_SW 45 36 PP1V2 =PP1V2_VDDIOD_H4 8 9
VOLTAGE=3.0V =PP3V0_S2R_HALL_CHSW 22 MAKE_BASE=TRUE NET_SPACING_TYPE=PWR
MIN_LINE_WIDTH=0.6MM VOLTAGE=1.2V =PP1V2_HSIC_H4 4 MAX_NECK_LENGTH=3 MM
MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6 MM
NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.2 mm =PP1V2_VDDQ_DDR 13 14
LDO11 45 36 PP2V85_CAM
MAKE_BASE=TRUE
=PP2V85_CAM 26
VOLTAGE=2.85V
LDO12 45 36 PP1V1 =PP1V1_PLL_H4 4

BUCK5 45 36 PP3V3_OUT
MAKE_BASE=TRUE
=PP3V3_NAND 12
MAKE_BASE=TRUE VOLTAGE=3.3V =PP3V3_USB_H4 4

VOLTAGE=1.1V =PP1V1_MIPI_H4 7 MIN_LINE_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.1MM =PP3V3_NAND_H4 9
MIN_NECK_WIDTH=0.2 MM =PP1V1_DP_PAD_DVDD_H4 7 NET_SPACING_TYPE=PWR
NET_SPACING_TYPE=PWR MAX_NECK_LENGTH=3MM =PP3V3_LCD 16
MAX_NECK_LENGTH=3 MM =PP1V1_USB_H4 4 GND
MAKE_BASE=TRUE
=PP1V1_HSIC_H4 4 VOLTAGE=0V
=PP1V1_MIPI_PLL_H4 4 MIN_NECK_WIDTH=0.15MM
NET_SPACING_TYPE=GND
=PP1V1_EDP_PAD_DVDD_H4 7 MAX_NECK_LENGTH=5 MM
VOUT_LED_A 45 37 PPLED_OUT_A
MAKE_BASE=TRUE
=PPLED_REG_A 16
VOLTAGE=20.4V
MIN_LINE_WIDTH=0.6 MM NET_SPACING_TYPE=PWR
MIN_NECK_WIDTH=0.2 MM MAX_NECK_LENGTH=3 MM
VOUT_LED_B 45 37 PPLED_OUT_B
MAKE_BASE=TRUE
=PPLED_REG_B 16
45 36 PP1V8_ALWAYS =PP1V8_ALWAYS 5 VOLTAGE=20.4V

A MAKE_BASE=TRUE
VOLTAGE=1.8V
SYNC_MASTER=MADHAVI SYNC_DATE=01/13/2011 A
NET_SPACING_TYPE=PWR PAGE TITLE
POWER ALIASES
DRAWING NUMBER SIZE

REVISION
R
10.0.0
80 OF 157
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8 7 6 5 4 3 2 1
CRITICAL
L8100
2.2UH-20%-1.85A-80MOHM
45 BUCK0_LXL 1 2 PP1V25_CPU 35 45
MIN_NECK_WIDTH=0.25 MM PST25201B-SM
NET_SPACING_TYPE=PWR CRITICAL CRITICAL CRITICAL ADDITIONAL DISTRIBUTED
TABLE_ALT_HEAD
DIDT=TRUE
L8101 1 C8102 1 C8103
25UF (N0 DE-RATING)
PART NUMBER ALTERNATE FOR
PART NUMBER
BOM OPTION REF DES COMMENTS: 2.2UH-20%-1.85A-80MOHM 22UF 22UF
20% 20%
TABLE_ALT_ITEM
45 BUCK0_LXM 1 2 2 6.3V 6.3V

X5R-CERM-1 2 X5R-CERM-1
197S0392 197S0299 ? Y8138 RADAR:8788152 ALTERNATE FOUNDRY MIN_LINE_WIDTH=0.6 MM
PST25201B-SM 603 603
TABLE_ALT_ITEM
152S1452 152S1292 ? L8128 RADAR:8376462 DIDT=TRUE XW8103
45 BUCK0_FB 1 2
SM
D MIN_NECK_WIDTH=0.20 MM
NOSTUFF
CRITICAL D
L8105
2.2UH-20%-1.85A-80MOHM
45 BUCK2_LXL 1 2 PP1V2_SOC 35 45
MIN_NECK_WIDTH=0.25 MM PST25201B-SM
NET_SPACING_TYPE=PWR CRITICAL CRITICAL CRITICAL ADDITIONAL DISTRIBUTED
CRITICAL
DIDT=TRUE
L8107 1 C8107 1 C8108 30UF (N0 DE-RATING)
2.2UH-20%-1.85A-80MOHM 22UF 22UF
L8112 BUCK2_LXM 1 2
20%
2 6.3V
20%
6.3V
2.2UH-20%-4A-32MOHM 45
X5R-CERM-1 2 X5R-CERM-1
PST25201B-SM 603 603
45 37 36 35 PPVCC_MAIN 1 2 SW_CHGA U8100 OMIT
NET_SPACING_TYPE=PWR CRITICAL
MIN_LINE_WIDTH=0.6 MM DIDT=TRUE
L8110
RDSON=0.0136@VGS=-2.5V
PIME101E-SM
DCR=32MOHM MAX
2 MIN_NECK_WIDTH=0.25 MM D1974AB
NET_SPACING_TYPE=SWITCHNODE
TFBGA 2.2UH-20%-1.85A-80MOHM
D8100 DIDT=TRUE
SYM 2 OF 4 CRITICAL
1 2 3 SOD-123W F30 BUCK0_LXL A11 45 BUCK2_LXR 1 2
S PMEG4030ER
CRITICAL1 G30 BUCK0_LXM A9
PST25201B-SM
L8115
CRITICAL CHG_LX MIN_NECK_WIDTH=0.25 MM 2.2UH-20%-1.85A-80MOHM
4 G H30 BUCK0_FB D7
ADDITIONAL DISTRIBUTED
Q8104 DIDT=TRUE XW8113 1 2 PP1V8_S2R
FDMC6683
R8172 45 BUCK2_FB 1 2
35 36 45
0 K10 VBAT NET_SPACING_TYPE=PWR PST25201B-SM 14UF (N0 DE-RATING)

MLP3.3X3.3 34 BATT_SNS 1 2 BATT_SNS_R BUCK2_LXL A7 MIN_LINE_WIDTH=0.25 MM
SM
NOSTUFF CRITICAL CRITICAL
ID=12.0A
5% NOSTUFF A27 IBAT_SENSE
BUCK3_LXL
1 C8117 1 C8118
NOSTUFF 1/20W 45 CRITICAL 22UF 22UF
C8172
R8173
D A22 BUCK2_LXM A6
1
MF 1
1
R8116 201
L8116 20% 20%
1/20W
0.022UF MIN_NECK_WIDTH=0.25 MM
499
5 A23 IBAT 6.3V 6.3V
BUCK2_LXR A4
201
NET_SPACING_TYPE=PWR 2.2UH-20%-1.85A-80MOHM 2 X5R-CERM-1 2 X5R-CERM-1
1%
MF
MOSFET FDMC6676BZ 470K LAYOUT NOTE - 10% DIDT=TRUE
1% R8172- PLACE NEAR BMU 2 25V
X7R BUCK2_FB D5 1 2
603 603
1/20W C8172- PLACE NEAR PMU 0402 45 BUCK3_LXM
CHANNEL P-TYPE
2
MF R8173- PLACE NEAR PMU MIN_LINE_WIDTH=0.6 MM
PST25201B-SM
2 201 ACT_DIO B25 ACT_DIO BUCK3_LXL A18
BUCK
RDS(ON) 27 MOHM @-4.5V
USB/BAT
MIN_LINE_WIDTH=0.2 MM DIDT=TRUE
45 39 36 35 PPBATT_VCC MIN_NECK_WIDTH=0.1 MM BUCK3_LXM A16 XW8117
IMAX 6.9 A E30 BUCK3_FB D16 45 BUCK3_FB 1 2
45 PPVBUS_PROT J30 VCENTER MIN_LINE_WIDTH=0.25 MM
SM
VGS MAX +/- 25V MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.20 MM CRITICAL NOSTUFF
BUCK4_LXL A14
C MIN_NECK_WIDTH=0.25MM
BUCK4_LXM A12
L8119
2.2UH-20%-1.85A-80MOHM
C
2
MAX_NECK_LENGTH=3 MM DIDT=TRUE
DZ8120 XW8114
3
2
1
VOLTAGE=6.0V
CRITICAL DIDT=TRUE SHORT-0201 46NC_VBUS_A_OV_L A30 VBUS_OV_N BUCK4_FB D13
BZT52C10LP 45 BUCK4_LXL 1 2 PP1V2_S2R 35 36 45
Q8123 S LLP CRITICAL 45 4 PPVBUS_USB 2 1 PMU_VCENTER MIN_LINE_WIDTH=0.6 MM
PST25201B-SM
FDMC6676BZ CRITICAL C8124 1 NOSTUFF
MIN_NECK_WIDTH=0.25MM E29 E1 MIN_NECK_WIDTH=0.25 MM
NET_SPACING_TYPE=PWR CRITICAL CRITICAL ADDITIONAL
CRITICAL DISTRIBUTED
1
2.2UF NET_SPACING_TYPE=PWR
MLP3.3X3.3 G 4 NOTE: 10V ZENER 10% MAX_NECK_LENGTH=3 MM F29 BUCK5_LX E2 DIDT=TRUE
L8121 1 C8121 1 C8122 20UF (N0 DE-RATING)
25V
LAYOUT NOTE: PLACE VOLTAGE=6V
G29 VBUS H1 2.2UH-20%-1.85A-80MOHM 22UF 22UF
X5R-CERM 2 1 C8125 20% 20%
805 VBUCK5_BYP 6.3V 6.3V
RIGHT AT THE PIN 10UF
H29 H2 (BYPASS RON=0.14 OHM MAX) 45 BUCK4_LXM
1 2 2 X5R-CERM-1 2 X5R-CERM-1
D 10% J29 MIN_NECK_WIDTH=0.25 MM PST25201B-SM 603 603
25V
2 X5R NET_SPACING_TYPE=PWR
5
805 BUCK5_FB G3 DIDT=TRUE

XW8126
VBUS_PROT_G
45 35 PPVBUS_USB_DCIN MIN_LINE_WIDTH=0.20MM CRITICAL 45 BUCK4_FB 1 2
NET_SPACING_TYPE=PWR MIN_NECK_WIDTH=0.1MM
N8 (150MA; 2.5-3.55V) NET_SPACING_TYPE=PWR
SM
MAX_NECK_LENGTH=3 MM 1 NET_SPACING_TYPE=ANLG LAYOUT NOTE: PLACE VLDO1 PP3V0_GRAPE 35 36 45 MIN_LINE_WIDTH=0.25 MM
VOLTAGE=6.0V R8130 RIGHT AT THE PIN K1 (100MA; 1.65-1.805V; BUCK3) PP1V7_VA_VCP MIN_NECK_WIDTH=0.20 MM NOSTUFF
VLDO2 35 36 40 45
220K REVIEW THESE N10 (50MA; 2.5-3.3V) CRITICAL
1% VLDO3 PP3V0_VIDEO 35 36 45
1/20W A10 N4 (100MA; 1.8-3.3V) PP3V0_OPTICAL
L8128
MF VLDO4 35 36 45 2.2UH-20%-3.3A-0.064OHM
201 2 B10 VDD_BUCK0 N11 (300MA; 2.5-3.6V)
VLDO5 PP3V2_LDO5 35 36 45
45 BUCK5_LX 1 2 PP3V3_OUT
LDO
35 45
A5 VLDO6 N9 (150MA; 2.5-3.6V) PP3V3_ACC 35 36 45 MIN_LINE_WIDTH=0.6 MM
PIME051E-SM
B5 VDD_BUCK2 VLDO7 N5 (50MA; 1.5-3.3V) PP3V0_VIDEO_BUF 35 36 45
NET_SPACING_TYPE=PWR DCR=64MOHM MAX CRITICAL ADDITIONAL
CRITICAL DISTRIBUTED
DIDT=TRUE
VLDO8 M10 (10MA; 2.0-3.55V) PP3V2_S2R_USBMUX 1 C8119 1 C8120 47UF (N0 DE-RATING)
USB REVERSE VOLTAGE PROTECTION VLDO9 N12 (300MA; 1.2-3.0V) PP3V0_IO
35 36 45
22UF 22UF
35 36 45
XW8132 20% 20%
VCC-MAIN
A17 VDD_BUCK3 N7 (200MA; 2.5-3.55V) PP3V0_S2R_HALL BUCK5_FB 1 2 6.3V 6.3V
VLDO10 35 36 45 45 2 X5R-CERM-1 2 X5R-CERM-1
A13 VLDO11 N3 (200MA; 1.7-3.0V) PP2V85_CAM 35 36 45 MIN_LINE_WIDTH=0.25 MM
SM 603 603
B13 VDD_BUCK4 N6 (150MA; 0.6-1.3V) PP1V1
MIN_NECK_WIDTH=0.20 MM NOSTUFF
VLDO12 35 36 45
F1 ON_BUF L2 PP1V8_ALWAYS 35 36 45
F2 VDD_BUCK5
G1 VBUCK4 A21 PP1V2_S2R 35 36 45
G2 VDD_BUCK5_BYP CPU1V2_SW A20 (RON=0.1 OHM MAX) PP1V2 35 45
B NOTE: FOR NO BATTERY SITUATION DSP_SW B21 (RON=1 OHM MAX)

DSP_SW
TP8133
1 TP-P55
TP
B
NOSTUFF
PPBATT_VCC A26 VCC_MAIN_SENSE VBUCK3 B18 PP1V8_S2R
SWITCH POWER
45 39 36 35 NOSTUFF 35 36 45
NOSTUFF CRITICAL CRITICAL CRITICAL
CRITICAL A24 CPU1V8_SW A19 (RON=0.2 OHM MAX) PP1V8 35 45
1 C8100
1 C8101 1 C8170 1 C8171 A25 VCC_MAIN WDIG_SW B19 (RON=0.5 OHM MAX) TP8101
10UF 10UF 10UF 45 35 PP1V8_GRAPE 1
10UF 20% 20% 20% TP
20% 6.3V 6.3V 6.3V TP-P55
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R
2 6.3V
CERM-X5R 0402-1 0402-1 0402-1 VBUCK0_SW0_G B16 NC_PMU_VBUCK0_SW0_G 46
1 C8138 1 C8140 1 C8139 1 C8141 NOSTUFF
0402-1 45 BATT_POS_RC M8 VDD_LDO1_6 VBUCK0_SW0_S B14 NC_PMU_VBUCK0_SW0_S 46
1UF 1UF 1UF 1UF
MIN_LINE_WIDTH=0.30MM 20% 10% 10% 10%
MIN_NECK_WIDTH=0.20MM 45 36 35 PP1V8_S2R K2 VDD_LDO2 2 6.3V
X5R 2 6.3V
CERM 2 6.3V
CERM 2 6.3V
CERM
1
R8100 NET_SPACING_TYPE=PWR
M11 VPUMP B20 PMU_VPUMP 0201 402 402 402
LDO INPUT
MAX_NECK_LENGTH=3 MM VDD_LDO3_5_8 36
0.5 VOLTAGE=4.6V 1 C8135 M5
1% 1UF VDD_LDO4_7
1/16W 10% M12 VDD_LDO9
MF 6.3V
LDO BYPASS
2
402 2 CERM M7
402 VDD_LDO10
DIDT=TRUE 36 PMU_VPUMP
45 37 36 35 PPVCC_MAIN M4 VDD_LDO11 45 36 35 PP3V0_GRAPE MIN_LINE_WIDTH=0.30MM
45 36 35 PP1V8_S2R M6 VDD_LDO12 45 40 36 35 PP1V7_VA_VCP NET_SPACING_TYPE=PWR
1 MAX_NECK_LENGTH=3 MM
1 C8136 45 36 35 PP3V0_VIDEO C8137 VOLTAGE=4.6V
N1 XTAL1 PP3V0_OPTICAL 0.01UF
XTAL
1UF NET_SPACING_TYPE=CRYSTAL
45 36 35
10%
10% N2 XTAL2 45 36 35 PP3V2_LDO5 6.3V 2
6.3V X5R
2 CERM 01005
402 CRITICAL 45 36 35 PP3V3_ACC
Y8138 45 36 35 PP3V0_VIDEO_BUF
32.768K-20PPM-12.5PF CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 2 42 PMU_EXTAL NET_SPACING_TYPE=CRYSTAL CRITICAL 1 1 1 1 1 1 1
42 PMU_XTAL C8150 C8149 C8148 C8146 C8145 C8144 C8147
2.2UF 2.2UF 4.7UF 2.2UF 2.2UF 10UF 2.2UF
VCC_MAIN BYPASS C8142
18PF
1 2012 1 C8143
18PF
10%
6.3V
X5R 2
10%
6.3V
X5R 2
20%
6.3V
X5R-CERM1 2
10%
6.3V
X5R 2
10%
6.3V
X5R 2
20%
6.3V
CERM-X5R 2
10%
6.3V
X5R 2
5% 5% 402 402 402 402 402 0402 402
TOTAL CAPS = ~400UF 25V
NP0-C0G 2
25V
2 NP0-C0G
(DISTRIBUTED AND NO DE-RATING) 201 201
A PLACEMENT_NOTE=PLACE NEAR L8225.1
(PLACE ONE 10UF CAP AT EACH VDD INPUT) 45 36 35
45 36 35
PP3V2_S2R_USBMUX
PP3V0_IO
SYNC_MASTER=MADHAVI SYNC_DATE=01/13/2011 A
PPVCC_MAIN 35 36 37 45
PAGE TITLE
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
45 36 35 PP3V0_S2R_HALL
PP2V85_CAM
POWER: AMELIA PMU
C8166 1 C8165 1 1 C8154 1 C8155 1 C8156 1 C8157 1 C8158 1 C8159 1 C8160 1 C8161 1 C8162 1 C8130 1 C8131 1 C8163 1 C8164 45 36 35
PP1V1
DRAWING NUMBER SIZE
150UF 150UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 1UF 82PF 18PF 45 36 35
051-8773 D
20%
6.3V 2
20%
6.3V 2
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
5%
2 25V
5%
2 25V
45 36 35 PP1V8_ALWAYS
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
Apple Inc. REVISION
TANT-1 TANT-1 X5R X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R X5R CERM NP0-C0G R
B15G
ESR MAX=70MOHM ESR MAX=70MOHM
B15G 603 603 0402 0402 0402 0402 0402 0402 0402 0402 0201 0201 201
C8169 1 C8168 1 C8167 1 C8153 1 C8152 1 C8151 1 10.0.0
0.22UF 2.2UF 2.2UF 2.2UF 4.7UF 1UF NOTICE OF PROPRIETARY PROPERTY: BRANCH
NOTE: CONCERNED ABOUT ESR > 20MOHM 20%
6.3V
10%
6.3V
10%
6.3V
10%
6.3V
20%
6.3V
10%
6.3V
NOTE: CHANGE SOME 1UF TO 4.7UF X5R 2 X5R 2 X5R 2 X5R 2 X5R-CERM1 2 CERM 2 THE INFORMATION CONTAINED HEREIN IS THE
0201 402 402 402 402 402
81 OF 157
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
(TEMP5 - TOP SIDE NEAR NAND) NET_SPACING_TYPE=ANLG BOARD_TEMP5_P 37
(TEMP6 BOTTOM SIDE NEAR BRIDGE FLEX) NET_SPACING_TYPE=ANLG BOARD_TEMP6_P 37
1
1
R8281
10KOHM-1% R8282
0201 10KOHM-1%
C8281 1
2 0201
100PF C8282 1
5% 2
6.3V
CERM 2
100PF
5% NOSTUFF
01005 6.3V 1
CERM 2 1 R8203
R8260
D
01005
5%
220K
1 C8204
0.1UF
10%
1%
200K
1/20W
D
1/32W 6.3V MF
MF 2 X5R 2 201
1 C8206 1
C8207 2 01005 201
0.01UF 0.01UF
XW8282 10%
2 6.3V 2 10% U8100 OMIT
X5R 6.3V
BOARD_TEMP6_N 1 2
01005 X5R D1974AB PLACEMENT NOTE: PLACE NEAR PIN K4
XW8281 SM 01005 TFBGA
BOARD_TEMP5_N 1 2 NOSTUFF
SYM 1 OF 4
NOSTUFF
SM
(INTERNAL PULL-DOWN) L29 M1
1 C8212 1 C8209 1 C8210
DIGITAL INPUT
PLACE XW AND CAP 27 IN FW_ZENER_PWR FW_DPHP_DET IREF PMU_IREF
NET_SPACING_TYPE=ANLG 0.1UF 1UF 0.22UF
REFERENCES
PLACE XW AND CAP CLOSE TO PMU 43 7 OUT DP_AP_HPD K18 DPHP VREF L1 PMU_VREF 10% 10% 20% PLACEMENT NOTE: PLACE NEAR PIN K24
2 6.3V
X5R 2 6.3V
CERM
6.3V
2 X5R
CLOSE TO PMU 28 5 IN HOME_EMI_L K16 BUTTON1 VDD_REF K24 PMU_VDD_REF
NET_SPACING_TYPE=ANLG 201 402 0201
24 5 IN ONOFF_L K17 BUTTON2 VDD_REF_A K4
24 5 IN SRL_L J17 BUTTON3 VDD_RTC M9 PMU_VDD_RTC
27 IN PORT_DOCK_ACC_DET_L A1 ACC_DET ADC_REF K9 27 PMU_ADC_REF
PORT_DOCK_ACCID M2 ACC_ID
27 IN
GPIO1 B22 CLK_32K_PMU (CPU1V8; PUSH-PULL) USED BY ZEPHYR2. WHICH IS NOW POR C8214 1
ANALOG
OUT 18 42
INPUT
4 USB_BRICKID N28 BRICK_ID 1000PF
IN B23 CLK_32K_WLAN
N27 GPIO2 OUT 15 42 (1.8_S2R; PUSH-PULL) 10%
30 ADC_IN7 ADC_IN7 6.3V
GPIO3 B24 RST_BT_L OUT 15 45 (1.8_S2R; PUSH-PULL; NO PD REQ’D PER BB TEAM) 2 X5R-CERM
M26 ADC_IN31 01005
GPIO4 D21 RST_WLAN_L OUT 15 45 (1.8_S2R; PUSH-PULL; NO PD REQ’D PER BB TEAM)
(TEMP1 - BOTTOM SIDE NEAR I/O FLEX CONN) BOARD_TEMP1_P NET_SPACING_TYPE=ANLG N30 TDEV1 GPIO5 D20 RST_BB_PMU_L 30 45 (1.8_S2R; PUSH-PULL)
OUT
(TEMP2 - BOTTOM SIDE NEAR PMU) BOARD_TEMP2_P NET_SPACING_TYPE=ANLG M30 TDEV2 GPIO6 D14 BATTERY_SWI 5 34 (FALLING EDGE SENSITIVE) 2.5V ALWAYS ON PU IN BMU
1 IN
(TEMP3 - BOTTOM SIDE NEAR H4G) BOARD_TEMP3_P NET_SPACING_TYPE=ANLG M29 TDEV3 GPIO7 D19 PM_BT_HOST_WAKE 15 (INTERNAL PD; RISING EDGE SENSITIVE)
1 IN
CRITICAL (TEMP4 - BOTTOM SIDE NEAR WIFI) L30 E16
BOARD_TEMP4_P NET_SPACING_TYPE=ANLG TDEV4 GPIO8 PM_WLAN_HOST_WAKE (INTERNAL PD; RISING EDGE SENSITIVE)
TEMPERATURE
R8216
GPIO
IN 15
CRITICAL 1
BOARD_TEMP5_P NET_SPACING_TYPE=ANLG A29 TDEV5 GPIO9 D17 PM_BB_HOST_WAKE (INTERNAL PD; RISING EDGE SENSITIVE) CAN’T BE USED FOR 32K CLK OUTPUT
10KOHM-1% R8222 CRITICAL 0201 37 IN 30
BOARD_TEMP6_P NET_SPACING_TYPE=ANLG A28 TDEV6 GPIO10 D18 AUD_MIK_HS1_INT_L (INTERNAL PU TO PP1V8_S2R; RISING EDGE SENSITIVE)
0201 10KOHM-1% R8218 37 IN 19
C8215 1 46 NC_BOARD_TEMP7 NET_SPACING_TYPE=ANLG B26 TDEV7 GPIO11 D15 DOCK_BB_EN 11 (1.8_S2R; PUSH-PULL) EXT PD BY BB MUXES
2 0201 10KOHM-1% 1 2 OUT
100PF C8221 1 CRITICAL 46 NC_BOARD_TEMP8 NET_SPACING_TYPE=ANLG D25 TDEV8 GPIO12 K21 NC_PMU_GPIO12 46 NEED RADAR TO STOP GENERATING 32K CLOCK
5% 2 0201
C 6.3V
CERM 2
01005
100PF
5%
6.3V 2
C8217
100PF
1
2
C8223 1
R8280 34 IN BATTERY_NTC
PMU_TCAL NET_SPACING_TYPE=ANLG
C30
D26
TBAT
TCAL
GPIO13
GPIO14
J20
K20
NC_PMU_GPIO13
RST_L63_L
46
19 45 (INTERNAL PU TO 1.8_S2R)
C
CERM 5% 10KOHM-1% OUT
01005 6.3V 100PF 2 CRITICAL GPIO15 J19 IRQ_HALL (BOTH EDGES SENSITIVE) EXT PU
CERM 2 5% R8219 IN 25
01005 6.3V 2 C8220 1 PM_KEEPACT B28 KEEPACT K19 NC_PMU_GPIO16
3.92K GPIO16
WDOG
CERM XW8203 0.1%
5 IN 46
01005 BOARD_TEMP4_N 1 2 100PF 402 39 IN PMU_SHDWN (INTERNAL PULL-DOWN) A2 SHDN GPIO17 J18 NC_PMU_GPIO17 46
5%
XW8202 SM 6.3V
CERM 2
1/16W NET_SPACING_TYPE=ANLG
BOARD_TEMP3_N 1 2 NOSTUFF 1 MF
01005 RST_PMU_IN (INTERNAL PULL-DOWN) B30 RESET_IN
XW8201 SM 45 4 IN
RESET
NOSTUFF PLACE XW AND CAP B29 RESET* J28
BOARD_TEMP2_N 1 2 45 30 27 4 OUT RST_AP_L AMUX_A0 NC_PMU_AMUX_A0 46
XW8200 SM PLACE XW AND CAP
CLOSE TO PMU
5 IRQ_PMU_L (PULLUP INSIDE H4P) B27 IRQ* AMUX_A1 H28 NC_PMU_AMUX_A1 46
(WHAT SIGNALS DO YOU WANT MEASURED?)
BOARD_TEMP1_N 1 2 NOSTUFF RESISTOR FOR TEMP CALIBRATION OUT
PLACE XW AND CAP CLOSE TO PMU AMUX_A2 K26 NC_PMU_AMUX_A2 46
PLACE XW AND CAP SM
NOSTUFF CLOSE TO PMU I2C0_SCL_1V8 C29 SCL AMUX_A3 K27 NC_PMU_AMUX_A3
ANALOG MUX
42 22 19 10 5 IN 46
CLOSE TO PMU
I2C & DWI

42 22 19 10 5 BI I2C0_SDA_1V8 D30 SDA AMUX_AY K29 NC_PMU_AMUX_AY 46
AMUX_B0 G28 NC_PMU_AMUX_B0 46
42 5 DWI_AP_CLK (INTERNAL PULL-DOWN) N29 DWI_CK AMUX_B1 F28 NC_PMU_AMUX_B1 46 (NOTE: 2MHZ)
IN
DWI NAMING RELATIVE TO AP (INTERNAL PULL-DOWN) M27 DWI_DI E28 CRICITAL
DWI_AP_DO AMUX_B2 NC_PMU_AMUX_B2
42 5 IN
DWI_AP_DI M28 DWI_DO AMUX_B3 D27 NC_PMU_AMUX_B3
46
L8229
42 5 OUT 46 2.2UH-1.05A-0.195OHM
CRITICAL CRITICAL AMUX_BY D29 NC_PMU_AMUX_BY 46 CRICITAL
1 2
L8225 D8228 WLED_LX_A M21 MAKE_BASE=TRUE
VLS201612E-SM
MIN_LINE_WIDTH=0.4 MM D8230
4.7UH-3.2A PMEG4010BEA MIN_LINE_WIDTH=0.6 MM
NET_SPACING_TYPE=SWITCHNODE
DIDT=TRUE N21 WLED_LXA VDD_LCM_SW M25 PPVCC_MAIN 35 36 45
VOLTAGE=6.0V
NET_SPACING_TYPE=SWITCHNODE PMEG2005AEL
1 2 (PPLED_OUT_A) K22 N26 MIN_NECK_WIDTH=0.2MM DIDT=TRUE
37 35 =PPVCC_MAIN_LED VOUT_WLED_A VDD_BOOST_LCM
45 PP6V0_LCM_HI NET_SPACING_TYPE=PWR
1 2 1 2
CRITICAL PIME051E-SM R8227 43 LED_IO1_A_R N15 WLED1_A LX_BOOST_LCM M24 LCM_LX
DCR=106MOHM MAX SOD-323 1.00 SOD882

C8226 1 43 16 OUT LED_IO_1_A 1 2 43 LED_IO2_A_R M15 WLED2_A LCM_FB
45 N25 PP6V0_LCM_VBOOST
10UF MIN_LINE_WIDTH=0.1 MM
MIN_NECK_WIDTH=0.1 MM 1%
MIN_NECK_WIDTH=0.1 MM 43 LED_IO3_A_R N16 WLED3_A VDD_LCM M14 MAKE_BASE=TRUE
VOLTAGE=6.0V
20%
10V 2 R8231 1/20W
M16 K30 MIN_LINE_WIDTH=0.4MM
BACKLIGHT
X5R
MF 43 LED_IO4_A_R WLED4_A LCM2_EN NC_LCM2_EN 46
(INTERNAL PULLDOWN; TE ENABLE) MIN_NECK_WIDTH=0.2MM
603 1.00 201 NET_SPACING_TYPE=PWR
LCM/GRAPE
LED_IO_2_A 1 2 LED_IO5_A_R N17 N14
LED
43 16 OUT 43 WLED5_A VLCM1 NC_VLCM1 46 MAX_NECK_LENGTH=3 MM
MIN_LINE_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.1 MM 1% MIN_NECK_WIDTH=0.1 MM 43 LED_IO6_A_R M17 WLED6_A VLCM2 M13 PP5V25_VLCM2 35 45
45 37 35 PPLED_OUT_A 1/20W
R8232
B CRITICAL CRITICAL CRITICAL CRITICAL
43 16 OUT LED_IO_3_A
MF
201
1
1.00
2 M23
VLCM3 N13 BB_VBUS_DET OUT 30
B
1 C8232 1 C8233 1 C8234 1 C8235 MIN_LINE_WIDTH=0.1 MM
1%
MIN_LINE_WIDTH=0.2 MM NET_SPACING_TYPE=SWITCHNODE
N23 WLED_LXB C8240 1 1 C8238
4.7UF 4.7UF 4.7UF 4.7UF MIN_NECK_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM DIDT=TRUE
2.2UF 1UF
10% 10% 10% 10% R8235 1/20W
MF K23 VOUT_WLED_B 10% 10%
2 35V
X5R-CERM 2 35V
X5R-CERM 2 35V
X5R-CERM 2 35V
X5R-CERM 1.00 201 6.3V 2
X5R 2 6.3V
CERM
43 16 OUT LED_IO_4_A 1 2 43 LED_IO1_B_R N18 WLED1_B
0603 0603 0603 0603 402 402
MIN_NECK_WIDTH=0.1 MM 1% MIN_NECK_WIDTH=0.1 MM 43 LED_IO2_B_R N19 WLED2_B
1/20W
MF R8239 43 LED_IO3_B_R M18 WLED3_B C8236 1 1 C8237
201 1.00 2.2UF 10UF
43 16 OUT LED_IO_5_A 1 2 43 LED_IO4_B_R N20 WLED4_B
20% 20%
1% LED_IO5_B_R M19 WLED5_B 10V 2 10V
X5R-CERM 2
MIN_NECK_WIDTH=0.1 MM MIN_NECK_WIDTH=0.1 MM 43
X5R
R8240 1/20W
MF 43 LED_IO6_B_R M20 WLED6_B 402 0603-1
1.00 201
43 16 LED_IO_6_A 1 2
OUT
1/20W
MIN_NECK_WIDTH=0.1 MM I2C ADDRESS: 0111100X (0X78)
MF
201
WLED_LX_B
CRITICAL CRITICAL MIN_NECK_WIDTH=0.25 MM
(PPLED_OUT_B)
L8255 D8258
4.7UH-3.2A PMEG4010BEA PPLED_OUT_A 35 37 45
=PPVCC_MAIN_LED 1 2
37 35
1 2 R8257 C8266 1
CRITICAL PIME051E-SM 1.00
DCR=106MOHM MAX SOD-323 43 16 OUT LED_IO_1_B 1 2 C8201 1 0.01UF PLACEMENT_NOTE=PLACE NEAR U8100.K22
C8256 1 MIN_LINE_WIDTH=0.1 MM MIN_LINE_WIDTH=0.2 MM
0.01UF
10%
50V
10UF MIN_NECK_WIDTH=0.1 MM 1% MIN_NECK_WIDTH=0.1 MM
10% X7R 2
PLACEMENT_NOTE=PLACE NEAR U8100.K22
20%
10V 2
R8261 1/20W
MF 50V 2
X7R
402
X5R 1.00 201
402
43 16 LED_IO_2_B 1 2
603 OUT
MIN_NECK_WIDTH=0.1 MM 1% MIN_NECK_WIDTH=0.1 MM
45 37 35 PPLED_OUT_B
1/20W
MF R8262 PPLED_OUT_B 35 37 45
201 1.00
CRITICAL CRITICAL CRITICAL CRITICAL 43 16 OUT LED_IO_3_B 1 2 C8267 1
1 C8262 1 C8263 1 C8264 1 C8265
C8251 1 0.01UF
A 4.7UF
10% 10%
4.7UF
10%
4.7UF 4.7UF
10%
R8265
1.00
1%
1/20W
MF
201
0.01UF
10%
10%
50V
X7R 2
PLACEMENT_NOTE=PLACE NEAR U8100.K23
PLACEMENT_NOTE=PLACE NEAR U8100.K23 SYNC_MASTER=MLB SYNC_DATE=01/14/2011 A
35V 35V 35V 35V LED_IO_4_B 1 2 50V 402 PAGE TITLE
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 43 16 OUT X7R 2
0603 0603 0603 0603 MIN_LINE_WIDTH=0.1 MM
1/20W
R8269
402 POWER: AMELIA PMU
MF DRAWING NUMBER SIZE
201 1.00
43 16 OUT LED_IO_5_B
1 2
MIN_LINE_WIDTH=0.2 MM Apple Inc. 051-8773 D
MIN_NECK_WIDTH=0.1 MM 1% MIN_NECK_WIDTH=0.1 MM REVISION
R8270 1/20W
MF
R
10.0.0
1.00 201
43 16 OUT LED_IO_6_B 1 2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
MIN_NECK_WIDTH=0.1 MM 1% MIN_NECK_WIDTH=0.1 MM THE INFORMATION CONTAINED HEREIN IS THE
1/20W PROPRIETARY PROPERTY OF APPLE INC.
MF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
201
82 OF 157
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U8100 OMIT U8100 OMIT

D1974AB D1974AB
D TFBGA
SYM 3 OF 4 F3
TFBGA
SYM 4 OF 4 H24
D
A3 A8 F4 H25
B1 VSS_BUCK02 B8 F5 H26
B2 B6 F6 H27
B4 B11 F8 H4
C2 VSS_BUCK3 B17 G10 H6
D10 A15 G11 H7
D11 VSS_BUCK34 B15 G12 H8
D22 D1 G13 H9
D23 VSS_BUCK5 D2 G14 J1
D24 VSSA_BUCK0 D8 G15 J10
D4 VSSA_BUCK2 D6 G16 J11
D9 VSSA_BUCK3 E15 G17 J12
E10 VSSA_BUCK4 D12 G18 J13
E11 VSSA_BUCK5 C1 G19 J14
E12 G20 J15
E13 M22 G21 J16
E14 VSS_WLED N22 G22 J2
E17 VSS VSS_LCM N24 G23 J21
E18 G24 J22
E19 F11 G25 J23
E20 F12 G26 VSS VSS J24
E21 F13 G27 J25
E22 F14 G4 J26
C E23 F15 G5 J27 C
E24 F16 G6 J3
E25 F17 G7 J4
E26 F18 G8 J5
E27 VSS F19 G9 J6
E3 F20 H10 J7
E4 F21 H11 J8
E5 F22 H12 J9
E6 F23 H13 K11
E7 F24 H14 K12
E8 F25 H15 K13
E9 F26 H16 K14
F10 F27 H17 K15
H18 K25
H19 K5
H20 K6
H21 K7
H22 K8
H23 M3
B B
A SYNC_MASTER=MADHAVI SYNC_DATE=01/13/2011 A
PAGE TITLE
POWER: AMELIA VSS

DRAWING NUMBER SIZE

REVISION
R
10.0.0
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DEBUG RESET ACCESS D

D
35 27 5 =PP1V8_S2R_MISC PLACE OUTSIDE OF CAN

NOSTUFF PPBATT_VCC
45 36 35
1
R9000
300
5%
1/20W NOSTUFF
MF 1
2 201 R9002
1.5K
1%
FORCE_DFU 1/20W
5 OUT MF PMU_SHDWN
2 201 37 OUT
PWR_ON_LED NOSTUFF
1
R9001
A NOSTUFF 300
5%
LED9000 1/20W
RED-50MCD-20MA MF
0603 2 201
C K
C
B B
A SYNC_MASTER=ALEX SYNC_DATE=10/04/2010 A
PAGE TITLE
DEBUG AND MISC

DRAWING NUMBER SIZE

REVISION
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PROBE POINTS
PP0
P4MM
SM
1 CODEC_LINE_OUT_REF 19 21
PP
PP1
P4MM
SM
1 CODEC_LINE_OUT_R 19 21
PP
PP2
P4MM
SM
1 AUD_SPKR_AMP2_PBUS 20
PP
D PP3
P4MM
D
SM
1 AUD_SPKR_AMP1_PBUS 20
PP
PLATED THROUGH HOLES PP4
P4MM
DRILL SIZE: 1.1MM X 0.4MM SM
1 CODEC_LINE_OUT_L
PP 19 21
PLATING SIZE: 1.4MM X 0.7MM
PP5
P4MM
FID9300 SL9300 SL9310
TH-NSP
SM
PP
1 DDR0_DQS_P<0> 8 13 44
FID TH-NSP 1
0P5SM1P0SQ-NSP
1
1
SL-1.1X0.4-1.4X0.7
PP6
P4MM
SL-1.1X0.4-1.4X0.7 SM
1 DDR0_DQ<0>
FID9301 PP 8 13 44
FID SL9301
0P5SM1P0SQ-NSP TH-NSP PP7
P4MM
1 1 SM
1 DDR0_DQS_N<0> 8 13 44
PP
FID9302 SL-1.1X0.4-1.4X0.7
FID PP8
P4MM
0P5SM1P0SQ-NSP SM
1 1 DDR0_DQS_N<1> 8 13 44
PP
FID9303 SL9302 SL9312

FID TH-NSP 1
TH-NSP PP9
P4MM
1 SM
0P5SM1P0SQ-NSP 1 DDR0_DQ<14>
1 SL-1.1X0.4-1.4X0.7 PP 8 13 44
SL-1.1X0.4-1.4X0.7
FID9304 PP10
P4MM
FID SL9313 SM
1 HSIC1_WLAN_DATA1
0P5SM1P0SQ-NSP TH-NSP PP 4 15 42
1 1
PP11
P4MM
FID9305 SL-1.1X0.4-1.4X0.7
SM
1
FID PP HSIC1_WLAN_STB1 4 15 42
C 0P5SM1P0SQ-NSP
1
SL9314 PP12
P4MM
C
SL9304 TH-NSP SM
TH-NSP 1 1 Z1_BON_L<5> 17 18
1 PP
SL-1.1X0.4-1.4X0.7
SL-1.1X0.4-1.4X0.7
PP13
P4MM
SM
1 Z1_B_ADR<2> 17 18
PP
SL9305 SL9315
TH-NSP 1
TH-NSP PP14
P4MM
1 SM
SL-1.1X0.4-1.4X0.7 1 Z1_B_ADR<1> 17 18
PP
SL-1.1X0.4-1.4X0.7
PP15
P4MM
SL9306 SL9316
TH-NSP
SM
PP
1 Z1_B_ADR<0> 17 18
TH-NSP 1
1
SL-1.1X0.4-1.4X0.7
PP16
P4MM
SL-1.1X0.4-1.4X0.7 SM
1 Z1_MISO 17 18
PP
PP17
P4MM
SM
1 Z1_BON_L<4> 17 18
PP
PP18
P4MM
SM
1 PP1V7_VA_VCP 35 36 45
PP
PP19
P4MM
SM
1 CONN_AUD_HEADSET_CHS_RET2 23 24
PP
PP20
P4MM
SM
B PP
1 CONN_AUD_HEADSET_CHS_MIC2 23 24
B
PP21
P4MM
SM
1 CONN_AUD_HEADSET_DET 23 24
PP
PP22
P4MM
SM
1 AUD_HP1_DET_H 23
PP
PP23
P4MM
SM
1 AUD_HS_MIC2_RET 22 23
PP
PP24
P4MM
SM
1 AUD_HS_MIC1_HI 22 23
PP
PP25
P4MM
SM
1 AUD_HS_MIC1_RET 22 23
PP
PP26
P4MM
SM
1 AUD_HS_MIC2_HI 22 23
PP
A SYNC_MASTER=ALEX SYNC_DATE=10/04/2010 A
PAGE TITLE
FCT/ICT TEST/BRACKETS
DRAWING NUMBER SIZE

REVISION
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MLB CONSTRAINTS
TABLE_BOARD_INFO
BOARD LAYERS BOARD AREAS BOARD UNITS ALLEGRO

(MIL or MM) VERSION
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA,BGA06-06 MM 16.2
D D
PHYSICAL CONSTRAINTS SPACING CONSTRAINTS
TABLE_PHYSICAL_RULE_HEAD
DEFAULT/BGA SPACING RULES
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_HEAD
ON LAYER? SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT

TABLE_PHYSICAL_RULE_ITEM
DEFAULT * Y =45_OHM_SE =45_OHM_SE 30 MM 0 MM 0 MM TABLE_SPACING_RULE_ITEM
DEFAULT * 0.100 MM ?
STANDARD * Y =DEFAULT =DEFAULT 12.7 MM =DEFAULT =DEFAULT TABLE_SPACING_RULE_ITEM
STANDARD * =DEFAULT ?
TABLE_SPACING_RULE_ITEM
BGA_SPA * =DEFAULT ?
REGULAR SPACING RULES

SINGLE-ENDED PHYSICAL RULES SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
TABLE_SPACING_RULE_HEAD
45 OHMS TABLE_SPACING_RULE_ITEM
1:1_SPACING * 0.057 MM ?
PHYSICAL_RULE_SET LAYER ALLOW ROUTE
ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM
NOTES:
0P08_SPACING * 0.080 MM ?
45_OHM_SE ISL1,ISL12 Y 0.110 MM 0.060 MM 3.0 MM TABLE_SPACING_RULE_ITEM
45_OHM_SE ISL5,ISL8 Y 0.077 MM 0.060 MM 3.0 MM

1.5:1_SPACING * 0.086 MM ? 0.075 MM ~ 3 MIL

2:1_SPACING * 0.114 MM ?
45_OHM_SE ISL3 Y 0.055 MM 0.050 MM 3.0 MM TABLE_SPACING_RULE_ITEM
0.089 MM ~ 3.5 MIL
2.5:1_SPACING * 0.143 MM ?
45_OHM_SE * N 0.055 MM 0.050 MM 3.0 MM
3:1_SPACING * 0.171 MM ?
0.102 MM ~ 4 MIL
C 50 OHMS
4:1_SPACING * 0.228 MM ?
0.114 MM ~ 4.5 MIL C
5:1_SPACING * 0.285 MM ?
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP
DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM

0.125 MM ~ 5 MIL
ON LAYER? 0P5MM_SPACING * 0.5 MM ?

0P64MM_SPACING * 0.64 MM ?
0.140 MM ~ 5.5 MIL

50_OHM_SE ISL3 Y 0.050 MM 0.050 MM 3.0 MM

*NOTE: ASSUMING 0.060MM DIELECTRIC THICKNESS 0.15 MM ~ 6 MIL
50_OHM_SE * N 0.050 MM 0.050 MM 3.0 MM

0.18 MM ~ 7 MIL
0.2 MM ~ 8 MIL
0.25 MM ~ 10 MIL
POWER/GND SPACING RULES 0.3 MM ~ 12 MIL
TABLE_SPACING_RULE_HEAD
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT
PWR_P1SPACING * 0.1 MM 900

0.33 MM ~ 13 MIL
GND_P1SPACING * 0.1 MM 950 0.4 MM ~ 16 MIL

SWITCHNODE * 0.5 MM 1000

1.0 MM = 39.37 MIL
SWITCHNODE TOP,BOTTOM 0.2 MM 1000
B DIFFERENTIAL PAIR PHYSICAL RULES POWER B

PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
ON LAYER?
90 OHMS PWR * Y 0.6MM 0.25 MM 10.0 MM
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM
ON LAYER? GND_PH * Y 0.6MM 0.075 MM 10.0 MM

90_OHM_DIFF TOP,BOTTOM Y 0.085 MM 0.085 MM 0.110 MM 0.110 MM

90_OHM_DIFF ISL3 Y 0.051 MM 0.051 MM =STANDARD 0.120 MM 0.120 MM

90_OHM_DIFF ISL5,ISL8 Y 0.072 MM 0.075 MM =STANDARD 0.120 MM 0.120 MM
MISC
MISC PHYSICAL RULES NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_HEAD
PHYSICAL_RULE_SET LAYER ALLOW ROUTE MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_ASSIGNMENT_ITEM
ON LAYER? * * BGA BGA_SPA

1:1_DIFFPAIR * Y =STANDARD =STANDARD =STANDARD 0.08 MM 0.08 MM TABLE_SPACING_ASSIGNMENT_ITEM
CLK * BGA BGA_SPA
SPEAKER * Y 0.3 MM 0.19MM 10 MM 0.08 MM 0.08 MM TABLE_SPACING_ASSIGNMENT_ITEM
PWR * * PWR_P1SPACING
LED * Y 0.2 MM 0.10MM 10 MM 0.08 MM 0.08 MM TABLE_SPACING_ASSIGNMENT_ITEM
GND * * GND_P1SPACING
TABLE_SPACING_ASSIGNMENT_ITEM
SWITCHNODE * * SWITCHNODE
ANLG * * 3:1_SPACING
LED * * 3:1_SPACING
A BGA AREA PHYSICAL RULES SYNC_MASTER=MIKE SYNC_DATE=01/21/2011 A

TABLE_PHYSICAL_ASSIGNMENT_HEAD PAGE TITLE
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
TABLE_PHYSICAL_ASSIGNMENT_ITEM
CONSTRAINTS: MLB RULES
* BGA BGA_PHY DRAWING NUMBER SIZE

ALLOW ROUTE
REVISION
PHYSICAL_RULE_SET LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP R
ON LAYER?
10.0.0
BGA_PHY * Y 0.060 MM 0.060 MM =STANDARD 0.076 MM 0.075 MM NOTICE OF PROPRIETARY PROPERTY: BRANCH
150 OF 157
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USB
TABLE_PHYSICAL_ASSIGNMENT_HEAD
JTAG NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
Clock Signal Constraints TABLE_SPACING_ASSIGNMENT_HEAD
USB_90D * 90_OHM_DIFF
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET JTAG * * 2:1_SPACING TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_PHYSICAL_ASSIGNMENT_ITEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

CLK_50S * 50_OHM_SE TABLE_SPACING_ASSIGNMENT_ITEM
USB * * 5:1_SPACING
TABLE_SPACING_ASSIGNMENT_HEAD NET_TYPE
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
D CLK * * 5:1_SPACING
I16 JTAG JTAG_AP_TCK 4 27 ELECTRICAL_CONSTRAINT_SET PHYSICAL

NET_TYPE
SPACING
D
JTAG JTAG_AP_TMS 4 27
I15
USB_90D USB USB_DK_D0_P 4 27
I14 JTAG JTAG_AP_TDI 4 10
I5
NET_TYPE USB_90D USB USB_DK_D0_N 4 27
ELECTRICAL_CONSTRAINT_SET JTAG JTAG_AP_TDO 4 10
I6
PHYSICAL SPACING I13
I7 USB_90D USB USB_DK_CON_D0_P
RST JTAG_AP_TRST_L 4 10 45
CLK_50S CLK CLK_32K_PMU 18 37
I20
I8 USB_90D USB USB_DK_CON_D0_N
I63
I162 CLK_50S CLK CLK_32K_WLAN 15 37
CLK_50S CLK CLK_32K_GPS I82 USB_90D USB USB_BB_D_P 11 30

I81
CLK_50S CLK CLK_CAM_FF 7 25 I83 USB_90D USB USB_BB_D_N 11 30
I88
CLK_50S CLK CLK_CAM_FF_FILT 25 I84 USB_90D USB USB11_MUX_D0_P 4 11
I89
SE_50S 0P2MM_SPACING CLK_CAM_FF_CONN 24 25 I85 USB_90D USB USB11_MUX_D0_N 4 11
I95
I96 CLK_50S CLK CLK_CAM_RF 7 25

USB_90D USB USB11_ACC_TX_N 11 27
I128
I94 CLK_50S CLK CLK_CAM_RF_FILT 25
USB_90D USB USB11_ACC_RX_P 11 27
I129
I225 CLK_50S CLK CLK_CAM_RF_CONN 24 25
I2C USB_90D USB ACC_PT_DK_CON_TX 27 29
I171
I130 CLK_50S CLK I2S0_ASP_MCK 5
USB_90D USB ACC_PT_DK_CON_RX 27 29
I172
I131 CLK_50S CLK I2S0_ASP_MCK_R 5 19
NET_PHYSICAL_TYPE AREA_TYPE
PHYSICAL_RULE_SET
I157 CLK_50S CLK CLK_CAM_FF_R 7 TABLE_PHYSICAL_ASSIGNMENT_ITEM
I204 USB_90D USB EXTRA_USB_D1_N
CLK_50S CLK CLK_CAM_RF_R 7
I2C_50S * 50_OHM_SE USB_90D USB EXTRA_USB_D1_P
I158 I206
I234 CLK_50S CLK CLK_CAM_FF_C 25 TABLE_SPACING_ASSIGNMENT_HEAD
I205 USB_90D USB NC_USB11_D1_N 4 46
I235 CLK_50S CLK CLK_CAM_RF_C 25

I207 USB_90D USB NC_USB11_D1_P 4 46
I2C * * 1.5:1_SPACING
I208 USB_90D USB NC_USB_D1_N 4 46
I209 USB_90D USB NC_USB_D1_P 4 46

UART NET_TYPE
I210 USB_90D USB TP_WLAN_USB_DN
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
USB_90D USB TP_WLAN_USB_DP
I211
I1 I2C_50S I2C I2C1_SDA_1V8 5 10 25 I212 USB_90D USB USB_GPIO_DM
UART_50S * 50_OHM_SE I2C_50S I2C I2C1_SCL_1V8 USB_90D USB USB_GPIO_DM_CONN
C I2
I3 I2C_50S I2C I2C0_SDA_1V8

5 10 25
5 10 19 22 37
I214
I213 USB_90D USB USB_GPIO_DP C

I4 I2C_50S I2C I2C0_SCL_1V8 5 10 19 22 37 I215 USB_90D USB USB_GPIO_DP_CONN

I2C_50S I2C I2C2_SDA_3V0 5 25
I61
USB_90D USB USB_PT_DK_CON_D_N 27 29
UART * * 3:1_SPACING I2C_50S I2C I2C2_SCL_3V0 5 25
I216
I62
USB_90D USB USB_PT_DK_CON_D_P 27 29
I2C_50S I2C ISP_AP_0_SCL 7 25

I217
UART UART * 2:1_SPACING
I98
USB_90D USB USB_UART_DM
I2C_50S I2C ISP_AP_0_SDA 7 25
I218
I99
I219 USB_90D USB USB_UART_DM_CONN
I100 I2C_50S I2C ISP_AP_1_SCL 7 25
I2C_50S I2C ISP_AP_1_SDA 7 25 I222 USB_90D USB USB_UART_DP

I101
NET_TYPE
I2C_50S I2C I2C2_SCL_3V0_ALS 10 24 25 I221 USB_90D USB USB_UART_DP_CONN
I102
I103 I2C_50S I2C I2C2_SDA_3V0_ALS 10 24 25
USB_90D USB EXTRA_USB11_D1_N
UART_50S UART UART0_AP_RXD 5 15 I223
I237
I228 I2C_50S I2C I2C1_SCL_1V8_CONN 24 25
USB_90D USB EXTRA_USB11_D1_P
UART_50S UART UART0_AP_TXD 5 15 I224
I236
I229 I2C_50S I2C I2C1_SDA_1V8_CONN 24 25
UART_50S UART UART0_MUX_RXD 11 15
I174
I124 I2C_50S I2C ISP_CAM_1_SCL 24 25
UART_50S UART UART0_MUX_TXD 11 15
I173
I125 I2C_50S I2C ISP_CAM_1_SDA 24 25
UART_50S UART UART1_BB_CTS_L 5 30
I175
I226 I2C_50S I2C ISP_CAM_0_SCL 24 25
UART_50S UART UART1_BB_RTS_L 5 30
I176
I227 I2C_50S I2C ISP_CAM_0_SDA 24 25
UART_50S UART UART1_BB_TXD
I177
UART_50S UART UART1_BB_RXD
5 30
5 30
HSIC
I178
I179 UART_50S UART UART3_BT_CTS_L 5 15


I182 UART_50S UART UART3_BT_RTS_L 5 15 XTAL TABLE_PHYSICAL_ASSIGNMENT_ITEM
I181 UART_50S UART UART3_BT_RXD 5 15 HSIC * 50_OHM_SE

I180 UART_50S UART UART3_BT_TXD 5 15 NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

I232 UART_50S UART UART6_WLAN_RXD 5 15
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD
CRYSTAL * * 5:1_SPACING NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

I233 UART_50S UART UART6_WLAN_TXD 5 15
HSIC * * 5:1_SPACING
NET_TYPE
B SPI I92 CRYSTAL XTAL_24M_I 4 ELECTRICAL_CONSTRAINT_SET PHYSICAL

NET_TYPE
SPACING
B
I90 CRYSTAL XTAL_24M_O 4
24M_O I191 HSIC HSIC_BB HSIC0_BB_DATA1 4 30

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET CRYSTAL 4
I93
I194 HSIC HSIC_BB HSIC0_BB_STB1 4 30
CRYSTAL PMU_XTAL 36
SPI_50S * 45_OHM_SE I230
HSIC HSIC_WLAN HSIC1_WLAN_DATA1 4 15 40
I231 CRYSTAL PMU_EXTAL 36
I193
I192 HSIC HSIC_WLAN HSIC1_WLAN_STB1 4 15 40
NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET I195 HSIC HSIC HSIC_BB_RDY 5 30
SPI * * 2:1_SPACING
I2S I196 HSIC HSIC HSIC_HOST_RDY 5 30
I197 HSIC HSIC HSIC_HOST_READY_WL 5
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET I198 HSIC HSIC HSIC_HOST_READY_WLAN 5 15

NET_TYPE TABLE_PHYSICAL_ASSIGNMENT_ITEM
I199 HSIC HSIC HSIC_WLAN_RDY 5 15

ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING I2S_90S * 45_OHM_SE
I200 HSIC HSIC NC_HSIC0_DATA2 4 46
I183 SPI_50S SPI SPI1_GRAPE_MISO 5 17

I201 HSIC HSIC NC_HSIC0_STB2 4 46
I184 SPI_50S SPI SPI1_GRAPE_MOSI 5 17 NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET I202 HSIC HSIC NC_HSIC1_DATA2 4 46
I185 SPI_50S SPI SPI1_GRAPE_SCLK 5 17

I203 HSIC HSIC NC_HSIC1_STB2 4 46

I2S * * 3:1_SPACING
I186 SPI_50S SPI SPI1_GRAPE_CS_L 5 17
I2S I2S * 2:1_SPACING

I187 SPI_50S SPI SPI2_IPC_MISO 5 30
I188 SPI_50S SPI SPI2_IPC_MOSI 5 30
I189 SPI_50S SPI SPI2_IPC_SCLK 5 30

NET_TYPE
I190 SPI_50S SPI SPI2_IPC_SRDY 5 30
I140 I2S_50S I2S I2S0_ASP_BCLK 5 19
DWI I143 I2S_50S I2S I2S0_ASP_LRCK 5 19
I142 I2S_50S I2S I2S0_ASP_DIN 5 19

I141 I2S_50S I2S I2S0_ASP_DOUT 5 19

A DWI * * 2:1_SPACING
I159
I144
I2S_50S
I2S_50S
I2S
I2S
I2S_L63_ASP_SDOUT
I2S2_VSP_BCLK
19
5 15 19
SYNC_MASTER=MIKE SYNC_DATE=01/21/2011 A
PAGE TITLE
I2S_50S I2S I2S2_VSP_LRCK
NET_TYPE
I148
I147 I2S_50S I2S I2S2_VSP_DIN

5 15 19
5 15 19
CONSTRAINTS: LOW SPEED BUS
I2S_50S I2S I2S2_VSP_DOUT 5 15 19
DRAWING NUMBER SIZE
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING I146
I160 I2S_50S I2S I2S_L63_VSP_SDOUT 19

I152 DWI DWI_AP_CLK 5 37
I2S_50S I2S I2S3_XSP_BCLK 5 19
REVISION
I145 R
I153 DWI DWI_AP_DI 5 37
I149 I2S_50S I2S I2S3_XSP_LRCK 5 19
10.0.0
I156 DWI DWI_AP_DO 5 37
I150 I2S_50S I2S I2S3_XSP_DIN 5 19
I2S_50S I2S I2S3_XSP_DOUT 5 19

I151 PROPRIETARY PROPERTY OF APPLE INC.
I2S_50S I2S I2S_L63_XSP_SDOUT 19
I161
151 OF 157
8 7 6 5 4 3 2 1
WWW.AliSaler.Com
8 7 6 5 4 3 2 1
ANALOG VIDEO CONSTRAINTS EMBEDDED DISPLAYPORT

TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_HEAD
ALLOW ROUTE
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

PHYSICAL_RULE_SET LAYER ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM
EDP_90D * 90_OHM_DIFF EDP_50S * 50_OHM_SE

VID_50S * Y =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD

NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM
EDP * * 5:1_SPACING
ANALOG_VIDEO * * 5:1_SPACING
NET_TYPE
ANALOG_VIDEO ANALOG_VIDEO * 3:1_SPACING
D NET_TYPE
I435 EDP_90D EDP EDP_AP_AUX_N 7 16 D
EDP_90D EDP EDP_AP_AUX_P 7 16
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING DISPLAYPORT I436
I437 EDP_50S EDP EDP_AP_HPD 7 16

TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_PHYSICAL_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET EDP_90D EDP EDP_AP_TX_N<0> 7 16

VID_50S ANALOG_VIDEO DAC_AP_OUT1 7 11
I439
I213 TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM
EDP_90D EDP EDP_AP_TX_N<1> 7 16

VID_50S ANALOG_VIDEO DAC_AP_OUT2 7 11 DP_90D * 90_OHM_DIFF DP_50S * 50_OHM_SE I438
I214
EDP_90D EDP EDP_AP_TX_N<2> 7 16
I215 VID_50S ANALOG_VIDEO DAC_AP_OUT3 7 11
I440
I442 EDP_90D EDP EDP_AP_TX_N<3> 7 16

I232 VID_50S ANALOG_VIDEO BUF_C_Y 11
I441 EDP_90D EDP EDP_AP_TX_P<0> 7 16
I231 VID_50S ANALOG_VIDEO BUF_CVBS_PB 11 DP * * 5:1_SPACING I444 EDP_90D EDP EDP_AP_TX_P<1> 7 16
I233 VID_50S ANALOG_VIDEO BUF_Y_PR 11 I443 EDP_90D EDP EDP_AP_TX_P<2> 7 16
NET_TYPE
EDP_90D EDP EDP_AP_TX_P<3> 7 16
VID_50S ANALOG_VIDEO VIDEO_EMI_CVBS_PB 10 11 27 ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
I445
I219
EDP_90D EDP EDP_AUX_CONN_N 16
VID_50S ANALOG_VIDEO VIDEO_EMI_C_Y 10 11 27 I447
I220
DP_90D DP DP_AP_AUX_N 7 28 EDP_90D EDP EDP_AUX_CONN_P 16
VID_50S ANALOG_VIDEO VIDEO_EMI_Y_PR 10 11 27 I416 I446
I221
I417 DP_90D DP DP_AP_AUX_P 7 28 I449 EDP_90D EDP EDP_DATA_CONN_N<0> 16
I222 VID_50S ANALOG_VIDEO VIDEO_PT_DK_CON_CVBS_PB 27 28

I418 DP_50S DP DP_AP_HPD 7 37 I448 EDP_90D EDP EDP_DATA_CONN_N<1> 16
I224 VID_50S ANALOG_VIDEO VIDEO_PT_DK_CON_C_Y 27 28 I419 DP_90D DP DP_AP_TX_N<0> 7 28 I450 EDP_90D EDP EDP_DATA_CONN_N<2> 16
I223 VID_50S ANALOG_VIDEO VIDEO_PT_DK_CON_Y_PR 27 28 I420 DP_90D DP DP_AP_TX_N<1> 7 28 I451 EDP_90D EDP EDP_DATA_CONN_N<3> 16
DP_90D DP DP_AP_TX_P<0> 7 28 EDP_90D EDP EDP_DATA_CONN_P<0> 16

VID_50S ANALOG_VIDEO VIDEO_PT_DK_CON_CVBS_PB_R 28 29
I422 I452
I526
I421 DP_90D DP DP_AP_TX_P<1> 7 28 I454 EDP_90D EDP EDP_DATA_CONN_P<1> 16
VID_50S ANALOG_VIDEO VIDEO_PT_DK_CON_C_Y_R 28 29
I527
DP_90D DP DP_EMI_AUX_N 27 28 43 EDP_90D EDP EDP_DATA_CONN_P<2> 16
I528 VID_50S ANALOG_VIDEO VIDEO_PT_DK_CON_Y_PR_R 28 29 I423 I453
I424 DP_90D DP DP_EMI_AUX_P 27 28 43 I455 EDP_90D EDP EDP_DATA_CONN_P<3> 16
I425 DP_90D DP DP_EMI_TX_N<0> 27 28 I457 EDP_90D EDP EDP_EMI_AUX_N 16

I427 DP_90D DP DP_EMI_TX_N<1> 27 28 I456 EDP_90D EDP EDP_EMI_AUX_P 16
I426 DP_90D DP DP_EMI_TX_P<0> 27 28 I458 EDP_90D EDP EDP_EMI_TX_N<0> 16
I428 DP_90D DP DP_EMI_TX_P<1> 27 28 I460 EDP_90D EDP EDP_EMI_TX_N<1> 16
DP_90D DP DP_PT_DK_CON_AUX_N 27 29 43 EDP_90D EDP EDP_EMI_TX_N<2> 16
MIPI I429
DP_PT_DK_CON_AUX_P 27 29 43
I459
EDP_EMI_TX_N<3> 16
C NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
I430
I431
DP_90D
DP_90D
DP
DP DP_PT_DK_CON_TX_N<0> 27 29
I462
I461
EDP_90D
EDP_90D
EDP
EDP EDP_EMI_TX_P<0> 16 C
I432 DP_90D DP DP_PT_DK_CON_TX_N<1> 27 29 I463 EDP_90D EDP EDP_EMI_TX_P<1> 16

MIPI_90D * 90_OHM_DIFF
I433 DP_90D DP DP_PT_DK_CON_TX_P<0> 27 29 I464 EDP_90D EDP EDP_EMI_TX_P<2> 16
I434 DP_90D DP DP_PT_DK_CON_TX_P<1> 27 29 I465 EDP_90D EDP EDP_EMI_TX_P<3> 16

I466 DP_90D DP DP_AP_TX_N<2> 7 28
MIPI * * 4:1_SPACING I467 DP_90D DP DP_AP_TX_N<3> 7 28
I469 DP_90D DP DP_AP_TX_P<2> 7 28
NET_TYPE I468 DP_90D DP DP_AP_TX_P<3> 7 28
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING I470 DP_90D DP DP_EMI_AUX_N 27 28 43 AUDIO/SPEAKER
I471 DP_90D DP DP_EMI_AUX_P 27 28 43 TABLE_PHYSICAL_ASSIGNMENT_HEAD
I472 DP_90D DP DP_EMI_TX_N<2> NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET
I473 DP_90D DP DP_EMI_TX_N<3> AUDIO * 1:1_DIFFPAIR

I474 DP_90D DP DP_EMI_TX_P<2> TABLE_PHYSICAL_ASSIGNMENT_ITEM
DP_90D DP DP_EMI_TX_P<3> SPEAKER * SPEAKER

I475
MIPI_90D MIPI0C MIPI0C_AP_CLK_P 7 25 I476 DP_90D DP DP_PT_DK_CON_AUX_N 27 29 43 TABLE_SPACING_ASSIGNMENT_HEAD
I315
MIPI_90D MIPI0C MIPI0C_AP_CLK_N 7 25 I477 DP_90D DP DP_PT_DK_CON_AUX_P 27 29 43 NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
I316
MIPI_90D MIPI0C MIPI0C_CAM_CLK_P 24 25 I478 DP_90D DP DP_PT_DK_CON_TX_N<2> 28 AUDIO * * 3:1_SPACING
I343
MIPI_90D MIPI0C MIPI0C_CAM_CLK_N 24 25 I479 DP_90D DP DP_PT_DK_CON_TX_N<3> 28
I342
MIPI_90D MIPI0C MIPI0C_AP_DATA_P<0> 7 25 I480 DP_90D DP DP_PT_DK_CON_TX_P<2> 28 NET_TYPE
I311
MIPI_90D MIPI0C MIPI0C_AP_DATA_N<0> 7 25 I481 DP_90D DP DP_PT_DK_CON_TX_P<3> 28 ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
I312
I399 MIPI_90D MIPI0C MIPI0C_AP_DATA_N<1> 7 25 AUDIO AUDIO LEFT_CH_OUT_P 19 20

I506
I398 MIPI_90D MIPI0C NC_MIPI0C_AP_DATA_N<2> 7 46
AUDIO AUDIO LEFT_CH_OUT_REF 19 20
I507
AUDIO AUDIO LEFT_CH_P 20
I508
MIPI_90D MIPI0C MIPI0C_AP_DATA_P<1> 7 25
I396
MIPI_90D MIPI0C NC_MIPI0C_AP_DATA_P<2> 7 BACKLIGHT
I395 46
I511 AUDIO AUDIO MAX983X4_L_IN_N 20
B I394
I519
MIPI_90D
CAM_100DVA3
MIPI0C
CAM
NC_MIPI0C_AP_DATA_P<3> 7
MIPI0C_CAM_DATA_N<0> 24 25
46
NET_PHYSICAL_TYPE AREA_TYPE
PHYSICAL_RULE_SET
I510 AUDIO
AUDIO
AUDIO
AUDIO
MAX983X4_L_IN_P
SPKRAMP_L_OUT_N
20
20
B
I531
MIPI_90D MIPI0C MIPI0C_CAM_DATA_N<1> 24 25 LED * LED
I518
I530 AUDIO AUDIO SPKRAMP_L_OUT_P 20
I521 MIPI_90D MIPI0C MIPI0C_CAM_DATA_N<2> TABLE_SPACING_ASSIGNMENT_HEAD
AUDIO AUDIO RIGHT_CH_OUT_REF 19 20

I512
I520 MIPI_90D MIPI0C MIPI0C_CAM_DATA_N<3> NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET
AUDIO AUDIO RIGHT_CH_OUT_P 19 20
I513
I523 CAM_100DVA3 CAM MIPI0C_CAM_DATA_P<0> 24 25 LED * *
3:1_SPACING AUDIO AUDIO RIGHT_CH_P 20

I529
I522 MIPI_90D MIPI0C MIPI0C_CAM_DATA_P<1> 24 25 AUDIO AUDIO MAX983X4_R_IN_P 20
I514
I525 MIPI_90D MIPI0C MIPI0C_CAM_DATA_P<2> NET_TYPE AUDIO AUDIO MAX983X4_R_IN_N 20
I515
I524 MIPI_90D MIPI0C MIPI0C_CAM_DATA_P<3> ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING AUDIO AUDIO SPKRAMP_R_OUT_N 20
I532
MIPI_90D MIPI0C MIPI0C_CAM_CLK_DEBUG_N I533 AUDIO AUDIO SPKRAMP_R_OUT_P 20

I390
I482 LED LEDA LED_IO1_A_R 37
I389 MIPI_90D MIPI0C MIPI0C_CAM_CLK_DEBUG_P LED LEDB LED_IO1_B_R 37

I484
MIPI_90D MIPI0C MIPI0C_CAM_D0_DEBUG_N AUDIO AUDIO EXT_MIC_P 19 22
I391 I483 LED LEDA LED_IO2_A_R 37
I516
MIPI_90D MIPI0C MIPI0C_CAM_D0_DEBUG_P AUDIO AUDIO EXT_MIC_REF 19 22

I392 I485 LED LEDB LED_IO2_B_R 37
I517
MIPI_90D MIPI0C MIPI0C_CAM_D1_DEBUG_N AUDIO AUDIO HSMIC_C_P 19 22

I535
MIPI_90D MIPI0C MIPI0C_CAM_D1_DEBUG_P I534 AUDIO AUDIO HSMIC_C_N 19 22

MIPI_90D MIPI0C MIPI0C_CAM_D2_DEBUG_N I536 AUDIO AUDIO HSMIC_R_P 22
HSMIC_R_N
MIPI_90D MIPI0C MIPI0C_CAM_D2_DEBUG_P AUDIO AUDIO 22
I537
I386 MIPI_90D MIPI0C MIPI0C_CAM_D3_DEBUG_N LED LEDA LED_IO5_A_R 37

I490
MIPI_90D MIPI0C MIPI0C_CAM_D3_DEBUG_P AUDIO AUDIO AUD_HP1_MLBCON_R 21 23
I539
I538 AUDIO AUDIO AUD_HP1_MLBCON_L 21 23

I492 LED LEDA LED_IO6_A_R 37
I541 AUDIO AUDIO CONN_AUD_HEADSET_RIGHT 23 24
I493 LED LEDB LED_IO6_B_R 37
CONN_AUD_HEADSET_LEFT 23 24
AUDIO AUDIO
I345 MIPI_90D MIPI1C MIPI1C_AP_DATA_P<0> 7 25 I494 LED LEDA LED_IO_1_A 16 37
I540
AUDIO AUDIO HP_R 19 21
I346 MIPI_90D MIPI1C MIPI1C_AP_DATA_N<0> 7 25 I495 LED LEDB LED_IO_1_B 16 37
I542
AUDIO AUDIO HP_L 19 21
I545 MIPI_90D MIPI1C NC_MIPI1C_AP_DATA_P<1> 7 46
I496 LED LEDA LED_IO_2_A 16 37
I543

I497 LED LEDB LED_IO_2_B 16 37
A I347
I348
MIPI_90D
MIPI_90D
MIPI1C
MIPI1C
MIPI1C_AP_CLK_P 7 25
MIPI1C_AP_CLK_N 7 25
I498
I499
LED
LED
LEDA
LEDB
LED_IO_3_A
LED_IO_3_B
16 37
16 37
PAGE TITLE
CAM_100DVGA CAM MIPI1C_CAM_DATA_P<0> 24 25 LED LEDA LED_IO_4_A
I353
I355 CAM_100DVGA CAM MIPI1C_CAM_DATA_N<0> 24 25

I500
I501 LED LEDB LED_IO_4_B

16 37
16 37
CONSTRAINTS: DISPLAY/AUDIO
I354 MIPI_90D MIPI1C MIPI1C_CAM_CLK_P 24 25 I502 LED LEDA LED_IO_5_A 16 37
DRAWING NUMBER SIZE
I356 MIPI_90D MIPI1C MIPI1C_CAM_CLK_N 24 25 I503 LED LEDB LED_IO_5_B 16 37

MIPI_90D MIPI1C MIPI1C_CAM_CLK_DEBUG_N I504 LED LEDA LED_IO_6_A 16 37
R
REVISION
I415
MIPI_90D MIPI1C MIPI1C_CAM_CLK_DEBUG_P I505 LED LEDB LED_IO_6_B 16 37
10.0.0
I414
MIPI1C_CAM_D0_DEBUG_N NOTICE OF PROPRIETARY PROPERTY: BRANCH
I413 MIPI_90D MIPI1C
I412 MIPI_90D MIPI1C MIPI1C_CAM_D0_DEBUG_P PROPRIETARY PROPERTY OF APPLE INC.
152 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DDR
TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
DDR_50S * 50_OHM_SE DDR * * 3:1_SPACING
DDR_90D *
90_OHM_DIFF NAND

NET_TYPE TABLE_PHYSICAL_ASSIGNMENT_ITEM
ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING NAND_50S * 50_OHM_SE
D NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE

SPACING_RULE_SET
D
NAND DEV
I221 DDR_50S DDR DDR0_CA<9..0> 8 13
NAND * * 2:1_SPACING
I222 DDR_50S DDR DDR0_DM<3..0> 8 13

NET_TYPE
I223 DDR_90D DDR DDR0_CK_P 8 13
NET_TYPE
ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING

I225 DDR_90D DDR DDR0_CK_N 8 13
PHYSICAL SPACING
I226 DDR_50S DDR DDR0_CKE<1..0> 8 13
I224 DDR_50S DDR DDR0_CSN<2..0> 8 13

NAND_50S NAND0 FMI0_AD<0> 6 12 I49 NAND_50S NAND0 SLOT0_FMI0_AD<0>
I68
I69
I228 DDR_50S DDR DDR0_ZQ 13
I70
I230 DDR_50S DDR0 DDR0_DQ<7..0> 8 13 40
I71
I229 DDR_50S DDR0 DDR0_DQS_P<0> 8 13 40
I72
I231 DDR_50S DDR0 DDR0_DQS_N<0> 8 13 40
I73
I232 DDR_50S DDR1 DDR0_DQ<15..8> 8 13 40
I74
I233 DDR_50S DDR1 DDR0_DQS_P<1> 8 13
I75
I235 DDR_50S DDR1 DDR0_DQS_N<1> 8 13 40
NAND_50S NAND0 FMI0_ALE 6 12 I57 NAND_50S NAND0 SLOT0_FMI0_ALE
I76
I234 DDR_50S DDR2 DDR0_DQ<23..16> 8 13
NAND_50S NAND0 FMI0_CE0_L 6 12 I58 NAND_50S NAND0 SLOT0_FMI0_CE0_L
I77
NAND_50S NAND0 FMI0_CE1_L 6 12 I59 NAND_50S NAND0 SLOT0_FMI0_CE1_L
I78
I237 DDR_50S DDR2 DDR0_DQS_N<2> 8 13
NAND_50S NAND0 FMI0_CE2_L I60 NAND_50S NAND0 SLOT0_FMI0_CLE
I120
I238 DDR_50S DDR3 DDR0_DQ<31..24> 8 13
NAND_50S NAND0 FMI0_CE3_L I62 NAND_50S NAND0 SLOT0_FMI0_DQS_P
I121
NAND_50S NAND0 FMI0_CE4_L I61 NAND_50S NAND0 SLOT0_FMI0_RE_N
I122
NAND_50S NAND0 FMI0_CE5_L I63 NAND_50S NAND0 SLOT0_FMI0_WE_L
I123
NAND_50S NAND0 FMI0_CE6_L I64 NAND_50S NAND1 SLOT0_FMI1_AD<0>
I124
I125
I201 DDR_50S DDR DDR1_CA<9..0> 8 13
NAND_50S NAND0 FMI0_CLE 6 12 I67 NAND_50S NAND1 SLOT0_FMI1_AD<2>
I126
I202 DDR_50S DDR DDR1_DM<3..0> 8 13
NAND_50S NAND0 FMI0_DQS_N I66 NAND_50S NAND1 SLOT0_FMI1_AD<3>
I127
DDR1_CK_P SLOT0_FMI1_AD<4>
C I203
I205
DDR_90D
DDR_90D
DDR
DDR DDR1_CK_N
8 13
8 13
I128
I129
NAND_50S
NAND_50S
NAND0
NAND0
FMI0_DQS_P
FMI0_RB0_L
6 12 I79
I80
NAND_50S
NAND_50S
NAND1
NAND1 SLOT0_FMI1_AD<5> C
I206 DDR_50S DDR DDR1_CKE<1..0> 8 13
NAND_50S NAND0 FMI0_RB1_L I81 NAND_50S NAND1 SLOT0_FMI1_AD<6>
I130
I204 DDR_50S DDR DDR1_CSN<2..0> 8 13
NAND_50S NAND0 FMI0_RE_N 6 12 I83 NAND_50S NAND1 SLOT0_FMI1_AD<7>
I131
NAND_50S NAND0 FMI0_RE_P I82 NAND_50S NAND1 SLOT0_FMI1_ALE
I132
NAND_50S NAND0 FMI0_WE_L 6 12 I84 NAND_50S NAND1 SLOT0_FMI1_CE0_L
I133
I210 DDR_50S DDR0 DDR1_DQ<7..0> 8 13
NAND_50S NAND0 FMI0_WP_L I85 NAND_50S NAND1 SLOT0_FMI1_CE1_L
I134
NAND_50S NAND1 FMI1_AD<0> 6 12 I86 NAND_50S NAND1 SLOT0_FMI1_CLE
I135
NAND_50S NAND1 FMI1_AD<1> 6 12 I87 NAND_50S NAND1 SLOT0_FMI1_DQS_P
I136
I212 DDR_50S DDR1 DDR1_DQ<15..8> 8 13
NAND_50S NAND1 FMI1_AD<2> 6 12 I88 NAND_50S NAND1 SLOT0_FMI1_RE_N
I137
NAND_50S NAND1 FMI1_AD<3> 6 12 I89 NAND_50S NAND1 SLOT0_FMI1_WE_L
I138
I139
I214 DDR_50S DDR2 DDR1_DQ<23..16> 8 13
I140
I141
I142
I218 DDR_50S DDR3 DDR1_DQ<31..24> 8 13
NAND_50S NAND1 FMI1_ALE 6 12 44 I94 NAND_50S NAND0 SLOT1_FMI0_AD<4>
I143
NAND_50S NAND1 FMI1_CE0_L 6 12 I95 NAND_50S NAND0 SLOT1_FMI0_AD<5>
I144
NAND_50S NAND1 FMI1_CE1_L 6 12 I96 NAND_50S NAND0 SLOT1_FMI0_AD<6>
I145
I146
I181 DDR_50S DDR DDR2_CA<9..0> 8 14
NAND_50S NAND1 FMI1_CE3_L I98 NAND_50S NAND0 SLOT1_FMI0_ALE
I147
I182 DDR_50S DDR DDR2_DM<3..0> 8 14
NAND_50S NAND1 FMI1_CE4_L I99 NAND_50S NAND0 SLOT1_FMI0_CE0_L
I148
NAND_50S NAND1 FMI1_CE5_L I100 NAND_50S NAND0 SLOT1_FMI0_CE1_L
I149
NAND_50S NAND1 FMI1_CE6_L I101 NAND_50S NAND0 SLOT1_FMI0_CLE
I150
I186 DDR_50S DDR DDR2_CKE<1..0> 8 14
NAND_50S NAND1 FMI1_CE7_L I102 NAND_50S NAND0 SLOT1_FMI0_DQS_P
I151
I184 DDR_50S DDR DDR2_CSN<2..0> 8 14
NAND_50S NAND1 FMI1_CLE 6 12 44 I103 NAND_50S NAND0 SLOT1_FMI0_RE_N
I152
NAND_50S NAND1 FMI1_DQS_N I104 NAND_50S NAND0 SLOT1_FMI0_WE_L
I153
DDR_50S DDR DDR2_ZQ 14 FMI1_DQS_P NAND_50S NAND1 SLOT1_FMI1_AD<0>
B I188
I190 DDR_50S DDR0 DDR2_DQ<7..0> 8 14

I154
I155
NAND_50S
NAND_50S
NAND1
NAND1 FMI1_RB0_L
6 12 I105
I106 NAND_50S NAND1 SLOT1_FMI1_AD<1> B

NAND_50S NAND1 FMI1_RB1_L I107 NAND_50S NAND1 SLOT1_FMI1_AD<2>
I157
NAND_50S NAND1 FMI1_RE_N 6 12 I108 NAND_50S NAND1 SLOT1_FMI1_AD<3>
I156
I192 DDR_50S DDR1 DDR2_DQ<15..8> 8 14
NAND_50S NAND1 FMI1_RE_P I109 NAND_50S NAND1 SLOT1_FMI1_AD<4>
I158
NAND_50S NAND1 FMI1_WE_L 6 12 44 I110 NAND_50S NAND1 SLOT1_FMI1_AD<5>
I160
NAND_50S NAND1 FMI1_WP_L 44 I111 NAND_50S NAND1 SLOT1_FMI1_AD<6>
I159
I194 DDR_50S DDR2 DDR2_DQ<23..16> 8 14
NAND_50S NAND1 FMI1_CLE 6 12 44 I112 NAND_50S NAND1 SLOT1_FMI1_AD<7>
I161
NAND_50S NAND1 FMI1_ALE 6 12 44 I113 NAND_50S NAND1 SLOT1_FMI1_ALE
I162
NAND_50S NAND1 FMI1_RE_L I114 NAND_50S NAND1 SLOT1_FMI1_CE0_L
I163
I198 DDR_50S DDR3 DDR2_DQ<31..24> 8 14
NAND_50S NAND1 FMI1_WE_L 6 12 44 I116 NAND_50S NAND1 SLOT1_FMI1_CE1_L
I164
NAND_50S NAND1 FMI1_WP_L 44 I115 NAND_50S NAND1 SLOT1_FMI1_CLE
I165
I200 DDR_50S DDR3 DDR2_DQS_N<3> 8 14 I117 NAND_50S NAND1 SLOT1_FMI1_DQS_P
I118 NAND_50S NAND1 SLOT1_FMI1_RE_N
I38 DDR_50S DDR DDR3_CA<9..0> 8 14 I119 NAND_50S NAND1 SLOT1_FMI1_WE_L
I39 DDR_50S DDR DDR3_DM<3..0> 8 14
I43 DDR_50S DDR DDR3_CKE<1..0> 8 14
I47 DDR_50S DDR DDR3_CSN<2..0> 8 14

DDR VREF

I37 DDR_50S DDR0 DDR3_DQ<7..0> 8 14

VREF * * 5:1_SPACING

NET_TYPE
I172 DDR_50S DDR1 DDR3_DQ<15..8> 8 14
DDR3_DQS_P<1>
A I173
I174
DDR_50S
DDR_50S
DDR1
DDR1 DDR3_DQS_N<1>
8 14
8 14
I166 PWR PPVREF_DDR0_CA 13 45
I175 DDR_50S DDR2 DDR3_DQ<23..16> 8 14
PWR PPVREF_DDR0_DQ PAGE TITLE

I167
I169 PWR PPVREF_DDR1_CA

13 45
13 45
CONSTRAINTS: DDR/FMI
PWR PPVREF_DDR1_DQ 13 45
DRAWING NUMBER SIZE
I168
I178 DDR_50S DDR3 DDR3_DQ<31..24> 8 14
I179 DDR_50S DDR3 DDR3_DQS_P<3> 8 14 REVISION
R
I180 DDR_50S DDR3 DDR3_DQS_N<3> 8 14 10.0.0
153 OF 157
8 7 6 5 4 3 2 1
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8 7 6 5 4 3 2 1
PWR NET_TYPE
TABLE_PHYSICAL_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET ELECTRICAL_CONSTRAINT_SET PHYSICAL SPACING
TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
PWR * PWR_PMU PWR * * 3:1_SPACING

I255 3.0V PP_PWR PWR MT_3V3_INT 18 45
I256 1.8V PP_PWR PWR Z1_1V8_OUT 18

NET_TYPE
I257 1.8V PP_PWR PWR Z2_VDDCORE 18
VOLTAGE PHYSICAL SPACING
1.8V PP_PWR PWR Z2_VDDANA 18
I258
ACC_PT_DK_CON_PP3V3 1.8V PP_PWR PWR Z2_3V3_1V8_IN 18

I221 3.3V PP_PWR PWR 27 29 I259
I1 PP_PWR PWR BUCK0_FB 36
I2 PP_PWR PWR BUCK0_LXL 36
BUCK0_LXM
D
I3
I4
PP_PWR
PP_PWR
PWR
PWR BUCK2_FB
36
36
D
I6 PP_PWR PWR BUCK2_LXM 36
I7 PP_PWR PWR BUCK2_LXR 36
I14 PP_PWR PWR BUCK5_LX 36
I16 0.4V PP_PWR PWR PP0V4_MIPI0D 7
I17 0.4V PP_PWR PWR PP0V4_MIPI1D 7
I18 1.1V PP_PWR PWR PP1V1 35 36
I21 1.1V PP_PWR PWR PP1V1_MIPID_PLL_F 4
I23 1.1V PP_PWR PWR PP1V1_PL0_F 4
I26 1.1V PP_PWR PWR PP1V1_PL4_F 4 GND


I27 1.1V PP_PWR PWR PP1V1_PLL_USB_F 4
I29 1.25V PP_PWR PWR PP1V25_CPU 35 36 GND_PH * GND

C I30
I31
1.2V
1.2V
PP_PWR
PP_PWR
PWR
PWR
PP1V2_S2R
PP1V2_SOC
35 36
35 36
C
NET_TYPE
I32 1.7V PP_PWR PWR PP1V7_VA_VCP 35 36 40
I33 1.8V PP_PWR PWR PP1V8_ALWAYS 35 36
I34 1.8V PP_PWR PWR PP1V8_DP_AVDD_AUX 7 I199 GND GND GND

1.8V PP_PWR PWR PP1V8_EDP_AVDD_AUX 7 GND GND VOLTAGE=0V GND_AUDIO_CODEC 19 21
I35 I200
1.8V PP_PWR PWR PP1V8_GRAPE 35 36 GND GND VOLTAGE=0V GND_AUDIO_HP_AMP 19 21 22
I36 I201
1.8V PP_PWR PWR PP1V8_S2R 35 36 GND GND VOLTAGE=0V GND_AUDIO_PT_DK 21 27
I37 I202
1.8V PP_PWR PWR PP1V8_SENSOR_FLT 24 26 GND GND VOLTAGE=0V GND_SPKR_AMP1 20
I38 I203
1.8V PP_PWR PWR PP1V8_VDDA18_TS 5 GND GND VOLTAGE=0V GND_SPKR_AMP2 20
I39 I207
2.85V PP_PWR PWR PP2V85_CAM 35 36 GND GND VOLTAGE=0V GND_PMU
I40 I206
I41 2.85V PP_PWR PWR PP2V85_CAM_FLT 24 26 I205 GND GND AGND

I42 3.0V PP_PWR PWR PP3V0_GRAPE 35 36 I217 GND GND AGND_U3000 17
I43 3.0V PP_PWR PWR PP3V0_IO 35 36
I44 3.0V PP_PWR PWR PP3V0_OPTICAL 35 36
I45 3.0V PP_PWR PWR PP3V0_S2R_HALL 35 36
I46 3.0V PP_PWR PWR PP3V0_S2R_HALL_FLT 24 26
I47 3.0V PP_PWR PWR PP3V0_SENSOR_FLT 10 24 26
I49 3.0V PP_PWR PWR PP3V0_VIDEO 35 36
I51 3.0V PP_PWR PWR PP3V0_VIDEO_BUF 35 36
I50 3.2V PP_PWR PWR PP3V2_LDO5 35 36

RST
I53 3.2V PP_PWR PWR PP3V2_S2R_USBMUX 35 36 TABLE_SPACING_ASSIGNMENT_HEAD
I52 3.3V PP_PWR PWR PP3V3_ACC 35 36

I54 3.3V PP_PWR PWR PP3V3_LCDVDD_SW_F 16

RST * *
4:1_SPACING
I55 3.3V PP_PWR PWR PP3V3_OUT 35 36
PP3V3_S0_LCD_FERR
B I56
I57
3.3V
5.25V
PP_PWR
PP_PWR
PWR
PWR PP5V25_VLCM2
16
35 37
ELECTRICAL_CONSTRAINT_SET PHYSICAL
NET_TYPE
SPACING
B
I58 6.0V PP_PWR PWR PP6V0_LCM_HI 37
I59 6.0V PP_PWR PWR PP6V0_LCM_VBOOST 37

RST BB_TRST_L
I165
I60 4.2V PWR500 PWR PPBATT_VCC 35 36 39
RST DBG_RST
I166
I61 1.8V PP_PWR PWR PPIO_NAND_H4 6 9
RST DEBUG_RST_L
I167
I62 20.4V PP_PWR PWR PPLED_BACK_REG_A 16
RST GSM_TXBURST_IND 5 15 30
I171
I63 20.4V PP_PWR PWR PPLED_BACK_REG_B 16
RST JTAG_AP_TRST_L 4 10 42
I169
I64 20.4V PP_PWR PWR PPLED_OUT_A 35 37
RST RST_AP_1V8_L 4
I170
I65 20.4V PP_PWR PWR PPLED_OUT_B 35 37
RST RST_AP_L 4 27 30 37
I168
I66 6.0V PP_PWR PWR PPVBUS_PROT 36
RST RST_BB_L 5 30
I172
I67 6.0V PP_PWR PWR PPVBUS_USB 4 36
RST RST_BB_PMU_L 30 37
I174
I68 6.0V PP_PWR PWR PPVBUS_USB_DCIN 35 36
RST RST_BT_L 15 37
I173
I69 5.0V PP_PWR PWR PPVBUS_USB_PT_DK_CON 27 29
RST RST_DET_L 5 30
I175
I176 GRAPE RST_GRAPE_L 6 17
I70 1.8V PP_PWR PWR PPVCCQ_NAND 12

RST RST_L63_L 19 37
I177
I71 4.7V PP_PWR PWR PPVCC_MAIN 35 36 37
RST RST_PMU_IN 4 37
I178
I72 0.6V PP_PWR PWR PPVREF_DDR0_CA 13 44
RST RST_WLAN_L 15 37
I179
I73 0.6V PP_PWR PWR PPVREF_DDR0_DQ 13 44
RST SIMCRD_RST
I181
I74 0.6V PP_PWR PWR PPVREF_DDR0_DQ_H4 8
RST TP_WLAN_TRST_L
I180
I76 0.6V PP_PWR PWR PPVREF_DDR1_CA 13 44
RST UD881_RST
I182
I75 0.6V PP_PWR PWR PPVREF_DDR1_DQ 13 44
RST UD882_RST
I183
I78 0.6V PP_PWR PWR PPVREF_DDR2_CA 14
I79 0.6V PP_PWR PWR PPVREF_DDR2_DQ 14
A I80
I81
0.6V
0.6V
PP_PWR
PP_PWR
PWR
PWR
PPVREF_DDR3_CA
PPVREF_DDR3_DQ
14
14
PAGE TITLE
0.6V PP_PWR PWR PPVREF_DDR3_DQ_H4
I82
I219 4.6V PP_PWR PWR BATT_POS_RC

8
36
CONSTRAINTS: POWER / GND
I84 18V PP_PWR PWR PP18V_GRAPE 17
DRAWING NUMBER SIZE
I85 18V PP_PWR PWR PP18V_R_GRAPE 17

I220 PP_PWR PWR DAC_AP_VREF 7
R
REVISION
I223 3.3V PP_PWR PWR PPVDDI_NAND_U1400 12

10.0.0
I224 PP_PWR PWR VR_BOOST_SW 17
I225 PP_PWR PWR VR_BOOST_L 17

I226 3.0V PP_PWR PWR MT_3V3_INT 18 45
154 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SNS

SNS_50S * 50_OHM_SE

SNS * * 3:1_SPACING
D NET_PHYSICAL_TYPE AREA_TYPE
PHYSICAL_RULE_SET
D
SNS_90D * 90_OHM_DIFF
I189
NC_DDR0_CKE<1> NO_TEST=TRUE 8 I227
NC_BON_L1 NO_TEST=TRUE 18
I117
NC_FMI0_CE2_L NO_TEST=TRUE 6
I48
NC_HSIC0_DATA2 NO_TEST=TRUE 4 42 I191
I119
I49 NC_HSIC0_STB2 NO_TEST=TRUE 4 42 I190
I118
I50 NC_HSIC1_DATA2 NO_TEST=TRUE 4 42 I193
NC_EAROUT_AP NO_TEST=TRUE 19
I121
I51 NC_HSIC1_STB2 NO_TEST=TRUE 4 42 I231
NC_EAROUT_AN NO_TEST=TRUE 19
I120
I122
I52 NC_JTAG_AP_TRTCK NO_TEST=TRUE 4
I196
NC_DDR0_CSN<1> NO_TEST=TRUE 8
I124
I195
I123
NC_FMI1_CE3_L NO_TEST=TRUE 6 I232
NC_LINE_IN1_CODEC NO_TEST=TRUE 19
I54 NC_USB_D1_P NO_TEST=TRUE 4 42 I198
I126
NC_LINE_IN1_REF_CODEC NO_TEST=TRUE 19
I55 NC_USB_D1_N NO_TEST=TRUE 4 42 I200
I128
NC_LINE_IN2_CODEC NO_TEST=TRUE 19
I56 NC_USB11_D1_P NO_TEST=TRUE 4 42
I127
NC_LINE_IN2_REF_CODEC NO_TEST=TRUE 19
I57 NC_USB11_D1_N NO_TEST=TRUE 4 42
I130
NC_MIC1_BIAS_CODEC NO_TEST=TRUE 19
I58 NC_USB_ANALOGTEST0 NO_TEST=TRUE 4 I237

NC_MIC1P_CODEC NO_TEST=TRUE 19
I59
NC_USB_ANALOGTEST1 NO_TEST=TRUE 4 I131
NC_MIC1N_CODEC NO_TEST=TRUE 19
I134
NC_MIC1_FILT_CODEC NO_TEST=TRUE 19
I60
NC_USB_ID0 NO_TEST=TRUE 4 I205
NC_PMU_VBUCK0_SW0_G NO_TEST=TRUE 36
I133
I61 NC_USB_ID1 NO_TEST=TRUE 4 I204
NC_PMU_VBUCK0_SW0_S NO_TEST=TRUE 36
I132
I226
NC_VBUS_A_OV_L NO_TEST=TRUE 36
I62 NC_USB_BRICKID1 NO_TEST=TRUE 4
C NC_I2S1_MCK NO_TEST=TRUE 5
I135
NC_FMI2_AD<0>
NC_FMI2_AD<1>
NO_TEST=TRUE
NO_TEST=TRUE
6
6
I207
I209
NC_BOARD_TEMP7
NC_BOARD_TEMP8
NO_TEST=TRUE
NO_TEST=TRUE
37
37
I240
NC_D5703_6
NC_D5700_6
NO_TEST=TRUE
NO_TEST=TRUE
C
I63 I137 I241
I64 NC_I2S1_BCLK NO_TEST=TRUE 5 I136

NC_FMI2_AD<2> NO_TEST=TRUE 6 I242
NC_D5701_6 NO_TEST=TRUE
I65 NC_I2S1_LRCK NO_TEST=TRUE 5 I139
NC_PMU_GPIO12 NO_TEST=TRUE 37 I243
NC_D5702_6 NO_TEST=TRUE
I66 NC_I2S1_DIN NO_TEST=TRUE 5 I138
NC_PMU_GPIO13 NO_TEST=TRUE 37
I244
NC_LCM2_EN NO_TEST=TRUE 37
I67 NC_I2S1_DOUT NO_TEST=TRUE 5 I140
NC_FMI2_AD<5> NO_TEST=TRUE 6
I245
NC_VLCM1 NO_TEST=TRUE 37
I68
NC_I2S2_MCK NO_TEST=TRUE 5 I143
I69 NC_I2S3_MCK NO_TEST=TRUE 5 I142

I70 NC_AP_GPIO216 NO_TEST=TRUE 5 I213

I71
NC_SPI_FLASH_CS_L NO_TEST=TRUE 5 I144
NC_FMI2_ALE NO_TEST=TRUE 6
I146
NC_FMI2_CLE NO_TEST=TRUE 6
I145
NC_FMI2_WE_L NO_TEST=TRUE 6 I216
NC_PMU_AMUX_A0 NO_TEST=TRUE 37
I72 NC_SWI_AP NO_TEST=TRUE 5
I148
NC_FMI2_RE_L NO_TEST=TRUE 6 I218
I147
NC_FMI2_DQS NO_TEST=TRUE 6 I217
I73 NC_SDIO0_WL_CLK NO_TEST=TRUE 5
I220
I76 NC_SDIO0_WL_CMD NO_TEST=TRUE 5
I152
NC_PMU_AMUX_AY NO_TEST=TRUE 37
I75 NC_SDIO0_WL_DATA<0> NO_TEST=TRUE 5
I151
NC_PMU_AMUX_B0 NO_TEST=TRUE 37
I150
I153
I79
NC_SDIO0_WL_DATA<3> NO_TEST=TRUE 5
I155
I81
NC_SPI3_MISO NO_TEST=TRUE 5 I154
NC_PMU_AMUX_BY NO_TEST=TRUE 37
I83 NC_SPI3_MOSI NO_TEST=TRUE 5 I157

I82 NC_SPI3_SCLK NO_TEST=TRUE 5 I156

I85 NC_SPI3_CS_L NO_TEST=TRUE 5
I161
I160
NC_AP_GPIO3 NO_TEST=TRUE 5
B I90
I92 NC_AP_GPIO7 NO_TEST=TRUE 5

I159
I162
NC_FMI3_AD<2>
NC_FMI3_AD<3>
NO_TEST=TRUE
NO_TEST=TRUE
6
6
B
I164
I163
I93
I166
I95 NC_BOARD_ID_3 NO_TEST=TRUE 5
I165
I97
I170
NC_FMI3_ALE NO_TEST=TRUE 6
I169
NC_FMI3_CLE NO_TEST=TRUE 6
I99 NC_AP_GPIO3V1 NO_TEST=TRUE 5
I168
NC_FMI3_WE_L NO_TEST=TRUE 6
I101
I171
NC_FMI3_RE_L NO_TEST=TRUE 6
I173
NC_FMI3_DQS NO_TEST=TRUE 6
I102
NC_UART2_RXD NO_TEST=TRUE 5
I104
NC_UART2_TXD NO_TEST=TRUE 5 I174
NC_MIPI_VSYNC_H4 NO_TEST=TRUE 7
NC_UART4_CTS_L NO_TEST=TRUE 5
I107 NC_MIPI0C_AP_DATA_P<2>
I176 NO_TEST=TRUE 7 43
I106
NC_UART4_RTS_L NO_TEST=TRUE 5
I179
NC_MIPI0C_AP_DATA_N<2> NO_TEST=TRUE 7 43
I105
NC_UART4_RXD NO_TEST=TRUE 5
NC_UART4_TXD NO_TEST=TRUE 5
I108 NC_MIPI0C_AP_DATA_P<3>
I177 NO_TEST=TRUE 7 43
I110
NC_UART6_CTSN NO_TEST=TRUE 5
I180
I109
NC_UART6_RTSN NO_TEST=TRUE 5
I181
NC_MIPI1C_AP_DATA_P<1> NO_TEST=TRUE 7 43
I184
I183
NC_ISP_AP_1_FLASH NO_TEST=TRUE 7
I185
NC_ISP_AP_1_PRE_FLASH NO_TEST=TRUE 7
PAGE TITLE
CONSTRAINTS: DEBUG
DRAWING NUMBER SIZE

REVISION
R
10.0.0
155 OF 157
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D D
C C
B B
PAGE TITLE
FUNC TEST POINTS

DRAWING NUMBER SIZE

REVISION
R
10.0.0
156 OF 157
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
C C
B B
PAGE TITLE
FUNC TEST POINTS

DRAWING NUMBER SIZE

REVISION
R
10.0.0
157 OF 157
8 7 6 5 4 3 2 1
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IPAD 3 J2-MLB 051-8773 r1000

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8 7 6 5 4 3 2 1

J2 MLB - DVT OK2FAB

8 10 AP: DDR MIKE N/A 39 90 DEBUG AND MISC ALEX 10/04/2010

15 21 MLB ALIASES/CONNECTIONS ALEX 09/30/2010 46 155 CONSTRAINTS: DEBUG MIKE 01/21/2011

20 37 AUDIO: SPEAKER AMP KAVITHA 02/03/2011

A 31 61 WLAN BB & POWER X26_WIFI_MIKE_BT 09/01/2011 SYNC_MASTER=MIKE SYNC_DATE=NA A

Apple Inc. 051-8773 D

GYRO ACCELEROMETER ALS BLOCK DIAGRAM: SYSTEM

SENSOR PANEL SENSOR PANEL VGA FLEX PPN1.0 PPN1.0 R

NOTICE OF PROPRIETARY PROPERTY: BRANCH

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

Page Notes 051-8773 1 SCH,MLB,J2 SCH1 CRITICAL ?

Power aliases required by this page: 820-2996 1 PCBF,MLB,J2 PCB1 CRITICAL ?

085-3058 1 DEV BOM,MLB,J2 DEV1 ?

BOM options provided by this page: SOC

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

DEVELOPMENT_JTAG_TAP 343S0561 1 IC,PMU,AMELIA,D1974AB U8100 CRITICAL ?

BASIC COMMON,ALTERNATE 333S0579 2 SDRAM,LPDDR2,512MB,SAMSUNG 46NM U1600,U1700 CRITICAL ?

AUDIO SPEAKER,INTERNAL_MIC TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

333S0580 333S0579 U1600,U1700 LPDDR2,HYNIX 44NM

C 333S0581 333S0579 U1600,U1700 LPDDR2,ELPIDA 45NM

BARCODE LABEL/EEEE CODES

825-7691 1 EEEE FOR 639-2352 (J1 16G) EEEE_DNKT CRITICAL EEEE_J1_16G

16GB FLASH CONFIGURATIONS

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

335S0781 1 HYNIX 26NM PPN1.0 16GB U1400 CRITICAL 16GB_PROD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

335S0804 335S0781 16GB_PROD U1400 TOSHIBA 24NM PPN1.0

825-7691 1 EEEE FOR 639-1870 (J2 128G) EEEE_DKQK CRITICAL EEEE_J2_128G

32GB FLASH CONFIGURATIONS

825-7691 1 EEEE FOR 639-2844 (J2A 16G) EEEE_DRJQ CRITICAL EEEE_J2A_16G

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

B PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

806-2105 1 FENCE,NAND,TOP,MLB,J2 PD_FENCE_NAND CRITICAL

64GB FLASH CONFIGURATIONS

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

335S0782 2 HYNIX 26NM PPN1.0 32GB U1400,U1410 CRITICAL 64GB_PROD

806-1865 1 FENCE,2,BTM,MLB,J2 PD_FENCE_BTM2 CRITICAL TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

335S0805 335S0782 64GB_PROD U1400,U1410 TOSHIBA 24NM PPN1.0

128GB FLASH CONFIGURATIONS

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

335S0814 2 HYNIX 26NM PPN1.0 64GB U1400,U1410 CRITICAL 128GB_PROD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

335S0806 335S0814 128GB_PROD U1400,U1410 TOSHIBA 24NM PPN1.0

Apple Inc. 051-8773 D

Apple Inc. 051-8773 D

39 5 FORCE_DFU AP20 GPIO26

Apple Inc. 051-8773 D

Apple Inc. 051-8773 D

CHECK CONNECTION FOR VSSA18_TS

MAX_NECK_LENGTH=3MM 201 240-OHM-0.2A-0.8-OHM MIN_LINE_WIDTH=0.2MM

43 25 OUT MIPI0C_AP_DATA_N<1> B32 MIPI0C_DNDATA1 ISP1_PRE_FLASH AE17 NC_ISP_AP_1_PRE_FLASH 46

ISP1_SCL AP24 ISP_AP_1_SCL OUT 25 42 DP_PAD_TX0P A28 DP_AP_TX_P<0> OUT 28 43

46 43 NC_MIPI0C_AP_DATA_N<2> B30 MIPI0C_DNDATA2 AP_DP_R_BIAS E23 DP_PAD_R_BIAS

46 43 NC_MIPI0C_AP_DATA_P<3> A31 MIPI0C_DPDATA3 SENSOR0_RST AK24

MIPI1C_DPDATA1 D34 NC_MIPI1C_AP_DATA_P<1> 43 46

MIPI1C_DNDATA1 C34 NC_MIPI1C_AP_DATA_N<1> 43 46 EDP_HPD AJ15 EDP_AP_HPD IN 16 43

MIPI1C_DPCLK F35 MIPI1C_AP_CLK_P OUT 25 43 EDP_PAD_AUXP A24 EDP_AP_AUX_P OUT 16 43

NOTE: 0.6V ANALOG REF EDP_PAD_TX0N D21 EDP_AP_TX_N<0> OUT 16 43

AP_EDP_R_BIAS E20 EDP_PAD_R_BIAS

EDP_PAD_TX3P A20 EDP_AP_TX_P<3> OUT 16 43

EDP_PAD_TX3N A19 EDP_AP_TX_N<3> OUT 16 43