The ARM Architecture

Agenda
ƒ Introduction to ARM Ltd
ARM Architecture/Programmers Model
Data Path and Pipelines
AMBA
Development Tools

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ARM Ltd

ƒ Founded in November 1990

ƒ Spun out of Acorn Computers

ƒ Designs the ARM range of RISC processor cores

ƒ Licenses ARM core designs to semiconductor
partners who fabricate and sell to their customers.
ƒ ARM does not fabricate silicon itself

ƒ Also develop technologies to assist with the design-

in of the ARM architecture
ƒ Software tools, boards, debug hardware,
application software, bus architectures,
peripherals etc

ARM Partnership Model

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ARM Powered Products

Agenda
Introduction to ARM Ltd
ƒ ARM Architecture/Programmers Model
Data Path and Pipelines
AMBA
Development Tools

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Architecture Revisions

ARMv7 (Future)
version

ARM1156T2F-S™
ARM1136JF-S™

ARMv6

ARM1176JZF-S™
ARM102xE XScaleTM ARM1026EJ-S™

ARMv5

ARM9x6E ARM926EJ-S™
® SC200™
ARM7TDMI-S™ StrongARM ARM92xT

V4

SC100™ ARM720T™

1994 1996 1998 2000 2002 2004 2006

time
XScale is a trademark of Intel Corporation

Data Sizes and Instruction Sets

ƒ The ARM is a 32-bit architecture.

ƒ When used in relation to the ARM:

ƒ Byte means 8 bits
ƒ Halfword means 16 bits (two bytes)
ƒ Word means 32 bits (four bytes)

ƒ Most ARM’s implement two instruction sets

ƒ 32-bit ARM Instruction Set
ƒ 16-bit Thumb Instruction Set

ƒ Jazelle cores can also execute Java bytecode

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Processor Modes
ƒ The ARM has seven basic operating modes:

ƒ User : unprivileged mode under which most tasks run

ƒ FIQ : entered when a high priority (fast) interrupt is raised

ƒ IRQ : entered when a low priority (normal) interrupt is raised

ƒ Supervisor : entered on reset and when a Software Interrupt

instruction is executed
ƒ Abort : used to handle memory access violations

ƒ Undef : used to handle undefined instructions

ƒ System : privileged mode using the same registers as user mode

The ARM Register Set

Current Visible Registers

r0
Abort
Undef
SVC
IRQ
FIQ
User Mode
Mode
Mode
Mode
Mode r1
r2
r3 Banked out Registers
r4
r5
r6 User FIQ IRQ SVC Undef Abort
r7
r8 r8 r8
r9 r9 r9
r10 r10 r10
r11 r11 r11
r12 r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr spsr

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Exception Handling

ƒ When an exception occurs, the ARM:

ƒ Copies CPSR into SPSR_<mode>
ƒ Sets appropriate CPSR bits
ƒ Change to ARM state 0x1C FIQ
0x18 IRQ
ƒ Change to exception mode 0x14 (Reserved)
ƒ Disable interrupts (if appropriate) 0x10 Data Abort
ƒ Stores the return address in LR_<mode> 0x0C Prefetch Abort
ƒ Sets PC to vector address 0x08 Software Interrupt
0x04 Undefined Instruction
ƒ To return, exception handler needs to:0x00 Reset
ƒ Restore CPSR from SPSR_<mode> Vector Table
ƒ Restore PC from LR_<mode> Vector table can be at
0xFFFF0000 on ARM720T
This can only be done in ARM state. and on ARM9/10 family devices

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Conditional Execution and Flags

ƒ ARM instructions can be made to execute conditionally by postfixing them with the
appropriate condition code field.
ƒ This improves code density and performance by reducing the number of
forward branch instructions.
CMP r3,#0 CMP r3,#0
BEQ skip ADDNE r0,r1,r2
ADD r0,r1,r2
skip

ƒ By default, data processing instructions do not affect the condition code flags but
the flags can be optionally set by using “S”. CMP does not need “S”.
loop
…
SUBS r1,r1,#1 decrement r1 and set flags
BNE loop if Z flag clear then branch

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Branch instructions
ƒ Branch : B{<cond>} label
ƒ Branch with Link : BL{<cond>} subroutine_label

31 28 27 25 24 23 0

Cond 1 0 1 L Offset

Link bit 0 = Branch

1 = Branch with link
Condition field

ƒ The processor core shifts the offset field left by 2 positions, sign-extends it
and adds it to the PC
ƒ ± 32 Mbyte range
ƒ How to perform longer branches?

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Data processing Instructions

ƒ Consist of :
ƒ Arithmetic: ADD ADC SUB SBC RSB RSC
ƒ Logical: AND ORR EOR BIC
ƒ Comparisons: CMP CMN TST TEQ
ƒ Data movement: MOV MVN

ƒ These instructions only work on registers, NOT memory.

ƒ Syntax:

<Operation>{<cond>}{S} Rd, Rn, Operand2

ƒ Comparisons set flags only - they do not specify Rd

ƒ Data movement does not specify Rn

ƒ Second operand is sent to the ALU via barrel shifter.

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Using a Barrel Shifter:The 2nd Operand
Register, optionally with shift operation
Operand Operand ƒ Shift value can be either be:
1 2 ƒ 5 bit unsigned integer
ƒ Specified in bottom byte of
another register.
Barrel
Shifter
ƒ Used for multiplication by constant

Immediate value
ƒ 8 bit number, with a range of 0-
255.
ALU
ƒ Rotated right through even
number of positions
ƒ Allows increased range of 32-bit
Result constants to be loaded directly into
registers

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Loading 32 bit constants

ƒ To allow larger constants to be loaded, the assembler offers a pseudo-
instruction:
ƒ LDR rd, =const
ƒ This will either:
ƒ Produce a MOV or MVN instruction to generate the value (if possible).
or
ƒ Generate a LDR instruction with a PC-relative address to read the
constant from a literal pool (Constant data area embedded in the
code).
ƒ For example
ƒ LDR r0,=0xFF => MOV r0,#0xFF
ƒ LDR r0,=0x55555555 => LDR r0,[PC,#Imm12]
…
…
DCD 0x55555555
ƒ This is the recommended way of loading constants into a register

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Single register data transfer
LDR STR Word
LDRB STRB Byte
LDRH STRH Halfword
LDRSB Signed byte load
LDRSH Signed halfword load

ƒ Memory system must support all access sizes

ƒ Syntax:
ƒ LDR{<cond>}{<size>} Rd, <address>
ƒ STR{<cond>}{<size>} Rd, <address>

e.g. LDREQB
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Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
ƒ Data Path and Pipelines
AMBA
Development Tools

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The ARM7TDM Core
ABE A[31:0] Address
Incrementer

Address Register Incrementer

P
C BIGEND
MCLK
nWAIT
Register Bank PC Update
nRW
Instruction MAS[1:0]
A
Decode Stage Decoder
L A B ISYNC
Instruction nIRQ
U Decompression nFIQ
Multiplier nRESET
B B and ABORT
B nTRANS
u u Read Data
nMREQ
u s Barrel s Register SEQ
Shifter Control LOCK
s nM[4:0]
Logic
Write Data nOPC
Register nCPI
32 Bit ALU CPA
CPB

DBE D[31:0]

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Pipeline changes for ARM9TDMI

ARM7TDMI
ARM decode
Instruction Thumb→ARM Reg Reg
Shift ALU
Fetch decompress Read Write
Reg Select

FETCH DECODE EXECUTE

ARM9TDMI
ARM or Thumb
Instruction Inst Decode Memory Reg
Shift + ALU Write
Fetch Reg Reg Access
Decode Read
FETCH DECODE EXECUTE MEMORY WRITE

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ARM10 vs. ARM11 Pipelines
ARM10
Branch ARM or Memory
Prediction Shift + ALU
Thumb Reg Read Access Reg
Instruction Instruction Write
Decode Multiply
Fetch Multiply
Add
FETCH ISSUE DECODE EXECUTE MEMORY WRITE

ARM11

Shift ALU Saturate

Fetch Fetch MAC MAC MAC Write

Decode Issue
1 2 1 2 3 back

Data Data
Address Cache Cache
1 2

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Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
Data Path and Pipelines
ƒ AMBA
Development Tools

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AMBA
Arbiter Reset

ARM
TIC
Remap/
External Bus Interface Timer
Pause
ROM External

Bridge
Bus
Interface
External
RAM On-chip Interrupt
Decoder RAM Controller

AHB or ASB APB

System Bus Peripheral Bus

ƒAMBA ƒACT
ƒ Advanced Microcontroller Bus ƒ AMBA Compliance Testbench
Architecture
ƒADK ƒPrimeCell
ƒ Complete AMBA Design Kit ƒ ARM’s AMBA compliant
peripherals
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AHB basic signal timing

Address Phase Data Phase A Data Phase B

A Address Phase B

HCLK

HADDR A B C

HWRITE A B C

HWDATA A B

HRDATA A B

HRESP OKAY A OKAY B

HREADY

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Agenda
Introduction to ARM Ltd
ARM Architecture/Programmers Model
Data Path and Pipelines
AMBA
ƒ Development Tools

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ARM Debug Architecture

Ethernet

Debugger (+ optional
trace tools)

JTAG port Trace Port

ƒ EmbeddedICE Logic
ƒ Provides breakpoints and processor/system
access
TAP
ƒ JTAG interface (ICE) controller
ƒ Converts debugger commands to JTAG ETM
signals
ƒ Embedded trace Macrocell (ETM) EmbeddedICE
Logic
ƒ Compresses real-time instruction and data
access trace
ƒ Contains ICE features (trigger & filter logic)
ƒ Trace port analyzer (TPA) ARM
core
ƒ Captures trace in a deep buffer

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