1
Real-Time implementation of a SPLL for FACTS.
Francisco D. Freijedo, Jesús Doval-Gandoy, Member, IEEE, Óscar López, Member, IEEE, David Piñeiro,
Carlos M. Peñalver, Member, IEEE, Andrés A. Nogueiras, Member, IEEE
Electronics Technology Department
University of Vigo
ETSI Industriales, Campus Lagoas
36200 Vigo, SPAIN
Email: fdfrei@uvigo.es; jdoval@uvigo.es; olopez@uvigo.es
Abstract— This paper presents a real-time implementation of a
software phase-locked loop (SPLL) for using in FACTS systems.
The FACTS phase locked loops (PLLs) main characteristics and
the disturbances impact over their performance are reviewed
making special emphasis on the weak points of the usual three-
phase trans-vector-type PLLs. These weak points are mainly slow
response under low amplitude ac inputs and three-phase unbal-
ances. Recently some alternatives, specially the adaptive SPLL,
solved these typical trans-vector issues. However, the discrete
implementation of adaptive SPLL in a programmable device like
a microcontroller, a DSP or a FPGA seems very complex. In
this work a double-loop SPLL has been developed with the aim
of reducting the complexity of a discrete implementation and
without losing performance with respect to the adaptive SPLL.
The proposed double-loop SPLL has been implemented in real-
time using Matlab/Simulink and the fast prototyping platform
dSpace DS1103; its high performance and feasibility are shown
in the simulation and real-time implementation sections.
I. I NTRODUCTION
A. Background
Phase Locked Loops (PLLs) are widely used in the control
of FACTS. Their principal use is to track the positive sequence
phase of the grid three-phase ac signal. Furthermore PLLs
should provide frequency and amplitude measurements. PLL
outputs are used to calculate the switching times of devices in
the control loop of FACTS; therefore they have an important
role in system dynamics and performance [1]. Indeed, the
speed of response and accurate of PLL becomes especially
critical when a transient happens in the distribution system.
Lately, the FACTS requirements on power quality, perfor-
mance and fault recovery have been increased, and the control
systems developed has became more and more sophisticated.
However the role of PLLs in these control systems is not still
investigated enough [2]. In this work a single-phase software
PLL is presented as an alternative to the most widely used
three-phase trans-vector-type PLL.
B. Role of PLL in FACTS control
The effect of PLL in different control schemes has been an-
alyzed in different works. In this subsection a brief discussion
about them is presented.
In [3] the authors have studied the effect of the PLL delay
on the performance of static synchronous series compensator
(SSSC) and static synchronous compensator (STATCOM).
1-4244-0136-4/06/$20.00 '2006 IEEE 2390
Va Vd
Vb Clarke & Park
Vc Transformations Vq w
A
,
q
PI 1/s
A A
A q
Fig. 1. Trans-vector-type three-phase PLL.
They have demonstrated that the PLL delay leads to an uncon-
trolled exchange of real and reactive between the STATCOM
and the transmission line. They have obtained similar results
for SSSC; furthermore, in SSSC, when a disturbance in the
power system occurs, large overshoot and undershoot appears
in the dc capacitor voltage. Therefore, by improving the PLL
speed the performance of FACTS devices are enhanced.
PLL performance is critical in control of dynamic voltage
restorer (DVR) too. Especially, when a DVR is protecting a
phase-shift sensitive load, the PLL speed of response to detect
these phase-shifts becomes crucial [4]. The different control
strategies of DVR use the fault information to calculate the
injected voltage; therefore, the faster the PLL obtains this
information, the faster the DVR response is.
C. Characteristics of PLLs working connected to grid
As it has been shown, PLLs used in FACTS work connected
to three-phase grid; they mainly have to track the phase-angle
of the positive sequence of the fundamental component of
voltage.
The most widely used three-phase PLLs using in FACTS
are based on the trans-vector-type PLL [2]. Trans-vector-type
PLLs use the Park’s and Clarke’s transformations for changing
→
−
the natural reference frame ( V abc ) to the rotating reference
→
− →
−
frame d-q ( V dq ); then the phase-angle of V dq is tracked in
the feedback loop (Fig. 1). Different alternatives to track the
dq-frame rotating phase-angle have been implemented. In [5]
to track the fundamental phase is achieved making zero the
quadrature component using a proportional integrator (PI) or
a lag/lead filter in the feedback loop. However, in [6] and [7]
the used method makes zero the direct component. Actually
both methods are similar; the feedback loop makes constant a
voltage reference in the dq rotating reference frame.

Vphase qerr w ,
Phase Detector
A
PI
A
Loop filter
qo.
A
Fig. 2. One-phase SPLL equivalent scheme of classical PLL.
Three-phase PLLs only need a feedback loop for tracking
the whole phase. Furthermore, they have a good transient
response and internal harmonic cancellation. However, its
behaviour is bad with lower ac voltages and under unbalanced
conditions [2]. Indeed, the main issue of trans-vector-based
PLLs is that they can not track individual phase-angle jumps,
→
− 0
because V dq does not have enough information to deter-
mine them. Recently, some works have improved these issues
evolving the trans-vector-type PLL to a double synchronous
reference frame (DRSF) which employs two feedback loop;
one for the positive sequence and other for the negative
sequence [8].
An alternative to three-phase PLLs is the use of three single-
phase PLLs which track the phase-angle of the input ac signals
independently. Furthermore, single-phase PLL should be more
effective in system like the series voltage restorer (SVR) of
[9] where a independent compensation is made for each phase.
Single-phase PLL classical scheme, widely explained in [10],
has been implemented in hardware since 70s. Classical PLL
can be easy implemented in software (SPLL) replacing the
classical blocks with their equivalent transfer function blocks
(Fig. 2).
The main limitation in hardware classical PLLs is the
utilization of only a single feedback loop, thereby it is not
possible to choice the filter coefficients for improving all the
type of transient responses at the same time. This difficulty
must be solved with an intermediate solution, in which the
PLL has an acceptable performing in all cases but without a
high speed. Other important limitation on classical hardware
PLLs is the internal second harmonic generation which de-
teriorates the output phase a lot. Using high order filter to
avoid this limitations has not been a useful solution due to the
introduced delay.
Recently, with the advance of technology of microcon-
trollers, DSPs, FPGAs, etc, the performance of hardware
classical PLLs can easily improve using SPLLs. A high
improvement in system transient response can be achieved by
controlling in different loops frequency, phase angle and volt-
age magnitude [2]. The addition of control loops to the system
gives the designer more degree of freedom to improve system
responses. Moreover, the software implementation allows to
use adaptive techniques for enhancing the whole performance
of the SPLL. The SPLL developed in this work take these
advantages for its implementation.
II. P OWER QUALITY DISTURBANCES AND PLL S
Voltage and current deviations from their ideal shape are
known as power quality disturbances [11]. The critical distur-
bances in FACTS applications are voltage sags, voltage swells,
phase-angle jumps, frequency changes, harmonics and electric
2
Voltage sag from 1 p.u. to 0.5 p.u. and phase-angle jump of -45 deg.
qo.
1
1/s
0.8
DCO
0.6
0.4
Amplitude (p.u.)
0.2
-0.2
-0.4
-0.6
-0.8
-1
0.02 0.04 0.06 0.08 0.1 0.12 0.14
Time (ms)
Fig. 3. Voltage sag from 1 p.u. to 0.5 p.u. with a +45 deg. phase-angle jump.
noise. The speed of response of PLLs to these disturbances
determines their performance.
Voltage sags are a frequent phenomenon in electrical dis-
tribution. They are characterized by a sudden drop in voltage
amplitude for several cycles. They are mainly due to faults
in the distribution system. Trans-vector-type PLLs have a
poor speed of response to sags, because the gain on the
feedback loop is proportional to the input voltage amplitude;
therefore inserting a gain compensator improves the speed
of response of PLLs during sags. Voltage swells are short
duration overvoltages; like in voltage sags the PLL gain should
be compensated.
Phase-angle jumps are suddenly changes in the phase of
the signal. During three-phase faults, phase-angle jumps occur
mainly due to difference in reactance to resistance ratio
between source and feeder. These phase-angle jumps usually
have values of few degrees. Voltage sags and large phase-
angle jumps can also appear at the same time, due to one-
phase faults in three-phase system [11]. In Fig. 3 is shown an
example of phase voltage sag with a phase-angle jump due to
a unbalanced fault. In 0.26 ms. the voltage amplitude drops
to 0.5 p.u. and then the phase-angle leads 45 deg. After a few
cycles, the voltage sags ends, and then phase-angle delays 45
deg to pre-fault value (dashed). The PLL speed of response
to this type of disturbance is very critical in DVR and SVR
protecting sensible loads.
Slight frequency changes around natural frequency (50 Hz.
or 60 Hz.) can occur; they are due to distribution line unbal-
ances and faults. PLLs should detect these frequency variations
and they should work without getting worse their performance.
Another typical and growing up disturbance is the harmonic
contamination; it is mainly due to switching loads, which gen-
erate harmonic components. These harmonics reach the whole
electrical distribution system, through the common coupling
points, and they have a bad influence over a lot of systems.
Moreover, the electrical distribution system is contaminated
with electrical noise too. PLLs should be immune to harmonics
and noise. In fact, the used PLLs feedback filters, like PI, lag-
lead, etc, are low pass filters, which should attenuate harmonic
2391

Vphase Amplitude Phase
Amplitude
Phase Frequency
loop Vphase normalized loop
Voutput normalized
Fig. 4. Proposed SPLL architecture.
components and noise of the input signal.
Finally, from the point of view of three-phase systems,
unbalances between phases are power disturbances too. There
is a system unbalance when there are signals with distinct
amplitudes, or phase to phase angles different from 120 deg.,
or both. As it has been shown in the previous section three-
phase PLLs based on trans-vector-type are not useful enough
under unbalanced situations. Therefore other solutions like
DRSF or single-phase PLLs must be used for having an
accurate and independent phase-angle track during unbalances.
III. D ESIGN OBJECTIVES AND SPLL QUALITY
MEASUREMENT
Ideally, the SPLL must have a quick speed of response to
grid disturbances; being especially critical sags, phase-angle
jumps and sags with phase jumps in systems protecting sensi-
tive loads. Moreover the system must be easily implemented
in a microcontroller, DSP or FPGA as a part of a high level
control system.
The SPLL quality measurement can checked in different
ways. The main magnitude to measure the SPLL performance
is the phase-angle error. In steady state, when the system is
tracked, the phase-angle error must be zero. However, when
a disturbance occurs a phase-angle error appears; then the
feedback loop must compensate it. The speed of response to
a disturbance can be measured as the time since it occurs
to the time when the steady state error becomes zero (or
quasi zero). Nevertheless, the speed of response to all different
disturbances is not an absolute measurement of the SPLL
performance; other parameters like recovery overshoots and
average quadratic phase-error during the faults should be taken
into account. Moreover, depending on the application and on
the higher level control the ripple in the outputs, amplitude
error, frequency error and noise immunity may be more or
less important features of the SPLL.
IV. A MPLITUDE - PHASE DOUBLE FEEDBACK LOOP SPLL
The proposed PLL in this paper is shown in 4; it has
two independent feedback loops whose features are shown
below. But, before analyzing these feedback loops, it should be
explained the quasi constant frequency approximation which
has been employed thinking of a discrete implementation.
A. Quasi constant frequency approximation
As it has been explained before, multiple-loop techniques
achieve more degrees of freedom to designers. The best
example of this is the adaptive SPLL proposed in [2] which
has a great performance for several type of disturbances. This
work also shows that the utilization of adaptive techniques
2392
3
gets better the SPLL performance. Nevertheless, the dynamic
of this SPLL has a complex study; moreover the discrete im-
plementation of its adaptive techniques would demand several
linearizations whose effect is not easy to evaluate. Therefore,
using this SPLL in a higher level control system seems
very difficult; the three-loop SPLL has the advantage to face
with amplitude, frequency and phase tracks independently, but
enhances more the whole complexity.
To reduce the three-loop complexity, maintaining the SPLL
performance, can be achieved taking into account the mag-
nitude change of the disturbances. While distribution system
faults can produce great voltage amplitude depressions and
great phase-angle jumps [11], the mean value of the frequency
rarely oscillates more than 1 Hz around the natural frequency.
Therefore, it is correct to consider much smaller frequency
changes than phase-angle or voltage changes. Assuming this
approximation, a double-loop PLL can be developed with sim-
ilar, or better, real performance. Moreover, adaptive techniques
used in [2] and in the Matlab Power System Blockset (PSB)
[12] can be applied using the quasi constant frequency approx-
imation; so they are more useful for a discrete implementation.
B. Amplitude-loop
The PLL first block is the amplitude-loop. Its input signal
→
− →
−
is V phase in p.u. and its outputs are the amplitude of V phase
and the normalized signal which is the input of the phase-
loop. The amplitude of normalized signal must be 1 p.u. so the
gain of the phase-loop maintains itself constant for any input
amplitude. As it is shown in Fig. 5 and in Fig. 4 the output
normalized signal is used in the amplitude-loop to obtain the
amplitude error signal Ec ; the input signal and the output
normalized signal are squared, so when the phase are tracked
Ec can be calculated using (1).
2
Ec = (V̂phase − 1) sin2 (ωt + Φ)
1 sin(2(ωt + Φ)) (1)
2
= (V̂phase − 1)( + )
2 2
Ec pass through the loop filter giving the filtered signal
Ecf which has very attenuated the second harmonic. Then
the dc component of Ecf is used to correct the amplitude
around the nominal amplitude (1 p.u.) being the correct factor
Fc = 1 + Ecf . The low pass filter Kpv improves the response
of a simple PI because it attenuates more the second harmonic
component√ of Ec and therefore it reduces the ripple in Fc . The
inverse of Fc gets the V̂phase measure and the √ normalized
signal is obtained multiplying the input signal by Fc .
C. Phase-loop
After the amplitude-loop, the phase-loop (Fig. 6) is placed.
The input of the phase-loop is the normalized signal. The
phase loop outputs are the phase, the frequency and the
normalized output signal. Actually, the phase-loop works like a
classical PLL using as input a normalized signal which makes
its gain constant. Like in classical PLLs a PI filter with a
integrator is used for phase tracking. The integrator block

Fig. 5. SPLL amplitude-loop.
Fig. 6. SPLL phase-loop.
together with the natural frequency block form the digitally
controlled oscillator (DCO).
But, with respect to the classical PLL loops, this phase-
loop contains blocks which implement adaptive techniques to
improve the system performance. These blocks are explained
as follows.
1) Cancellation of second harmonic in phase detector:
Classical PLL uses a multiplier as phase detector. The phase-
error is obtained from the feedback loop multiplying the input
signal by the output signal led 90 deg. (cos(θo ) ). Then the
output of the multiplier has two terms. A term which only
depends on the signal error, and a second harmonic term (2).
sin(ωt + θi ) × cos(ωt + θo ) =
1 1 (2)
= sin(θi − θo ) + sin(2ωt + θi + θo )
2 2
When the system is tracked the first term of (2) can be
linearized as sin(θi − θo ) ≈ θi − θo . This term has all the
information of the phase error. However, the second term of
(2), which has not information, has a big amplitude. Ideally,
this second harmonic component is eliminated in the loop
filter. However the gain of the loop filter for 2ω is not small
enough to cancel the influence of the second harmonic in the
dynamics. This influence is clearly visible in analog PLLs
where the phase measure has a ripple over the ideal ramp.
The phase detector can help to mitigate the second harmonic
generation. The first try of removing the problem has been ap-
plied in [2] moving the second harmonic to a higher frequency
which is much more attenuated in the low-pass filters.A less
complex, but effective method, has been developed in the
PSB/SPLL [12]. The second harmonic is estimated from the
output phase. Then it is directly subtracted in the output of
2393
4
Fig. 7. Elimination of the second harmonic by subtraction.
Fig. 8. Frequency averager block for a constant frequency (50 Hz).
the multiplier. Due to its simplicity and effectiveness this
method has been employed in the phase detector of the phase-
amplitude-loop (Fig. 6).
The used phase detector is shown in Fig. 7.This system
efficiently eliminates all the second harmonics when the SPLL
is locked, but when it is unlocked, the amplitude of the second
harmonic is multiplied by a factor dependent of instantaneous
tracking error in the system. Such method will be only
advantageous when the SPLL is locked or his tracking error is
little (over less than 5 deg.). This penalizes a little the speed of
response to phase-angle jumps, but the global influence over
the dynamics improves a lot the PLL performance.
2) Frequency averager: After the phase detector the fre-
quency averager (FA) block is put (Fig. 8). This block is an
approximation of the PSB/FVA (Frequency variable averager)
for a fixed frequency value which is the natural frequency
(50 Hz). Its finality is to eliminate the harmonic components
of the input signal. The input of FA is multiplied by the
frequency and integrated. The transport delay block delays
its input signal exactly one cycle (20 ms.). Then from the
output of the integrator, the same signal delayed one cycle is
subtracted. The transfer function of FA is shown in (3); its
main feature in Fig. 6 is its gain which drops abruptly to zero
in all the harmonics of “F req”.
F req −s
H(s) = (1 − e F req ) (3)
s
The discrete implementation of the FA block consumes
memory recurses because the SPLL needs to hold the points of
its input during a cycle. This can be easily seen in the discrete
transfer function (4).
F req · Ts 1
H(z) = (1 − z − F req·Ts ) (4)
z−1
This block can be optionally used in amplitude-loop for
avoiding the ripple in the amplitude measure (Fig.5).
D. Coefficients choice and performance
The rigorous study of the SPLL dynamics is quite complex,
because it contains a lot of nonlinearities; however, the use
of software tools can help the designer in the stability and
performance analysis. The “Simulink response optimization
tool” (SRO) has been employed in this work [13]. The
 5

50

40
1

30

20
0.5
Phase-error (deg.)

Amplitude (p.u.)
10

0
0
-10

-20

-0.5
-30

Vspll
-40

-1 Vphase
-50
0 0.05 0.1 0.15 0.2 0.25 0.3
Time (sec)
0.1 0.15 0.2 0.25 0.3 0.35
Time (s)
Fig. 9. Fitting the phase-angle error during a 0.5 p.u. sag with a +45 deg.
phase-angle jump using the SRO tool.
Fig. 10. SPLL response to a 0.5 p.u. sag with a +45 deg. phase-angle jump.

1.1

SRO tool inputs are the desired SPLL responses (boundary

conditions) for an input signal (disturbance), and the outputs 1
Vspll
are all the coefficient combinations and their response that can
fit to the input boundary conditions (Fig. 9). 0.9 Vphase
Amplitude (p.u.)

In this work, the final coefficients choice has been made

evaluating the SPLL quality parameters for different distur- 0.8

bances, especially the most critical. After this, the stability of

SPLL must be checked in all the possible worst-cases. The 0.7

final election of the coefficients is shown in table I.

0.6
TABLE I
SPLL GAINS 0.5

Amp-loop Ki Amp-loop Kp Phase-loop Ki Phase-loop Kp

0.4
965.5 1.12 148.9 169.3 0.1 0.15 0.2 0.25 0.3 0.35
Time (s)

Fig. 11. SPLL amplitude during the 0.5 p.u. sag with +45 deg. phase jump.
V. S IMULATION RESULTS
Simulations results have been obtained using Mat-
lab/Simulink. These results analyze the main SPLL features used to determine the time used by the SPLL for tracking
during a voltage sag with phase-angle jump of +45 deg, similar after a disturbance; determining when the system is tracked
to Fig. 3. The main reason of electing this disturbance is its depends on a designer criterion. For example, for a phase-
significance over the SPLL whole performance, because it has jump of 45 deg. the designer may establish that the system is
an amplitude depression and a big phase-angle jump. tracked when the phase-error is less than 2.5 deg. However,
→
− this is not an absolute measurement, because a system with
In Fig. 10 it is shown V phase with the disturbance (dashed)
→
− →
− high overshoot can achieve quickly a phase-error smaller than
and the SPLL response V spll (solid); V spll is obtained
multiplying the output amplitude by the normalized output the threshold value, but due to oscillation the system cannot
signal. It can be seen that in approximately a cycle the SPLL be considered tracked.
output is adapted to fault voltage and it spends the same time Comparing these results with the results of adaptive SPLL
to return to pre-fault situation. shown in [2], it can be seen that both systems have similar
The SPLL amplitude measured during the disturbance is performance under amplitude sags and phase-angle jumps.
shown in Fig. 11. It can be seen that the overshoot is greater
→
− VI. R EAL -T IME IMPLEMENTATION RESULTS
when V phase returns to pre-fault situation. It is important to
say that the adaption time depends on the deep of the sag, To analyze the feasibility of the SPLL in a real system it has
being especially critical for very low amplitude sags. Tuning been implemented using the fast prototyping platform dSpace
the SPLL for a faster response to deep sags, involves a high DS1103 which contains a microprocessor, a DSP and an I/O
gain in the amplitude-loop which generates large overshoot in interface. A programmable AC power source has been used
the outputs during the transients. to generate the disturbances. The inputs and outputs of the
In Fig. 12 it is shown the SPLL response for the disturbance prototype have been captured in a digital oscilloscope.
phase-angle steps. The difference between SPLL phase and In Fig. 13 they are shown the input signal from the ac
the real phase gives the phase-error. The phase-error is widely source, the SPLL output signal and the normalized measured

2394
 6

60

50

40 Vphase
Phase-angle (deg.)

VSPLL
30

20

10

-10
0.1 0.15 0.2 0.25 0.3 0.35 0.4
Time (s)

Fig. 12. SPLL phase-angle response to a 0.5 p.u. sag with a +45 deg.
phase-angle jump.

Fig. 14. Real-Time implemented SPLL response to a 0.5 sag with phase-angle
Vphase jump of +45 deg. (Vphase dashed, Vspll solid).

implementation very feasible for its use in programmable

devices like microcontrollers, DSPs or FPGAs, and into a
higher level control system.

ACKNOWLEDGEMENT
Vspll Phase
This work was supported by the Spanish Ministry of Science
and Technology under project number DPI2003-01513.

Fig. 13. Input Vphase , output Vspll and SPLL measured phase-angle.
phase-angle during a typical steady-state situation. It can be
seen that the output signal is closely equal to reference.
Moreover, the phase-angle ramp is straight and it has not
second harmonic, because it has been removed previously in
phase-detector.
In Fig. 14. the real-time response of the SPLL for the
disturbance analyzed in simulation is shown. The input of
SPLL with the disturbance and the synchronized oscilloscope
trigger signal have been generated in the AC power source. It
can be seen that the implementation results are very similar
to the simulation results, which confirms the feasibility of a
discrete implementation of the model.
VII. C ONCLUSIONS
A SPLL for FACTS control has been proposed, and its
features have been shown with simulation and real-time im-
plementation. Moreover, the used algorithms make the discrete
R EFERENCES
[1] N. G. Hingorani and L. Gyugyi., Understanding FACTS, R. J. Herrick.,
Ed. IEEE Press., 2000.
[2] D. Jovcic, “Phase locked loop system for FACTS,” IEEE Transactions
on Power Systems, vol. 18, no. 3, pp. 1116–1124, August 2003.
[3] A. H. Norouzi and A. M. Sharaf., “Two control schemes to enhance the
dynamic performance of the statcom and sssc,” IEEE Transactions on
power delivery., vol. 20, pp. 435–442, 2005.
[4] J. G. Nielsen, F. Blaabjerg, and N. Mohan, “Control strategies for
dynamic voltage restorer compensating voltage sags with phase jump,”
Proceed. of APEC2001, vol. 2, 2001, pp. 1268-1273., vol. 2, pp. 1268–
1273, 2001.
[5] C. Zhang, C. Fitzer, V. K. Ramachandraramurthy, A. Arulampalam,
M. Barnes, and N. Jenkins, “Software phase-locked loop applied to
dynamic voltage restores (DVR),” Proc. IEEE Power Eng. Soc. Winter
Meeting. Conf., vol. 3, pp. 1033–1038, 2001.
[6] V. Kaura and V. Blasko., “Operation of a phase locked loop system
under distorted utility conditions.” IEEE IEEE Transactions on industry
applications., vol. 33, pp. 58–63, 1997.
[7] H. Awad, J. Svensson, and M. Bollen., “Phase-locked loop for static
series compensator.” in EPE, 2003.
[8] P. Rodriguez, J. Pou, J. Bergas, I. Candela, R. Burgos, and D. Boroyevic,
“Double synchronous reference frame pll for power converters control,”
in Conference on Power Electronics Specialists, 2005.
[9] ABB, “Series voltage restorer-data sheet.” 2004, 3BHT 490 484 R001.
[10] R. E. Best, Phase Locked Loops. Design, Simulation and Applications.
4th Edition. McGraw-Hill, 1999.
[11] M. H. J. Bollen., Understanding power quality problems. Voltage sags
and interrupions., R. J. Herrick., Ed. IEEE Press Editorial Board.,
2000.
[12] Mathwoks, Power System BlockSet, User Manual., 2000.
[13] Mathworks., Simulink Response Optimization For Use with Simulink.
User’s guide., 3rd ed., March. 2006.

2395