#define D PORTD

LCD_init()
{
//delay 30ms
data();
//delay 10ms
data();
//delay 1ms
data();
w8();
D = 0b00111100; //F DEGISEBILIR (3. bit)
RS = 0;
RW = 0;
w8();
D = 0b00001000; //RS RW 0 gene
w8();
D = 1;
w8();
D = 0b000001
}
w8()
{
RW = 1;
while(BF) //BF = D7
NOP;
RW = 0
}
data()
{
D4 = 1;
D5 = 1;
D6 = 0;
D7 = 0;
RS = 0;
RW = 0;
}
while(1)
{
LCD_init();