DATA AND RESULTS

Truth Table - FULL ADDER

INPUTS THEORETICAL EXPERIMENTAL

OUTPUTS OUTPUTS

A B CIN S Cout S Cout

0 0 0 0 0 0 0

0 0 1 1 0 1 0

0 1 0 1 0 1 0

0 1 1 0 1 0 1

1 0 0 1 0 1 0

1 0 1 0 1 0 1

1 1 0 0 1 0 1

1 1 1 1 1 1 1

Logic Diagram – FULL ADDER

X2
U6
0 2.5 V
Key = Space U1
U2
U7
0 XOR2 U8 X1
XOR2
Key = Space 0
Key = Space 2.5 V
U3

AND2 U5
U4

OR2
AND2