Branch Counselor’s Message

The IEEE Student Branch of Vellore Institute of Technology has been one of the most
active and innovative branches in our Deemed University. Under the guidance of
Management Authorities of VIT, we have made great strides in spreading knowledge
about the latest technologies amongst our students, through an innovative approach of
combining entertainment with education. The IEEE Student Branch, VIT continues to
carry forward the objectives of IEEE and accomplishing the goals of RAB (Regional
Activities Board). We have always looked forward to innovation and implementation of
new ideas in improving the overall “utility” and “worthiness” of our Branch for the
benefit of our Student Members.

R. Saravana Kumar

Branch Counselor
 Chairman’s Message

Welcome to the September Issue of IEEE Student Branch, VIT Newsletter, SWASTI.

Swasti gives an opportunity to students and faculty of Vellore Institute of Technology

(Deemed University) to pen down their technical knowledge as Technical Articles,
Technical Abstracts and Technical Quizzes, thus giving them a chance to share their
knowledge with other students and faculty.

I am pleased to inform that for every issue of Swasti, one student each, contributing the
best article from Group-A (Consisting of students from Final Year and Pre-Final Year)
and Group-B (Consisting of II Year & I year Students) will be awarded with a certificate.

Moreover, the best article will also be forwarded to be published in the Madras Section
Newsletter, which is circulated in all IEEE Student Branches in Tamil Nadu.

I look forward to more students joining IEEE to become a part of the Esteemed IEEE
Fraternity...

Please mail your feedback/suggestions at zutshiboy@yahoo.com.

Aditya Zutshi

Final Year ECE

Chairman & Editor

 From Editor’s Desk

Welcome to the September Issue of IEEE Student Branch, VIT Newsletter, “Swasti”.
It is heartening to see Students and Faculty Members coming forward for submitting their
Technical Articles for the Newsletter. We hope of having more students and faculty
members contributing Technical Articles/Technical Paper Abstracts/Technical Projects
Abstract/Technical Quizzes for the newsletter in the coming future. Please mail your
contributions for the forthcoming issues to zutshiboy@yahoo.com/
kashyap.reddy@gmail.com

Let The Saga Of IEEE Continue…

Editors:
Aditya Zutshi
IV ECE
Kashyap Reddy
II CSE
Abhinav Bisen
II EIE
 Activities of IEEE Student Branch, VIT in August ‘05

11th August ’05: Guest lecture on Digital Image Processing & Image
Compression – Lecture given by Mr. Mahesh Anand, Lecturer, Department
of Electrical Sciences.
29th – 30th August ’05: Electroutsav ’05, an electronic project exhibition
organized by IEEE Student Branch & Department of Electronics &
Communication.
30th - 31st August ’05: Axon ’05, a technical symposium organized by IEEE
Student Branch, VIT, Department of EEE & Association of Electrical
Engineers.

Certificate for best technical article in Swasti August ’05 Issue

The technical article submitted for Swasti August ’05 Issue by Mr. Dushyant
Mishra, Final Year Bio-Technology on The Big Bang-In The Brain has been selected
as the as the best technical article from Group-A (Consisting of Final Year & Pre-
Final Year Students) and that submitted by Mr. Shyam Bharath, II CSE on Data
Encryption & Compression has been selected as the best technical article from
Group-B (Consisting of II Year & I Year Students).

The IEEE Student Branch, VIT wishes them heartiest congratulations...!!!

 What is MEMS Technology?

Micro-Electro-Mechanical Systems (MEMS) is the integration of mechanical elements,

sensors, actuators, and electronics on a common silicon substrate through micro
fabrication technology. While the electronics are fabricated using integrated circuit (IC)
process sequences (e.g., CMOS, Bipolar, or BICMOS processes), the micromechanical
components are fabricated using compatible "micromachining" processes that selectively
etch away parts of the silicon wafer or add new structural layers to form the mechanical
and electromechanical devices.

Picture 1

MEMS promises to revolutionize nearly every product category by bringing together

silicon-based microelectronics with micromachining technology, making possible the
realization of complete systems-on-a-chip. MEMS is an enabling technology allowing
the development of smart products, augmenting the computational ability of
microelectronics with the perception and control capabilities of microsensors and
microactuators and expanding the space of possible designs and applications.

Microelectronic integrated circuits can be thought of as the "brains" of a system and

MEMS augments this decision-making capability with "eyes" and "arms", to allow
microsystems to sense and control the environment. Sensors gather information from the
environment through measuring mechanical, thermal, biological, chemical, optical, and
magnetic phenomena. The electronics then process the information derived from the
sensors and through some decision making capability direct the actuators to respond by
moving, positioning, regulating, pumping, and filtering, thereby controlling the
environment for some desired outcome or purpose. Because MEMS devices are
manufactured using batch fabrication techniques similar to those used for integrated
circuits, unprecedented levels of functionality, reliability, and sophistication can be
placed on a small silicon chip at a relatively low cost.

1.0 The Beginners guide to MEMS Processing

MEMS technology is based on a number of tools and methodologies, which are used to
form small structures with dimensions in the micrometer scale (one millionth of a meter).
Significant parts of the technology has been adopted from integrated circuit (IC)
technology. For instance, almost all devices are build on wafers of silicon, like ICs. The
structures are realized in thin films of materials, like ICs. They are patterned using
photolithographic methods, like ICs. There are however several processes that are not
derived from IC technology, and as the technology continues to grow the gap with IC
technology also grows. There are three basic building blocks in MEMS technology,
which are the ability to deposit thin films of material on a substrate, to apply a patterned
mask on top of the films by photolithograpic imaging, and to etch the films selectively to
the mask. A MEMS process is usually a structured sequence of these operations to form
actual devices.
Thus these operations are deposition, lithography and etching.

1.1 MEMS and Nano -Technology

MEMS and Nano devices are extremely small. For example, MEMS and Nanotechnology
has made possible electrically-driven motors smaller than the diameter of a human hair
(right), but MEMS and Nanotechnology is not primarily about size.
MEMS and Nanotechnology is also not about making things out of silicon, even though
silicon possesses excellent materials properties, which make it an attractive choice for
many high-performance mechanical applications; for example, the strength-to-weight
ratio for silicon is higher than many other engineering materials which allows very high-
bandwidth mechanical devices to be realized.
Instead, the deep insight of MEMS and Nano is as a new manufacturing technology, a
way of making complex electromechanical systems using batch fabrication techniques
similar to those used for integrated circuits, and uniting these electromechanical elements
together with electronics.

1.2 Advantages of MEMS and Nano Manufacturing

First, MEMS and Nanotechnology are extremely diverse technologies that could
significantly affect every category of commercial and military product. MEMS and
Nanotechnology are already used for tasks ranging from in-dwelling blood pressure
monitoring to active suspension systems for automobiles. The nature of MEMS and
Nanotechnology and its diversity of useful applications make it potentially a far more
pervasive technology than even integrated circuit microchips. Second, MEMS and
Nanotechnology blurs the distinction between complex mechanical systems and
integrated circuit electronics. Historically, sensors and actuators are the most costly and
unreliable part of a macroscale sensor-actuator-electronics system. MEMS and
Nanotechnology allows these complex electromechanical systems to be manufactured
using batch fabrication techniques, decreasing the cost and increasing the reliability of
the sensors and actuators to equal those of integrated circuits. Yet, even though the
performance of MEMS and Nano devices is expected to be superior to macroscale
components and systems, the price is predicted to be much lower.

1.3 Mems and NanoTechnology -Applications

There are numerous possible applications for MEMS and Nanotechnology. As a
breakthrough technology, allowing unparalleled synergy between previously unrelated
fields such as biology and microelectronics, many new MEMS and Nanotechnology
applications will emerge, expanding beyond that which is currently identified or known.
Here are a few applications of current interest:

1.3.1 Biotechnology
MEMS and Nanotechnology is enabling new discoveries in science and engineering such
as the Polymerase Chain Reaction (PCR) microsystems for DNA amplification and
identification, micromachined Scanning Tunneling Microscopes (STMs), biochips for
detection of hazardous chemical and biological agents, and microsystems for high-
throughput drug screening and selection.

1.3.2 Communications
High frequency circuits will benefit considerably from the advent of the RF-MEMS
technology. Electrical components such as inductors and tunable capacitors can be
improved significantly compared to their integrated counterparts if they are made using
MEMS and Nanotechnology. With the integration of such components, the performance
of communication circuits will improve, while the total circuit area, power consumption
and cost will be reduced. In addition, the mechanical switch, as developed by several
research groups, is a key component with huge potential in various microwave circuits.
The demonstrated samples of mechanical switches have quality factors much higher than
anything previously available.

1.3.3 Accelerometers
MEMS accelerometers are quickly replacing conventional accelerometers for crash air-
bag deployment systems in automobiles. The conventional approach uses several bulky
accelerometers made of discrete components mounted in the front of the car with separate
electronics near the air-bag; this approach costs over $50 per automobile. MEMS and
Nanotechnology has made it possible to integrate the accelerometer and electronics onto
a single silicon chip at a cost between $5 to $10. These MEMS accelerometers are much
smaller, more functional, lighter, more reliable, and are produced for a fraction of the cost
of the conventional macroscale accelerometer elements.

1.4 Current Challenges

MEMS and Nanotechnology is currently used in low- or medium-volume applications.
Some of the obstacles preventing its wider adoption are:

1.4.1 Limited Options

Most companies who wish to explore the potential of MEMS and Nanotechnology have
very limited options for prototyping or manufacturing devices, and have no capability or
expertise in microfabrication technology. Few companies will build their own fabrication
facilities because of the high cost. A mechanism giving smaller organizations responsive
and affordable access to MEMS and Nano fabrication is essential.

1.4.2 Packaging
The packaging of MEMS devices and systems needs to improve considerably from its
current primitive state. MEMS packaging is more challenging than IC packaging due to
the diversity of MEMS devices and the requirement that many of these devices be in
contact with their environment. Currently almost all MEMS and Nano development
efforts must develop a new and specialized package for each new device. Most
companies find that packaging is the single most expensive and time consuming task in
their overall product development program. As for the components themselves, numerical
modeling and simulation tools for MEMS packaging are virtually non-existent.
Approaches which allow designers to select from a catalog of existing standardized
packages for a new MEMS device without compromising performance would be
beneficial.

1.4.3 Fabrication Knowledge Required

Currently the designer of a MEMS device requires a high level of fabrication knowledge
in order to create a successful design. Often the development of even the most mundane
MEMS device requires a dedicated research effort to find a suitable process sequence for
fabricating it. MEMS device design needs to be separated from the complexities of the
process sequence.

Manish Kumar
B.Tech II EIE
VIT
 Lost in time
The General Theory of Relativity has 2 postulates.
According to Einstein,
Æ The laws of physics may be expressed in equations having the same form in all frames
of reference.
Æ The speed of light in free space has the same value for all the observers regardless of
their state of motion.

Lorentz transformations give us two important results:

These are Length contraction and Time dilation

L= L0 [1 – (v2/c2)] 1/2 and T=T0/ [1-(v2/c2)] 1/2

Here the symbols represent:

L – The length after contraction

L0 – the original length
T – The time interval perceived by a person
T0 – the original time interval

Thus we have:

The length of an object appears to a person shorter than the original length due to
contraction.

The time perceived by a person in a stationary frame is more than the actual time taken

Using this concept we apply it to particles which can travel with velocities of the order of
the speed of light.
Several types of particle accelerators are found today. The accelerate sub atomic particles
to velocities very near but less than the speed of light. One thing of interest to note here is
that the velocity of these particles should not exceed the speed of light. That is approx.
(3*108 m/s).
Let us assume 2 cases.
1Æ Let us take a case where velocity of particle is more than that of light.
We take velocity of particle to be v.
V=c+x
We get
L = L0 [1-((c + x)/c) 2]1/2
= L0 (-2x/c) 1/2 (as x is much smaller than c)
= L0i (2/c) 1/2(x) 1/2
The effective length obtained is not actually possible in reality.

Similarly,
T = T0 / [1-((C + x)/c) 2]1/2
= T0 / (-2x/c) 1/2 (as x is much smaller than c)
= -T0/(x)1/2i(c/2)1/2

This time interval obtained is imaginary and is not possible in reality.

We may assume that as the velocity of particle is more than velocity of light in air then
the particle may show Cerenkov effect.
Taking a Cerenkov cone,

vt

a
Ct
/n

In this cone
Cos a = c/nv

Substituting v = c+x and n = 1 we get

Cos a = c/c+x
a <~ 90

So Cerenkov cone is not formed and the phenomenon does not take place at all.

These prove to us that material particle can never travel with a velocity more than
velocity of light.

Mathematically,
(s) 2 = (ct )2 – (x)2
x – Short displacement
t – Time interval
Since the object travels with v = c
ct < | x |
s2 < 0
this spacelike event is depicted graphically as

ct

x = ct

At present

unrelated

x = - ct

The area between x = + ct and x = -ct and y = 0 represents this event.

Taking the second case, we consider the object to be traveling with speeds equal to the
velocity of light.
2 Æ Let the velocity of the particle be v
v=c
We get
L = L0 [1-(c/c)2]1/2
= L0 * 0
=0
The effective length obtained is zero. This means that to an observer at rest the effective
length of the object appears to be zero.

Similarly,
T = T0 / [1-(c/c)2]1/2
= T0 / 0
= infinite

This time interval obtained is infinite. To an observer at rest the time of flight of the
object is infinite.
This is possible only when we visualize the universe to be 4 dimensional. The universe as
we see may be three dimensional but in reality there is a fourth dimension of time. To the
person performing the experiment at rest, relative to the object the matter contracts to 0
length and in traveling takes infinite time. So the object gets lost in space. It has actually
been captured in time dimension.

We take a particle accelerator capable of accelerating sub-atomic particles to the speed of

light. We find that the particles show speeds that are slightly less than the speeds of light,
but never equal. Moreover on placing an obstruction in its path not all particles affect it.
Some fraction may be lost. This is primarily because the particle is lost in time dimension
without affecting the object.

Mathematically,
(s)2 = ( ct )2 – (x)2
x – short displacement
t – time interval
Since the object travels with v = c

ct = | x |
s2 = 0
this lightlike event is depicted graphically as

ct

x = ct

At present

Unrelated

x = - ct

The lines x = + ct and x = -ct and y = 0 represents this event.

Thus we conclude that a particle unable to achieve the speed of light is not because it
cannot achieve that speed or because of inefficiency of machine, but because it is lost in
time.
Thus no material particle on this earth is capable to achieve the velocity of light.

Satadru Chakraborty
B.Tech I EEE
VIT
 Plasma – the fourth state of matter
The fourth state of matter, the one with weaker intermolecular attraction than gas is
called plasma. This plasma can be produced by completely ionizing the gas. This
complete ionization can be brought about by many methods. The most useful method to
do this is the laser induction – the core of this article.

Laser induction can be broadly classified into two divisions on the basis of the way
ionization is brought about.

a) Cascade Ionization: On making low wavelength laser incident on neutral

molecules of gas, free electrons are generated. These electrons collide with
neutral molecules of the gas giving rise to ionized molecules and electrons.

M + laser beam Æ electrons

M + e- Æ M+ + 2e-

This leads to increased concentration of metal ions which when collected together
is called Plasma.

b) Multi Photon Ionization: Photons are directly made to incident on the gas
molecules to bring about ionization. But one must remember that ionization can
take place only if the energy of photons is greater than the ionization energy of
the gas.
Ionization rate α Im
I = Irradiance
m = integer

Also,

Both the above mechanisms require high laser irradiance of order of about
10 w/cm . But breakdown of solids has been observed at irradiance of about 106 w/cm2.
8 2

So, one can’t use these methods for direct conversion of solids into plasma. One can
overcome this problem by adopting – “Thermal Runway”

c) Thermal Runway: In this method, one has to heat up the solid with a laser. The
solid vaporizes when heated. Absorption of radiation by electrons in vapours
leads to generation of more electrons. Thus, it is highly helpful in direct
conversion of solids into laser.
APPLICATIONS OF LASER INDUCED PLASMA

i) Plasma production is more sustained and continuous as compared to that

obtained from ICP, d.c arcs.
However, this subject is under research and as such no more advantages have
been reported as yet.

Despite of its ability to produce high quality plasma, lasers can’t be always
relied upon due to the high cost of CO2 lasers – the best lasers among all.

Divya Amarnath
B. Tech I CSE
VIT
 Detecting a Heartbeat with a Cell Phone

Is someone listening in on your vital signs? Conspiracy theorists might be wary of the
latest wireless vital signs monitor, which is the joint work of James C. Lin, an electrical
engineering professor at the University of Illinois at Chicago, and a group of researchers
at Lucent technologies Inc., in Murray Hill, NJ. That team has been developing a method
of extracting heart and respiratory data from cell phone signals, which could be
monitored from the other end of a phone call or over the internet.

The idea is to use wireless handsets as miniature Doppler radars. They would determine
the movement of the outside of the chest by observing how the frequency of their
transmission shifts as it is reflected off part of a person’s body. “The movement of the
chest actually contains both respiration and movement associated with a beating heart,”
said Lin. Earlier work found that signals from chest motion correlate directly with
changes in the pressure inside the heart.

The method requires processing to extract the relevant signals from the background
noise, in principle, be done either within the phone itself, with some hardware and
software modifications or at the receiving station. The researchers have performed
experiments using a Laboratory-built radio operating in the same frequency range as most
cell phones, 800 – 1800MHz. The group has also achieved promising results using analog
cell phones, and Lin is hopeful that digital phones will produce a Doppler response that
requires less signal processing.

If it works, the system could bring remote cardiac monitoring into the hands of many
more people and greatly expand telemedicine’s reach. Lin hopes to try the technique out
on patients three to five years from now. Those fearing that unsavory elements will have
easy access to their breathing pattern can relax, he said. Someone trying to listen in on
another’s heart rate would need both access to the phone’s signal and the right processing
scheme to tease out the data. “It can be done, of course, “he admitted. “But you’d have to
get over some bars first.”

Mahesh Anand S.

Lecturer
School of Electrical Sciences, VIT
 Protein Engineering

Protein Engineering is one of the widely used technologies in the industrial genetics. It is
one of the vital fields of study under biotechnology. The tricks which protein engineering
plays in genetics is worth appreciating. Protein engineering in simple words means the
manipulation of the three dimensional structure of protein, by using the knowledge
gained from X-ray crystallographic technique. As this method helps modification of the
structure of protein, it is used to modify and rectify the structure of various enzymes. This
as a result increases the activity of the enzymes, it's specificity, rate of reaction, spectrum
of the conditions such as pH, temperature etc in which it works. All in all it increases the
efficiency of the enzyme, substrate utilization and the net yield of the product. The
technique gives us the freedom of inserting the desired amino acid residues in the
structure of protein and hence changing the structure of protein. Protein engineering
along with DNA technology is used as a tool by the geneticists and biotechnologists to
improve the strain of micro-organisms used in various cultures like fermentation,
antibiotic production. Therefore recent developments in the fields of medicine, enzyme
technology have been a direct outcome of PROTEIN ENGINEERING. Still many phases
of protein engineering is under research and soon will brought to the limelight by the
young scientists who have buried themselves in the detail study of various aspects of
protein engineering.

Arundhati Choudhury
B.Tech I Bio-Technology
VIT
 Tips on using web graphics for web design

1. GIF vs. JPEG

As you may know, the most widely supported web image graphic formats are GIF and
JPEG. This may add to you confusion--when should I use GIF and when should I use
JPEG?

The easy rule to remember:

1. Use GIF format with graphics that you have created on your computer such as
horizontal rules, buttons, or animation.
2. Use JPEG format when the images are scanned pictures or photographs.

GIF file can contain the maximum of 256 colors (8 bit) or less, which is good for
customizing your graphic files. For example, if you create a GIF image of a red arrow,
you can customize the file to have only two colors, read and white. This means that the
file is very small because its palette contains only two colors. GIF file will yield a higher
quality and smaller size image, compared to JPEG, when it is used with computer
generated graphics such as icons, logos, buttons, etc.

JPEG was built to contain 24-bit (16.7+ million colors) and was developed specifically
for photographic-style images. JPEG stores the information of images by keeping track of
color changes. The advantage of JPEG is that it can carry a smaller file size than GIF
when used in storing photographs and images with a wide variety of shading. But, it will
not yield a smaller file when dealing with low color level and details like computer
generated graphics.

GIFs also have some special features such as animation, transparency, and interlacing.

2. Tips for creating transparent GIFs

Sometimes, you have to create a graphic using anti-aliasing or another method--like

glows, feathers, or drop shadows--to make its appearance look soft. Doing this, the image
looks soft because the edge of image is blended with the background. You have to be
careful when making the image transparent because the edge of the image has some parts
of the original background surface attached. Please look at the examples below.

Both images are transparent GIFs that were created using the anti-aliasing method, which
makes the edge of image look soft. The difference is the first image was created on a
white background and has been made transparent, but the second image was created on a
black background and has been made transparent. Both images were put here on a white
background, so you can see the black color come along with the second image.
To avoid this problem, remember to create your transparent GIFs on a background color
that is the same or close to your web page background color.
If you do not use anti-aliasing, your image may not look nice, but there is no effect when
making it transparent. The image below on the left was created on a gray background,
and the image on the right was created on a white background. Both show no difference
when put on a white background.

3. Dealing with web colors

Have you ever created web pages or graphics in which the colors always change when
being viewed in different machines? Why does this happen? It's because different
platforms use different color palettes. Both Macs and PCs have 256 colors in their system
palettes, but only 216 of them are the same colors.

The major browsers, Netscape and Internet Explorer, use the same palette-management
process to pull colors from the system palettes. So, if you specify colors by randomly
choosing by favor, those colors will be forced by browsers to display incorrectly using
the color in the system palette.

How do I know which colors will not change when they are viewed on different
machines?

The 216 web colors are in the form of 00 33 66 99 CC FF.

The numbers that are put together like the above example are called "Hexadecimal
Colors" (Hex=6). You cannot select these numbers from your system palette, but you can
specify RGB value in your system palette. RGB is red, green, and blue value. These
numbers are used to convert RGB values to Hexadecimal values.

Any color format like CF33B6 is not a 216 web color.

4. Use smaller graphics files in your web page

Speed makes a difference on the Web - the faster your pages load, the more likely you are
to keep the attention of your viewer.

There are two ways to significantly increase the speed of your pages: reduce the number
of graphics images, and reduce the size of graphics images. Although reducing the
number of graphics images can have a dramatic effect on speed, it also diminishes the
content of your site and may not be acceptable to you. Reducing the size of your graphics
images is often the preferable way to speed up the response of your pages.
Try using solid-color GIF images (like logos, cartoons, and text as graphics). The GIF
file format is very efficient with images that have horizontal regions of solid color, so
design your images accordingly.

5. Now the most important tip

You should make your website according to the mood it requires. For a Fun n Frolic
website, you should use contrast colors and lot of animated GIFs for Cartoons. Similarly,
for making an enterprise website, you should focus more on content than web graphics.

Use the colors in such a way that User can read the text properly. Also, the website
should look attractive.

6. Using image maps

Image maps allow you to put hyperlinks into graphics images. If your viewer clicks on
the picture, the browser connects to another HTML page. Image maps are often used for
top-level indexes on homepages.

For example, you made a single image of a Computer. Now, you can define clickable
regions using Image maps and specify links for each of the regions. Doesn’t it sound
interesting?? You can have a link to go into the CD-ROM, one for the Monitor, one for
your Mouse and so on…

Saptarshi Poddar
B.Tech I CSE
VIT
 Hyper Threading

What is Hyper-Threading Technology?

Hyper-Threading Technology is a groundbreaking innovation that significantly improves

processor performance. Pioneered by Intel on the Intel® Xeon™ processor family for
servers, Hyper-Threading Technology has enabled greater productivity and enhanced the
user experience. View Cast introduced Hyper-Threading on the Niagara Power Stream
systems in April 2003.
Hyper-Threading Technology is now supported on the Intel® Pentium® 4 Processor with
HT Technology. Hyper-Threading provides a significant performance boost that is
particularly suited to today's computing climate, applications, and operating systems.

How Hyper Threading Works?

Faster clock speeds are an important way to deliver more computing power. But clock
speed is only half the story. The other route to higher performance is to accomplish more
work on each clock cycle, and that's where Hyper-Threading Technology comes in. A
single processor supporting Hyper-Threading Technology presents itself to modern
operating systems and applications as two virtual processors. The processor can work on
two sets of tasks simultaneously, use resources that otherwise would sit idle, and get
more work done in the same amount of time.
HT Technology takes advantage of the multithreading capability that's built in to
Windows XP and many advanced applications. Multithreaded software divides its
workloads into processes and threads that can be independently scheduled and
dispatched. In a multiprocessor system, those threads execute on different processors. HT
Technology allows a single Pentium

Working Of Hyper Threading Technology

Greater resource utilization equals greater performance and responsiveness.

4 processor to function as two virtual or logical processors. There's still just one physical
Pentium 4 processor in your PC — but the processor can execute two threads
simultaneously
In high-performance workstations, Hyper-Threading Technology enables thread-level
parallelism (TLP) by duplicating the architectural state on each processor while sharing
one set of processor execution resources. When scheduling threads, the operating system
treats the two distinct architectural states as separate "logical" processors, which allows
multiprocessor capable software to run unmodified on twice as many logical processors.
Although Hyper-Threading Technology will not provide the level of performance scaling
achieved by adding a second processor, benchmark tests show video capture applications
can experience up to a 30% gain in performance. This technology will perform best with
operating systems that have been optimized for Hyper-Threading Technology, such as
Windows XP.
View Cast continues to increase the performance of our Niagara product line with the
latest enhancements available such as HT technology. We optimize and test these
configurations resulting with a high-performing and reliable turnkey video capture
system at the best value possible
Implementing hyper-threading
Although hyper-threading might seem like a pretty large departure from the kind of
conventional, process-switching multithreading done on a single-threaded CPU, it
actually doesn't add too much complexity to the hardware. Intel reports that adding
hyper-threading to their Xeon processor added only %5 to its die area. To understand just
how hyper-threading affects the Pentium 4 Xeon's micro architecture and performance,
let's briefly look in a bit more detail at the Xeon's SMT implementation.
Intel's Xeon is capable of executing at most two threads in parallel on two logical
processors. In order to present two logical processors to both the OS and the user, the
Xeon must be able to maintain information for two distinct and independent thread
contexts. This is done by dividing up the processor's micro architectural resources into
three types: replicated, partitioned, and shared. Let's take a look at which resources fall
into which categories:

Register renaming logic

Instruction Pointer
Replicated ITLB
Return stack predictor
Various other architectural registers
Re-order buffers (ROBs)
Partitioned Load/Store buffers
Various queues, like the scheduling queues, uop queue, etc.
Caches: trace cache, L1, L2, L3
Shared Microarchitectural registers
Execution Units
Replicated resources

There are some resources that you just can't get around replicating if you want to
maintain two fully independent contexts on each logical processor. The most obvious of
these is the instruction pointer (IP), which is the pointer that helps the processor keep
track of its place in the instruction stream by pointing to the next instruction to be
fetched. In order to run more than one process on the CPU, you need as many IPs as there
are instruction streams keep track of. Or, equivalently, you could say that you need one
IP for each logical processor. In the Xeon's case, the maximum number of instruction
streams (or logical processors) that it will ever have to worry about is 2, so it has 2 IPs.
Similarly, the Xeon has two register allocation tables (RATs), each of which handles the
mapping of one logical processor's eight architectural integer registers and eight
architectural floating-point registers onto a shared pool of 128 GPRs (general purpose
registers) and 128 FPRs (floating-point registers). So the RAT is a replicated resource
that manages a shared resource (the micro architectural register file).
Partitioned resources
The Xeon's partitioned resources are mostly to be found in the form of queues that
decouple the major stages of the pipeline from one another. These queues are of a type
that I would call "statically partitioned." By this, I mean that each queue is split in half,
with half of its entries designated for the sole use of one logical processor and the other
half designated for the sole use of the other. These statically partitioned queues look as
follows:

Statically Partitioned Queue

The Xeon's fscheduling queue is partitioned in a way that I would call "dynamically
partitioned." In a scheduling queue with 12 entries, instead of assigning entries 0 through
5 to logical processor 0 and entries 6 through 11 to logical processor 1, the queue allows
any logical processor to use any entry but it places a limit on the number of entries that
any one logical processor can use. So in the case of a 12-entry scheduling queue, each
logical processor can use no more than six of the entries.

Dynamically Partitioned Queue

Be aware that the above diagram shows only one of the Xeon's three scheduling queues.
From the point of view of each logical processor and thread, this kind of dynamic
partitioning has the same effect as fixed partitioning: it confines each LP to half of queue.
However, from the point of view of the physical processor, there's a crucial difference
between the two types of partitioning. See, the scheduling logic, like the register file and
the execution units, is a shared resource, a part of the Xeon's micro architecture that is
SMT-unaware. The scheduler has no idea that it's scheduling code from multiple threads.
It simply looks at each instruction in the scheduling queue on a case-by-case basis,
evaluates the instruction's dependencies, compares the instruction's needs to the physical
processor's currently available execution resources, and then schedules the instruction for
execution. To return to the example from our hyper-threading diagram, the scheduler may
issue one red instruction and two yellow to the execution core on one cycle, and then
three red and one yellow on the next cycle. So while the scheduling queue is itself aware
of the differences between instructions from one thread and the other, the scheduler in
pulling instructions from the queue sees the entire queue as holding a single instruction
stream.
The Xeon's scheduling queues are dynamically partitioned in order to keep one logical
processor from monopolizing them. If each scheduling queue didn't enforce a limit on the
number of entries that each logical processor can use, then instructions from one logical
processor might fill up the queue to the point where instructions from the other logical
processor would go unscheduled and unexecuted.
One final bit of information that should be included in a discussion of partitioned
resources is the fact that when the Xeon is executing only one thread, all of its partitioned
resources can be combined so that the single thread can use them for maximum
performance. When the Xeon is operating in single-threaded mode, the dynamically
partitioned queues stop enforcing any limits on the number of entries that can belong to
one thread, and the statically partitioned queues stop enforcing their boundaries as well.

Super threading with a multi threaded processor

One of the ways that ultra-high-performance computers eliminate the waste associated
with the kind of single-threaded SMP described above is to use a technique called time-
slice multithreading, or super threading. A processor that uses this technique is called a
multithreaded processor, and such processors are capable of executing more than one
thread at a time. If you've followed the discussion so far, then this diagram should give
you a quick and easy idea of how super threading works:

Super threaded CPU

You'll notice that there are fewer wasted execution slots because the processor is
executing instructions from both threads simultaneously. I've added in those small arrows
on the left to show you that the processor is limited in how it can mix the instructions
from the two threads. In a multithreaded CPU, each processor pipeline stage can contain
instructions for one and only one thread, so that the instructions from each thread move in
lockstep through the CPU.
To visualize how this works, take a look at the front end of the CPU in the preceding
diagram. In this diagram, the front end can issue four instructions per clock to any four of
the seven functional unit pipelines that make up the execution core. However, all four
instructions must come from the same thread. In effect, then, each executing thread is still
confined to a single "time slice," but that time slice is now one CPU clock cycle. So
instead of system memory containing multiple running threads that the OS swaps in and
out of the CPU each time slice, the CPU's front end now contains multiple executing
threads and its issuing logic switches back and forth between them on each clock cycle as
it sends instructions into the execution core.
Multithreaded processors can help alleviate some of the latency problems brought on by
DRAM memory's slowness relative to the CPU. For instance, consider the case of a
multithreaded processor executing two threads, red and yellow. If the red thread requests
data from main memory and this data aren’t present in the cache, then this thread could
stall for many CPU cycles while waiting for the data to arrive. In the meantime, however,
the processor could execute the yellow thread while the red one is stalled, thereby
keeping the pipeline full and getting useful work out of what would otherwise be dead
cycles.
While super threading can help immensely in hiding memory access latencies, it does
not, however, address the waste associated with poor instruction-level parallelism within
individual threads. If the scheduler can find only two instructions in the red thread to
issue in parallel to the execution unit on a given cycle, then the other two issue slots will
simply go unused.

Hyper-threading: the next step

Simultaneous multithreading (SMT), a.k.a. hyper-threading, takes superthreading to the

next level. Hyper-threading is simply super threading without the restriction that all the
instructions issued by the front end on each clock be from the same thread. The following
diagram will illustrate the point:

Hyper Threaded CPU

Now, to really get a feel for what's happening here, let's go back and look at the single-
threaded SMP diagram.
Single-threaded SMP

If you look closely, you can see what we have done in the hyper-threading diagram is to
take the execution patterns for both the red and the yellow threads in the SMP diagram
and combine them so that they fit together on the single hyper-threaded processor like
pieces from a puzzle. We rigged the two threads' execution patterns so that they
complemented each other perfectly (real life isn't so neat) in order to make this point: the
hyper-threaded processor, in effect, acts like two CPUs in one.
From an OS and user perspective, a simultaneously multithreaded processor is split into
two or more logical processors, and threads can be scheduled to execute on any of the
logical processors just as they would on either processor of an SMP system. We'll talk
more about logical processors in a moment, though, when we discuss hyper-threading
implementation issues.
Hyper-threading strength is that it allows the scheduling logic maximum flexibility to fill
execution slots, thereby making more efficient use of available execution resources by
keeping the execution core busier. If you compare the SMP diagram with the hyper-
threading diagram, you can see that the same amount of work gets done in both systems,
but the hyper-threaded system uses a fraction of the resources and has a fraction of the
waste of the SMP system; note the scarcity of empty execution slots in the hyper-
threaded machine versus the SMP machine.
To get a better idea of how hyper-threading actually looks in practice, consider the
following example: Let's say that the OOE logic in our diagram above has extracted all of
the instruction-level parallelism (ILP) it can from the red thread, with the result that it
will be able to issue two instructions in parallel from that thread in an upcoming cycle.
Note that this is an exceedingly common scenario, since research has shown the average
ILP that can be extracted from most code to be about 2.5 instructions per cycle.
(Incidentally, this is why the Pentium 4, like many other processors, is equipped to issue
at most 3 instructions per cycle to the execution core.) Since the OOE logic in our
example processor knows that it can theoretically issue up to four instructions per cycle
to the execution core, it would like to find two more instructions to fill those two empty
slots so that none of the issue bandwidth is wasted. In either a single-threaded or
multithreaded processor design, the two leftover slots would just have to go unused for
the reasons outlined above. But in the hyper-threaded design, those two slots can be filled
with instructions from another thread. Hyper-threading, then, removes the issue
bottleneck that has plagued previous processor designs
Hyper Threading: The Final Destination

Hyper Threading is the most innovative upcoming technology that is surely going to
enhance the processor performance. It has enabled greater productivity and is going to
boom up technical development in all fields. HT technology is advantageous due its
multithreading capability. As HT technology grows it will surely benefit mankind which
will ultimately lead to widespread technical development

ANUDEEP SAHA
DILIP RAJ
AJAZ MOHAMMAD
ABHISHEK KUMAR

B.Tech I Year
 PC-Based Scrolling Message Display

Equipments Required

1. IC-74174 hex D-type flip flop

2. LED’s
3. 220 ohm resistors
4. PCB
5. Bread Board
6. Wires
7. Soldering Iron

Introduction

In the modern world, the displays on electronic devices have become widely popular.
Everywhere we go we can see displays of text in the dot matrix pattern with text either
scrolling or flashing.
The project made here is the scrolling message display which is being controlled by a
computer based program in TURBO C. The message typed here from the keyboard of the
computer is displayed on the light emitting diodes (LED’s) arranged as 5X7 dot matrix
display in moving message format. The PC’s parallel port serves as an interface between
the circuit and the computer programming. This program is designed to display English
alphabet, numbers and some of the special characters.
The PC’s parallel port is used to output the display code and the clock signal for the
scrolling message display.

Features

LED-based scrolling message displays are increasingly being used for disseminating
information at different places but most of the displays lack in storage capacity and
cannot display a large number of characters at a time. These types of message displays
have the following features:-

1. The message to be displayed is stored in a file and the message length to be displayed
is limited only by free memory space on the hard disk of the computer.

2. The number of characters displayed at a time can be as high as 30.

3. The message stored in the file can be changed using any text editor including
notepad.

4. The running speed of the message displayed can be increased or decreased by

pressing a few keys.
Circuit Description

IC-74174

It contains six hex D-type flip flops. It is used as a 6-bit edge triggered storage parallel
input parallel output (PIPO) storage register. These positive edge triggered flip flops
utilize TTL circuitry to implement D-type flip flop logic. These PIPO registers are used
to shift the signal from left to right.

Information at the D input meeting the setup and whole timing requirement is transferred
to the Q outputs on the positive going edge of the clock pulse. Clock triggering is at the
particular voltage level and is not directly related to the transition time of the positive
going pulse. When the clock input is at either high or low levels, the input signal has no
effect at the output.

Parallel Port

The parallel port is terminated into a 25 pin D-type female connector at the back of the
PC. Each parallel port is actually made up of three ports, namely, data port, status port
and control port. Here, only data port is used for this scrolling message display.
Pins 2 through 9 form the 8-bit data output port. This is purely a write only port, which
means it can only output data. The base address of the first parallel port is ‘378H’. These
pins have been used here to transfer the data from the computer program to the circuit
which then displays the character being entered by the user from the keyboard.
Pins 10 through 13 and 15 are the input pins forming the input port. This is purely a read
only port, which means it can only input data. These pins have not been used here as
there is no need of transferring any data or information from circuit to the computer.
Pins 18 to 25 are grounded while pins 1, 14, 16 and 17 form the control port which is
used for some special control functions of the printer and are not required in this circuit.

Resistors

Resistor is a linear device which resists the flow of current through it. In this circuit
resistors of 220 ohms have been connected in series to the led’s so that proper amount of
current can pass through them.
Resistors of different values are available which can be distinguished from one another
on the basis of colour coding. There are four colored rings on the resistors.

LED

It stands for light emitting diodes. It is a semiconductor devices which emits light of a
particular frequency when current is passed through it. Basically it is a forward biased p-
n junction diode.
Working

Parallel-input parallel-output (PIPO) registers are used to shift the signal from right to
left. The clock pulse and the clock signal are generated by the computer program and the
output from the parallel port (base address 0X378).
IC-74174 has been used as PIPO register, which comprises high speed, hex D-type flip-
flops. It is used as a 6-bit edge-triggered storage register. The data on the inputs of the
flip-flop is transferred for storage during high to low transition of clock. Data lines D0
through D5 of the parallel port are connected to the input pins of the first flip-flop (IC2).
The output of IC2 is fed to the next flip-flop IC input as well as LED. Data line D6 is fed
to IC8, while data line D7 is connected to the clock inputs of IC2 through IC8. Clock pins
of all the flip-flop IC’s are connected together. Master reset pin1 of all the flip-flops is
connected to Vcc. Pins 18 through 25 of the parallel port are grounded. As data present
on lines D0 through D6 shifts from the first stage to the next stage, and so on, the
message appears as scrolling on the dot-matrix Led display.
The present circuit supports a display made of 42 LED’s comprising seven rows and six
columns. Each character is displayed in a matrix of 5 columns and 7 rows, hence the sixth
column LED’s form part of the next character.

Software Description

The software for the scrolling message display has been developed in ‘C’ language and
compiled in ‘Turbo C’. When the scroll.exe file is run, the program tries to open the
message. text file. The file sends the text written in it to the circuit via the parallel port for
display on 5X7 dot matrix pattern.
To increase the running speed of the message press ‘I’ key and to decrease the speed
press ‘D’ key. Press ‘R’ for displaying the message from the beginning. To change the
text being displayed, exit the program by pressing Esc and edit the message.txt file, save
it and execute the scroll.exe file.
The program makes use of the outportb() function, which works perfectly only on
Windows 95/98.

Source Code

#include<stdio.h>
#include<dos.h>
#include<process.h>
#include<graphics.h>
unsigned char str1[15],str2[13],str3[5];
int DELAY =500;
void setcode();
void sendcode();
void getcode(char);
void main()
{
FILE *fp,*FP2;
char line[150],ch,c;
textmode(128+16);
clrscr();
textcolor(6);
gotoxy(33,8);
printf("WELCOME TO PC \n");
gotoxy(23,9);
printf("CONTROLLED SCROLLING MESSAGE DISPLAY");
getch();
clrscr();
fp=fopen("MESS.TXT","w");
printf("\nENTER THE MESSAGE YOU WANT TO BE PRINTED");
printf("\n\nENTER . TO TERMINATE\n");
do
{
scanf("%c",&ch);
fputc(ch,fp);
}while(ch!='.');

fclose(fp);
fp=fopen("MESS.TXT","r");
if(fp==NULL)
{
printf("\n\nCANT CREATE MESSAGE.TXT");
exit(0);
}

clrscr();
startagain:
while(!kbhit())
{
ch=fgetc(fp);
if(ch=='.')
{
printf("EXITING");
exit(0);
}
textmode(128);
printf("\n SCROLLING MESSAGE DISPLAY:Sending\ %c",ch);
getcode(ch); //GETTING THE HEXADECIMAL VALUE OF
CHARACTER
setcode(); //SETTING STRING 2 FOR SENDING
sendcode(); //SENDING STR2 TO THE OUT PORT
 }
ch=getch();
switch(ch)
{
case'i':
case'I': if(DELAY>10)
{
DELAY-=5;
}
else
{
DELAY-=1;
}
if(DELAY<0)
{
DELAY=0;
}
printf("\n SCROLLING MESSAGE DISPLAY:Speed Increased");
break;
case'd':
case'D': DELAY+=10;
printf("\n SCROLLING MESSAGE DISPLAY:Speed Decreased");
break;
case'r':
case'R': rewind(fp);
printf("\n SCROLLING MESSAGE DISPLAY:Strtd frm Begining");
break;
case 27: clrscr();
printf("\n SCROLLING MESSAGE DISPLAY:Exiting");
fclose(fp);
delay(2000);
printf(".");
delay(300);
printf(".");
delay(300);
printf(".");
delay(300);
printf(".");
delay(300);
exit(0);
}
goto startagain; //END OF MAIN
}

void getcode(char ch)

{
switch(ch)
{
case'a':
case'A':
str1[0]=0x7c;str1[1]=0x12;str1[2]=0x11;str1[3]=0x12;str1[4]=0x7c;
break;

case'b':
case'B':
str1[0]=0x36;str1[1]=0x49;str1[2]=0x49;str1[3]=0x49;str1[4]=0x7f;
break;

case'c':
case'C':
str1[0]=0x22;str1[1]=0x41;str1[2]=0x41;str1[3]=0x41;str1[4]=0x3c;
break;

case'd':
case'D':
str1[0]=0x1c;str1[1]=0x22;str1[2]=0x41;str1[3]=0x41;str1[4]=0x7f;
break;

case'e':
case'E':
str1[0]=0x41;str1[1]=0x41;str1[2]=0x49;str1[3]=0x49;str1[4]=0x7f;
break;

case'f':
case'F':
str1[0]=0x01;str1[1]=0x01;str1[2]=0x09;str1[3]=0x09;str1[4]=0x7f;
break;

case'g':
case'G':
str1[0]=0x3a;str1[1]=0x49;str1[2]=0x41;str1[3]=0x41;str1[4]=0x3e;
break;

case'h':
case'H':
str1[0]=0x7f;str1[1]=0x08;str1[2]=0x08;str1[3]=0x08;str1[4]=0x7f;
break;

case'i':
case'I':
str1[0]=0x41;str1[1]=0x41;str1[2]=0x7f;str1[3]=0x41;str1[4]=0x41;
break;

case'j':
case'J':
str1[0]=0x7f;str1[1]=0x41;str1[2]=0x41;str1[3]=0x41;str1[4]=0x21;
break;

case'k':
case'K':
str1[0]=0x41;str1[1]=0x22;str1[2]=0x14;str1[3]=0x08;str1[4]=0x7f;
break;

case'l':
case'L':
str1[0]=0x40;str1[1]=0x40;str1[2]=0x40;str1[3]=0x40;str1[4]=0x7f;
break;

case'm':
case'M':
str1[0]=0x7f;str1[1]=0x02;str1[2]=0x04;str1[3]=0x02;str1[4]=0x7f;
break;

case'n':
case'N':
str1[0]=0x7f;str1[1]=0x08;str1[2]=0x04;str1[3]=0x02;str1[4]=0x7f;
break;

case'o':
case'O':
str1[0]=0x3e;str1[1]=0x41;str1[2]=0x41;str1[3]=0x41;str1[4]=0x3e;
break;

case'p':
case'P':
str1[0]=0x06;str1[1]=0x09;str1[2]=0x09;str1[3]=0x09;str1[4]=0x7f;
break;

case'q':
case'Q':
str1[0]=0x3e;str1[1]=0x61;str1[2]=0x51;str1[3]=0x41;str1[4]=0x3e;
break;

case 'r':
case 'R':
str1[0]=0x46;str1[1]=0x29;str1[2]=0x19;str1[3]=0x09;str1[4]=0x7F;
break;
case 's':
case 'S':
str1[0]=0x32;str1[1]=0x49;str1[2]=0x49;str1[3]=0x49;str1[4]=0x26;
break;

case 't':
case 'T':
str1[0]=0x01;str1[1]=0x01;str1[2]=0x7F;str1[3]=0x01;str1[4]=0x01;
break;

case 'u':
case 'U':
str1[0]=0x3F;str1[1]=0x40;str1[2]=0x40;str1[3]=0x40;str1[4]=0x3F;
break;

case 'v':
case 'V':
str1[0]=0x1F;str1[1]=0x20;str1[2]=0x40;str1[3]=0x20;str1[4]=0x1F;
break;

case 'w':
case 'W':
str1[0]=0x7f;str1[1]=0x20;str1[2]=0x10;str1[3]=0x20;str1[4]=0x7F;
break;

case 'x':
case 'X':
str1[0]=0x63;str1[1]=0x14;str1[2]=0x08;str1[3]=0x14;str1[4]=0x63;
break;

case 'y':
case 'Y':
str1[0]=0x03;str1[1]=0x04;str1[2]=0x78;str1[3]=0x04;str1[4]=0x03;
break;

case 'z':
case 'Z':
str1[0]=0x03;str1[1]=0x04;str1[2]=0x08;str1[3]=0x11;str1[4]=0x61;
break;

case '0':
str1[0]=0x1C;str1[1]=0x22;str1[2]=0x41;str1[3]=0x22;str1[4]=0x1C;
break;

case '1':
str1[0]=0x40;str1[1]=0x40;str1[2]=0x7F;str1[3]=0x42;str1[4]=0x44;
break;

case '2':
str1[0]=0x46;str1[1]=0x49;str1[2]=0x51;str1[3]=0x61;str1[4]=0x42;
break;

case '3':
str1[0]=0x31;str1[1]=0x4B;str1[2]=0x45;str1[3]=0x49;str1[4]=0x21;
break;

case '4':
str1[0]=0x10;str1[1]=0x7F;str1[2]=0x12;str1[3]=0x14;str1[4]=0x18;
break;

case '5':
str1[0]=0x31;str1[1]=0x49;str1[2]=0x49;str1[3]=0x49;str1[4]=0x27;
break;

case '6':
str1[0]=0x32;str1[1]=0x49;str1[2]=0x49;str1[3]=0x51;str1[4]=0x3A;
break;

case '7':
str1[0]=0x07;str1[1]=0x79;str1[2]=0x01;str1[3]=0x01;str1[4]=0x01;
break;

case '8':
str1[0]=0x36;str1[1]=0x49;str1[2]=0x49;str1[3]=0x49;str1[4]=0x36;
break;

case '9':
str1[0]=0x3E;str1[1]=0x49;str1[2]=0x49;str1[3]=0x49;str1[4]=0x26;
break;

case '.':
str1[0]=0x60;str1[1]=0x60;str1[2]=0x00;str1[3]=0x00;str1[4]=0x00;
break;

case ' ':

str1[0]=0x00;str1[1]=0x00;str1[2]=0x00;str1[3]=0x00;str1[4]=0x00;
break;

case '!':
str1[0]=0x67;str1[1]=0x7F;str1[2]=0x00;str1[3]=0x00;str1[4]=0x00;
break;
 case '-':
str1[0]=0x08;str1[1]=0x08;str1[2]=0x08;str1[3]=0x08;str1[4]=0x08;
break;

case '+':
str1[0]=0x08;str1[1]=0x08;str1[2]=0x3E;str1[3]=0x08;str1[4]=0x08;
break;

case '_':
str1[0]=0x40;str1[1]=0x40;str1[2]=0x40;str1[3]=0x40;str1[4]=0x40;
break;

default:
str1[0]=0x0;str1[1]=0x0;str1[2]=0x0;str1[3]=0x0;str1[4]=0x0;
break;
}
}

void setcode()
{
int i,k;
for(i=0,k=0;i<10;i+=2,k++)
{
str2[i]=str1[k];
str2[i+1]=str1[k]+128;
}
str2[i]=0;
str2[i+1]=128;
}

// THIS WILL SEND IT TO PORT(PARRALEL)

void sendcode()
{
int i;
for(i=0;i<12;i++)
{
outportb(0x0378,str2[i]); //interfacing
delay(DELAY);
}
} Robab Haider II-MSSE
Khyati Shrivastava B.Tech II CSE
Piyush Sharma B.Tech II TC
 The Electric Automobile

Introduction:
The electric vehicle is presented in the last years as the future alternative in the
urban transport. The comparisons between this one and the major competitor, the
combustion automobile are always better for the last one due to the economic reasons and
for its capabilities and infrastructure facilities. All main automotive companies are
involved in new prototypes of electric vehicles as an alternative of the problems that the
present automobile have.

Parameters To Justify The Use Of Electric Vehicles:

Environmental Reasons:
The first favorable consequence of the electric car is its low or zero direct
contamination or contamination during its use. The difference with the combustion cars
is mainly that those burn organic fuels giving as a consequence that the emission of
CO to the environment of the cities which cause the greenhouse gas effect. The electric
car do not produce this effect in a direct form, so it is possible its control.

Comparison of contaminate levels for each type of vehicle

Gasoline Diesel Electric

Dust 15 135 26
SO2 100 220 630
NOx 880 840 276
HC 310 300 16
CO 2150 2140 27
CO2 234 214 126

The consumption of each type of vehicle was compared and can be seen in the following
lines:

• Diesel motorization : 6.5l in 100km

• Gasoline motorization : 8.5l in 100km
• Electric motorization : 28kwh in 100km
One more advantage of electric cars is that they are extremely silent where as the
combustion cars reach values about 70db.

Present availability:
 One of the most important limitations in the current electric cars in comparison to
the combustion cars, is its autonomy and its capacity of energy storage. General
conclusions obtained in medium values are outstanding due to the number of kilometers
done daily are directly related with the number of displacements done daily and per day,
being 40km the mean value at a medium velocity of 50km/h, and being the medium
number of passengers two with a 30% of the volume of the baggage occupied. These are
highly energy saving cars than the conventional combustion cars.

Infrastructures:

One of the most important difficulties for the development of electric cars is, the
absence of the necessary infrastructures for the maintenance of these types of vehicles.
In comparison with combustion cars, it takes several hours to achieve a full charge of the
energy storage system (batteries) of the electric cars, against few minutes to fill the tank
of gasoline. The introduction of electric cars in big cities will involve conditioning of
places for battery recharge, as well as the recondition of housing garages and car repair
shops. All this things, will rise the electric energy consumption, so it will be necessary for
creation of new auxiliary power stations, moreover it will be necessary for a readjustment
of the energy supply, because the electric energy consumption, will raise during nights,
due to the recharge of electric’s cars will take place during this hours mainly.

Weight and performance qualities:

Nowadays two important parameters limit the success of electric car in the
market, the first one is the ratio: weight of energy storage / total weigh, which is
extremely favorable for combustion cars (a few litters against more than 300Kg), and the
second one is the performance qualities like acceleration, autonomy, maximum velocity,
etc.

In a combustion car, the fuel tank represents a 5% of the total weight of the car,
how ever in a electric car the weight of the batteries represent a 40%. As can be seen,
with these data in our hands, it is very easy to see that the weight in a electric car is a
decisive factor if it is compared to the combustion car. The load capacity in electric cars
is far away from the same in combustion cars, that is the reason because, there is no
development of systems were the load capacity is determinant, as trucks or coaches.

The second inconvenient, can be explained with the classifications that has been
done with this type of vehicles: urban cars, because for urban cycles of driving, the
performance qualities of an automobile are not as important as other types of cycles of
driving, as a road cycle of driving for example. For urban cycles of driving it is no
necessary high performances qualities as high accelerations, or high maximum velocities
that can be given by combustion cars, due to limitations in maximum velocities and dense
road traffic of big cities. The great difference between the performance qualities of
electric and combustion cars lie in current motors, the energetic power obtained in
electric motors by using electric energy for the same relations in weight and size.
Conclusion:
↓ The relationship between the weight of the energy storage system (batteries) and
the weight of the rest of the vehicle is unfavorable for electric cars, as a consequence
there are no vehicles for mass transportation due to the limitations in the load capacity.
↓ The quality performances are higher in the combustion car than in electric car.
↓ The autonomy of combustion cars is higher than the electric cars.
↓ There are no infrastructure for maintenance of electric vehicles yet.
↑ The level of contamination is very low though depending on the origin of the
energy supply.

In order to have a serious alternative to the present car, it is necessary to search

the adequate properties and a competitive design, because the electric car has more
inconvenience than combustion car as we have mentioned above. That the reason because
the electric car is restricted to users as urban car, with reduced dimensions, easy way of
driving, low levels of consumption and an enough autonomy for daily use for two people
in the city.

SEGU SAI BALA KRISHNA

V.SRAVAN KUMAR
B.Tech II IT
VIT
 Submission of Articles for Forthcoming Swasti Issues

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 IEEE Student Branch, VIT Executive Committee 2005-2006

Branch Counselor
Mr. R. Saravana Kumar, Senior Lecturer EEE Department

Chairman
Mr. Aditya Zutshi, IV ECE
Vice Chairman
Mr. Rahul Pratyush Mohanty, III EIE
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Mr. Kashyap Reddy, II CSE
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