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Schedulability Analysis
Marco Di Natale
Scuola Superiore S. Anna
Outline
• Algorithm:
– It is the logical procedure to solve a certain problem
– It is informally specified a a sequence of elementary steps
that an “execution machine” must follow to solve the
problem
– It is not necessarily expressed in a formal programming
language!
• Program:
– It is the implementation of an algorithm in a programming
language
– Can be executed several times with different inputs
• Process:
– An instance of a program that given a sequence of inputs
produces a set of outputs
Operating System
Programmer
Level Web Printer
Shell Videogame
Browser Daemon
System
Level Interface (System API)
• Why abstraction?
– Programming the HW directly has several drawbacks
• It is difficult and error-prone
• It is not portable
– Suppose you want to write a program that reads a text file
from disk and outputs it on the screen
• Without a proper interface it is virtually impossible!
Abstraction Mechanisms
• performance
– take advantage of blocking time
• while some thread waits for a blocking condition, another thread
performs another operation
– parallelism in multi-processor machines
• if we have a multi-processor machine, independent activities can be
carried out on different processors are the same time
• expressive power
– many control application are inherently concurrent
– concurrency support helps in expressing concurrency, making
application development simpler
theoretical model
Stack
Stack
(variable size)
Stack (variable size)
BSS
Initialized Data
Text
Processes
TID
Thread Table PID
CR
IP
SP
Other Reg.
State
Priority
Time left
...
Thread states
b
Start
a Ready Running
c
f
e d
Blocked Terminate
Thread queues
Ready queue
Admit Dispatch
CPU
Preemption
• It happens when
– The thread has been “preempted” by another higher priority
thread
– The thread blocks on some condition
– In time-sharing systems, the thread has completed its “round”
and it is the turn of some other thread
• We must be able to restore the thread later
– Therefore we must save its state before switching to another
thread
Time sharing systems
CPU
Timer
interrupt
Background on Programming …
• Scheduler:
– two level scheduling: events and tasks
– scheduler is simple FIFO
– a task can not preempt another task
– events (interrupts) preempt tasks (higher priority)
main {
…
while(1) {
while(more_tasks)
schedule_task;
sleep;
}
}
TinyOS: OS for WSN
typedef struct {
tp
void (*tp) ();
} TOSH_sched_entry_T; TOSH_MAX_TASKS
Task code
TOSH_sched_full
TOSH_sched_free
TOSH_queue
enum {
TOSH_MAX_TASKS = 8,
TOSH_TASK_BITMASK = (TOSH_MAX_TASKS - 1)};
TOSH_sched_entry_T TOSH_queue[TOSH_MAX_TASKS];
volatile uint8_t TOSH_sched_full;
volatile uint8_t TOSH_sched_free;
TinyOS: OS for WSN
void TOSH_sched_init(void)
{
TOSH_sched_free = 0;
TOSH_sched_full = 0;}
bool TOS_empty(void)
{
return TOSH_sched_full == TOSH_sched_free;
}
TinyOS: OS for WSN
bool TOS_post(void (*tp) ()) __attribute__((spontaneous)) {
__nesc_atomic_t fInterruptFlags;
uint8_t tmp;
/*
fInterruptFlags = __nesc_atomic_start(); * TOS_post (thread_pointer)
*
tmp = TOSH_sched_free; * Put the task pointer into the
TOSH_sched_free++; * next free slot.
TOSH_sched_free &= TOSH_TASK_BITMASK; * Return 1 if successful,
* 0 if there is no free slot.
if (TOSH_sched_free != TOSH_sched_full) { *
__nesc_atomic_end(fInterruptFlags); * This function uses a
* critical section to protect
TOSH_queue[tmp].tp = tp; * TOSH_sched_free.
return TRUE; * As tasks can be posted in both
} * interrupt and non-interrupt
else { * context, this is necessary.
TOSH_sched_free = tmp; */
__nesc_atomic_end(fInterruptFlags);
return FALSE;
}
}
TinyOS: OS for WSN
bool TOSH_run_next_task () {
__nesc_atomic_t fInterruptFlags; uint8_t old_full; void (*func)(void);
• a resource can be
– a HW resource like a I/O device
– a SW resource, i.e. a data structure
– in both cases, access to a resource must be regulated to
avoid interference
• example 1
– if two processes want to print on the same printer, their
access must be sequentialised, otherwise the two printing
could be intermangled!
• example 2
– if two threads access the same data structure, the operation
on the data must be sequentialized otherwise the data could
be inconsistent!
interaction model
Shared memory
mutual exclusion problem
• bad interleaving:
...
LD R0, x TA x = 0
LD R0, x TB x = 0
INC R0 TB x = 0
ST x, R0 TB x = 1
INC R0 TA x = 1
ST x, R0 TA x = 1
...
critical sections
• definitions
– the shared object where the conflict may happen is a “resource”
– the parts of the code where the problem may happen are called
“critical sections”
• a critical section is a sequence of operations that cannot be interleaved
with other operations on the same resource
– two critical sections on the same resource must be properly
sequentialized
– we say that two critical sections on the same resource must
execute in MUTUAL EXCLUSION
– there are three ways to obtain motual exclusion
• implementing the critical section as an atomic operation
• disabling the preemption (system-wide)
• selectively disabling the preemption (using semaphores and mutual
exclusion)
critical sections: atomic operations
• multi-processor
– define a flag s for each resource
– use lock(s)/unlock(s) around the critical section
• problems:
– busy waiting: if the critical section is long, we waste a lot of
time
– cannot be used in single processors!
int s;
...
lock(s);
<critical section>
unlock(s);
...
critical sections: disabling preemption
<disable preemption>
<critical section>
<enable preemption> no context
switch may happen
during the critical
section
general mechanism: semaphores
typedef struct {
<blocked queue> blocked;
int counter;
} sem_t; Note:
the real prototype
void sem_init (sem_t &s, int n); of sem_init is
slightly different!
void sem_wait (sem_t &s);
void sem_post (sem_t &s);
wait and signal
• system calls
– wait() and signal() involve a possible thread-switch
– therefore they must be implemented as system calls!
• one blocked thread must be removed from state RUNNING and
be moved in the semaphore blocking queue
• protection:
– a semaphore is itself a shared resource
– wait() and signal() are critical sections!
– they must run with interrupt disabled and
by using lock() and unlock() primitives
semaphore implementation (2)
Specifications
Software design
sign-off
Control algorithm
design
Functional
Control design testing
sign-off
Software design
RTS and Platform-Based Design
Platform based design and the decoupling of Functionality and Architecture
enable the reuse of components on both ends in the meet-in-the middle
approach
Reuse of functions on different
architectures
Application Space Vehicle functional model
Independent of Platform
Application
instance
Functional
Platform
specification
Functional Model System platform model
interface System
Platform Independent from both and suitable for
Architecture Stack evaluation of mapping solutions
Architecture Platform
Platform space
exploration
Platform
instance
Execution architecture model
Architecture Space Independent of Functionality
Reuse of resources to
implement different
functions
RTS and Platform-Based Design
• Design (continued): matching the logical design into the SW
architecture design
Dispenser Kiosk
functional model)
0..1 active 1 halt 1..16 controlled by 1 payment due
Motor 1 resume
activeEH theDispenser get fuel price aDispenser theKiosk dispensing authorized
status myMotor fuel pulse
nozzle replaced request service display fuel price
stop
dispensing authorised «boundary» request service
start Keyboard Unit 1 1
resume halt dispensing
1 «entity» {persistence = transitory} myController resume dispensing
«boundary» myEH dispensing completed
Fuel Transaction
Flowmeter 1 select dispenser
1
myMeter litres dispensed abort transaction
count 1
price per litre collect transaction
«boundary» 1 total cost 1 dDisplay 1
Holster Switch mySwitch create «boundary»
0..1 1
collect details Dispenser Display
status
destroy
perform display check 1 theDisplay sends trans. details to
add 5ml
freeze display «boundary»
update display Kiosk Display
Task and
Resources Threads (tasks)
resource
Threads (tasks)
model
RTOS API
RTOS
Timing attributes (from
platform deployment)
An introduction to Real-Time scheduling
• Application of schedulability theory (worst case timing
analysis and scheduling algorithms)
• for the development of scheduling and resource
management algorithms inside the RTOS, driving the
development of efficient (in the worst case) and predictable
OS mechanisms (and methods for accessing OS data
structures)
• for the evaluation and later verification of the design of
embedded systems with timing constraints and possibly for
the synthesis of an efficient implementation of an
embedded system (with timing constraints) model
– synthesis of the RTOS
Real-time scheduling
• Assignment of system resources to the software threads
• System resources
– pyhsical: CPU, network, I/O channels
– logical: shared memory, shared mailboxes, logical channels
• Typical operating system problem
• In order to study real-time scheduling policies we need a model
for representing
– abstract entities
• actions,
• events,
• time, timing attributes and constraints
– design entities
• units of computation
• mode of computation
• resources
Classification of RT Systems
• Based on input
– time-driven: continuous (synchronous) input
– event-driven: discontinuous (asynchronous) input
• Based on criticality of timing constraints
– hard RT systems: response of the system within the timing
constraints is crucial for correct behavior
– soft RT systems: response of the system within the timing
constraints increases the value of the system
• Based on the nature of the RT load:
– static: predefined, constant and deterministic load
– dynamic: variable (non deterministic) load
• real world systems exhibit a combination of these characteristics
Classification of RT Systems: criticality
-∞
Classification of RT Systems: Input-based
• Activation models
InstanceA : InstanceB :
helloMsg
{0 ms}
{1.5 ms}
{2 ms}
2.7 ms
{4.7 ms}
ackMsg
{10.2 ms}
{11 ms}
Modeling Real-time systems
• What type of timing constraints are in a Simulink
diagram?
Scheduling of Real-time systems
• What are the key concepts for real-time systems?
– Schedulable entities (threads)
– Shared resources (physical – HW / logical)
– Resource handlers (RTOS)
• Defined in the design of the Architectural level
Our definition of real-time
• Based on timing correctness
Completion time Slack
– includes timing constraints Start time
Deadline
• Response times
• Deadlines
• Jitter Release time
time
• Release times, slack …
• Precedence and resource constraints
Real-time systems: handling timing constraints
• “the fastest possible response is desired. But, like the cruise control
algorithm, fastest is not necessarily best, because it is also desirable
to keep the cost of parts down by using small microcontrollers. What is
important is for the application requirements to specify a worst-case
response time. The hardware and software is then designed to meet
those specifications“
• “Embedded systems are usually constructed with the least powerful
computer that can meet the performance requirements. Marketing and
sale concerns push for using smaller processors and less memory
reducing the so-called recurring costs”
Real-time systems: handling timing constraints
Task 1
Task 2
Task 1
Task 2
Real-time systems: handling timing constraints
C
T1 3
T2 2
T3 2
P1 T1 T9 T4 2
P2 T2 T4 T5 T7 T5 4
P3 T3 T6 T8 T6 4
T7 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 T8 4
T9 9
Operating Systems background
• Increasing the number of processors …
completion time=15
C
T1 3
T2 2
T3 2
P1 T1 T7
T4 2
P2 T2 T5 T8
T5 4
P3 T3 T6 T9 T6 4
P4 T4 T7 T7 4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
T8 4
T9 9
A typical solution: cyclic scheduler
= 50 msec function A
= period 100 msec (function B)
= 200 msec (2 functions C, D)
= 400 msec (4 functions : E, F, G, H)
A typical solution: cyclic scheduler
Advantages:
• simplicity (no true OS, only dispatcher tables)
• efficiency
• observability
• jitter control
• extremely general form (handles general precedence and resource
constraints)
Disadvantages
• almost no flexibility
• potentially hides fundamental information on task interactions
• additional constraints on scheduling
• all functions scheduled in a minor cycle must terminate before
the end of the minor cycle.
A+B+E ≤ minor cycle time (the same for A+C+F, A+B+G, A+D+H)
Problems with cyclic schedulers
• Solution is customized upon the specific task set
– a different set, even if obtained incrementally, requires a completely
different solution
• Race conditions may be “hidden” by the scheduling solution
– see the shared resource section
– problems due to non-protected concurrent accesses to shared
resources may suddenly show up in a new solution
Problems with cyclic schedulers
• Solution is customized upon the specific task set
• what happens if in our example …
– we change the implementation of C and A+C+F > minor cycle?
– Possible solution: C is split in C1 and C2 (this might not be easy)
With Resources
With Offsets
Optimal Pri ass. Yes (Aud) [Aud]
Test Processor Demand
Case 1: Independent periodic tasks
T1 T1 t
t
1 2 3 4 5 1 2 3 4 5
T2 t
T2 t
1 2 3 4 5 1 2 3 4 5
T2 t
1 2 3 4 5
T1 t
1 2 3 4 5
CRITICAL
TIME ZONE
Rate Monotonic
0,9
0,8
0,7
0,6
1 2 3 4 5 6 7 8 9 10
number of t a s k s
Response time based guarantee
• Response time is the sum of
• Execution time
– Time spent executing the task
• Non schedulable entities with higher priority
– Interrupt Handlers
• Scheduling interference
– Time spent executing higher priority jobs
• Blocking time
– Time spent executing lower priority tasks
• Because of access to shared resources
Yes!
Example #2
• Task τ1 : C1 =20; T1 =100; D1 =100
Task τ2 : C2 =30; T2 =145; D2 =145
Task τ3 : C3 =68; T3 =150; D3 =150
Ri
Ri = Ci + ∑ C j
j∈hp ( i ) T j
win
wi = Ci + ∑ C j
n +1
j∈hp ( i ) T j
Algorithm
Deadline Monotonic (DM)
• More later...
Arbitrary Deadlines
• Case when deadline Di < Ti is easy…
• Case when deadline Di > Ti is much harder
– multiple iterations of the same task may be alive
simultaneously
– may have to check multiple task initiations to obtain the
worst case response time
• Example: consider two tasks
– Task 1: C1 = 28, T1 = 80
– Task 2: C2 = 71, T2 = 110
– Assume all deadlines to be infinity
Arbitrary Deadlines (contd.)
• Response time for task 2:
activation completion time response time
0 127 127
110 226 116
220 353 133
330 452 122
440 551 111
550 678 128
660 777 117
770 876 106
w n
i (q)
wi (q ) = (q + 1)Ci + ∑
n +1
C j
j∈hp ( i ) T j
Ri (q) = wi (q ) − qTi
• The number of releases that need to be considered is bounded by
the lowest value q* of q = 0,1,2,… for which the following relation is
true:
q* = min q Ri (q ) ≤ Ti
• Note: for D ≤ T, the condition is true for q=0 if the task can be
scheduled, in which case the analysis simplifies to original
– if any R>D, the task is not schedulable
Arbitrary Deadlines (contd.)
PriorityAssignment(∆)
∆ set of all tasks
{
j priority level
for j in (n..1) { feasible() feasibility test
unassigned = TRUE Ψ(j) inverse of priority
for τA in ∆ { level assignment
if ((feasible(τA, j)) { function
Ψ(j) = τA
∆ = ∆ – τA
unassigned = FALSE
}
if (unassigned)
exit // NOT SCHEDULABLE
}
}
• Processor demand criterion
Response Time Analysis
• Response time Analysis runs in pseudopolynomial
time
• Is it possible to know a-priori the time intervals over
which the test should be performed?
– The iterative procedure tests against increasing intervals
corresponding to the wik
• The alternative method is called processor demand
criterion
• It applies to the case of static and dynamic priority
Fixed Priority Scheduling
• Utilization-based Analysis
• Response time Analysis
• Processor Demand Analysis
– Important: allows for sensitivity analysis ....
Processor Demand Analysis
• Consider tasks τ1, τ2, … τn in decreasing order of
priority
• For task τi to be schedulable, a necessary and
sufficient condition is that we can find some t ∈ [0,Ti]
satisfying the condition
• Notation
Wi(t) = Σj=1..iCjt/Tj
Li(t) = Wi(t)/t
Li = min0 ≤ t ≤ Ti Li(t)
L = max{Li}
• General sufficient & necessary condition:
– Task τi can be scheduled iff Li ≤1
• Practically, we only need to compute Wi(t) at all times
αi = {kTj | j=1,…,I; k=1,…,Tj/Tj}
– these are the times at which tasks are released
– Wi(t) is constant at other times
• Practical RM schedulability conditions:
– if mint∈αi Wi(t)/t ≤ 1, task τi is schedulable
– if maxi∈{1,…,n}{mint∈αi Wi(t)/t} ≤ 1, then the entire set is schedulable
Example
• Task set:
• τ1: T1=100, C1=20
Wi(t)
• τ2: T2=150, C2=30
• τ3: T3=210, C3=80
• τ4: T4=400, C4=100
• Then:
• α1 = {100}
• α2 = {100,150} time
• α3 = {100,150,200,210} Points that need to be checked
• α4 = {100,150,200,210,300,400}
• Preemptive Scheduling
– Dispatch Priority = Base Priority
• Non-Preemptive Scheduling
– Dispatch Priority = Maximum Priority
Preemption Threshold (dual priority) : esempio
Tasks Ci Ti Di πi
• Task τ1 20 70 50 1
τ2 20 80 80 2
τ3 35 200 100 3
τ1
τ2
τ3
0 20 40 70 80 90 95
WCRT τ3
Preemption Threshold: analysis
• Before a task τi starts execution, there is blocking from lower
priority tasks and interference from higher priority tasks.
Among all lower priority tasks, only one lower priority task can
cause blocking. The maximum blocking time of a task τi,
denoted by B(τi), is given by:
• All higher priority tasks that come before the start time
Si(q) and any earlier instances of task τi before instance q
should be finished before the q-th start time.
Preemption Threshold: analysis
• Once the q-th instance of task τi starts execution, we have to
consider the interference to compute its finish time. From the
definition of preemption threshold, we know that only tasks with
higher priority than the preemption threshold of τi can preempt
τi and get the CPU before it finishes. Furthermore, we only
need to consider new arrivals of these tasks, i.e., arrivals after
Si(q).
Release Jitter
• A key issue in
distributed systems
• Sporadic task will be
released at time 0, 5,
25, 45, and so on …
• i.e. at times 0, T-J, 2T-
J, 3T-J, and so on…
Release Jitter (contd.)
• Examination of the derivation of the schedulability
equation implies that process i will suffer one
interference from S if Ri is between 0 and T-J, that is
Ri ∈ [0, T–J), two if Ri ∈ [T–J, 2T-J), three if Ri ∈ [2T–
J, 3T-J), and so on…
Release Jitter (contd.)
• In general, periodic tasks do not suffer jitter
• But, an implementation may restrict granularity of
system timer which releases periodic tasks
• a periodic task may therefore suffer from jitter
• If response time is to be measured relative to the real
release time then the jitter value must be added to
that previously calculated:
Riperiodic = Ri + Ji
Arbitrary Deadlines with Release Jitter
Tasks with Jitter/Processor demand (dbf)
• Task τ1: T1=50, C1=10 J1=10, τ2: T2=80, C2=20 J2=20
Ri + J j
Ri = Ci + ∑ C j
match=wcrt
match=wcrt j∈hp ( i ) Tj
J1 time
Availability of processor time
J2
Task A
• RM
Task B
• EDF...
Task A
Task B
…utilization Task A
can be
further Task B
increased !
Earliest Deadline First
• Problems
– absolute deadlines change for each new task instance,
therefore the priority needs to be updated every time the task
moves back to the ready queue
– more important, absolute deadlines are always increasing,
how can we associate a (finite) priority value to an ever-
increasing deadline value
– most important, absolute deadlines are impossible to compute
a-priori (there are infinitely many). Do we need infinitely many
priority levels?
– What happens in overload conditions?
Implementation of fixed priority
extracting a task
requires finding First task in
the first non-empty the ready list
bucket Inserting a task requires
0 finding the appropriate
priority bucket
0 1 1 0 1…
…
1
1
Step 2: multiple priority queue
0 ready list (extraction O(m)
insertion O(1)) where m is the
11111…
…11 1 number of priorities
Address of bucket 0
Implementation of fixed priority
0000h
1013h d1-
d1-d2 = 43F2h-
43F2h-2148h = 22AA > 0
d2 d2 d1>d2
2148h
43F2h
d1
A01Fh
d1-
d1-d2 = A01Fh-
A01Fh-1013h = 900C < 0
d1
d1<d2
8000h
Implementation of Earliest Deadline First
• Overload conditions
• EDF can give rise to a cascade of deadline miss
– There is no guarantee on which is the task that will miss its
deadline
– (see also problems with determination of worst case
completion time)
• Try the case
– C1=1 T1=4
– C2=2 T2=6
– C3=2 T3=8
– C4=3 T4=10
(utilization =106%)
Overload in FP scheduling
• Overload conditions
• Misconception: In FP the lowest priority tasks are the
first to miss the deadline
• Counterexample: start from the set (2,4) (2,6) fully
utilizing the processor
Task Synchronization
• So far, we considered independent tasks
• However, tasks do interact: semaphores, locks,
monitors, rendezvous etc.
• shared data, use of non-preemptable resources
• This jeopardizes systems ability to meet timing
constraints
• e.g. may lead to an indefinite period of priority inversion where
a high priority task is prevented from executing by a low priority
task
Optimality and Ulub
• When there are shared resources ...
– The RM priority assignment is no more optimal. As a matter
of fact, there is no optimal priority assignment (NP-complete
problem [Mok])
– The least upper bound on processor utilization can be
arbitrarily low
• It is possible (and quite easy as a matter of fact) to build a
sample task set which is not schedulable in spite of a utilization
U→0
Key concepts
• Task
– Encapsulating the execution thread
– Scheduling unit
– Each task implements an active object
• Protected Objects
– Encapsulating shared information (Resources)
– The execution of operations on protected objects is mutually
exclusive
Response time of a real-time thread
• Execution time
– time spent executing the task (alone)
• Execution of non schedulable entities
– Interrupt Handlers
• Scheduling interference
– Time spent executing higher priority jobs
• Blocking time
– Time spent executing lower priority tasks
• Because of shared resources
P B
MY TASK
S1
τ low
τ highest
Lock tried (S1)
τ high
s1
τ medium
τ low
s1 s1 s1
τ high
s1
τ medium
Ready
τ low
s1 s1 s1
R4 R3 R2
τ1
R2 B R2
τ2
priority
B
R3 R3
τ3
R4 R4
τ4
Priority Inheritance Protocol
• Disadvantages
• Tasks may block multiple times
• Worst case behavior (CS not nested) even worse
than non-preemptable CS
• Costly implementation except for very simple cases
• Does not even prevent deadlock (nested CS)
Priority Ceiling Protocol
• priority ceiling of a resource S = maximum priority among all tasks
that can possibly access S
• A process can only lock a resource if its dynamic priority is higher
than the ceiling of any currently locked resource (excluding any that it
has already locked itself).
• If task τ blocks, the task holding the lock on the blocking resource
inherits its priority
• Two forms
– Original ceiling priority protocol (OCPP)
– Immediate ceiling priority protocol (ICPP, similar to Stack Resource
Policy SRP)
• Properties (on single processor systems)
– A high priority process can be blocked at most once during its execution
by lower priority processes
– Deadlocks are prevented
– Transitive blocking is prevented
Deadlock (prevention)
• Conditions for deadlock (Coffman 71)
1. Mutual exclusion : a resource cannot be used by more than one
process at a time
2. Hold and wait : processes already holding resources may request
new resources
3. No preemption: No resource can be forcebly removed from a
process holding it, Resources can be released only by the explicit
action of the process
4. Circular wait: two or more processes form a circular chain where
each process waits for a resource that the next process in the
chain holds
• Deadlock only occurs when all of the previous four hold true
PCP
PCPprevents
preventscircular
circularwaits!
waits!
Example of OCPP
τ 1
R2 ceiling R2 = 1
τ 2
R3 ceiling R3 = 1
τ 3 R4 ceiling R4 = 1
τ 4
wait (R4) wait (R3) wait (R2)
R4 R3 R2
τ 1 wait (R2)
R2
τ 2 wait (R3)
priority
B
R3
τ3
R4
τ 4 R4
Immediate Priority Ceiling Protocol
• High and low priority task share a
τ high
critical section
S1
• Ceiling priority of CS = Highest priority
τ low among all tasks that can use CS
• CS is executed at ceiling priority
τ highest
Ready
τ high
s1
τ medium
Ready
τ low
s1 s1
τ 1
R4 R3 R2
τ1
ready
R2
τ2
priority
ready B
R3
τ3
R4
τ4
OCPP vs. ICPP
• Worst case behavior identical from a scheduling point of view
• ICCP is easier to implement than the original (OCPP) as
blocking relationships need not be monitored
• ICPP leads to less context switches as blocking is prior to first
execution
• ICPP requires more priority movements as this happens with all
resource usages; OCPP only changes priority if an actual block
has occurred.
Response time analysis
Response
time
Computation
Preemption from
time
higher priority tasks
PC IPC
Response Time Calculations & Blocking (contd.)
PI
PC IPC
• An example ...
R1 R2 R3 BPIP BPCP
τ1 20 5 5
τ2 5 10 20 10
τ3 5 5 18 10
τ4 5 13 10
τ5 10 3
Example: Shared resources
ES • Task
– 5 Tasks
• Shared resources
IS
– Results buffer
• Used by R1 and R2
T1 • R1 (2 ms) R2 (20 ms)
R1 C1 – Communication buffer
• Used by C1 and C3
write()
Br write() • C1 (10 ms) C3 (10 ms)
write_2()
T2
R2
read() Bc
T3
C3
Example: Shared Resources
Mission started on
November th
16 1996 and
finished on September 27th
1997.
The Mars Pathfinder Case
cruiser / lander (fixed) hosting the navigation and microrover (mobile) hosting :
landing functionality and the subsystems :
• ASI/MET for sensing meteorological • APXS : X-ray spectrometer
atmospheric data • Image acquisition devices
• IMP for image acquisition
System architecture
VME bus
1553 bus
CPU
ASI/MET
BUS 1553
• Cyclic Scheduler @ 8 Hz
• The 1553 is controlled by two tasks:
– Bus Scheduler: bc_sched computes the bus schedule for the
next cycle by planning transactions on the bus (highest priority)
– Bus distribution: bc_dist collects the data transmitted on the bus
and distributes them to the interested parties (third priority level)
– A task controoling entry and landing is second level, there are
other tasks and idle time
• bc_sched must complete before the end of the cycle to setup the
transmission sequence for the upcoming cycle.
– In reality bc_sched and bc_dist must not overlap
bc_sched
priority
bc_dist
other tasks
active bus
t1 t2 t3 t4 t5 0.125 ms
What happened
IPC
switched communication
buffer (pipe)
Priority
others
lock
ASI/MET
0 t1 t2 t3 t4 t5 0.125 s
• ASI/MET acquires control of the bus (shared resource)
• Preemption of bc_dist
• Lock attempted on the resource
• bc_sched is activated, bc_dist is in execution after the deadline
• bc_sched detects the timing error of bc_dist and resets the system
The Solution
• After debugging on the pathfinder replica at JPL,
engineers discover the cause of malfunctioning as a
priority inversion problem.
• Priority Inheritance was disabled on pipe semaphores
• The problem did not show up during testing, since the
schedule was never tested using the final version of
the software (where medium priority tasks had higher
load)
• The on-board software was updated from earth and
semaphore parameters (global variables in the
selectLib()) were changed
• The system was tested for possible consequences on
system performance or other possible anomalies but
everything was OK
Pathfinder with PIP
bc_sched
blocked end
bc_dist
Priority
others
lock unlock
ASI/MET
0 t1 t2 t3 t4 t5 0.125 s
• Except for very simple (but long) CS, PIP does not provide
performances better then other solutions (non preemptive CS or
PCP)
• PIP has a costly implementation, overheads include:
– Managing the basic priority inheritance mechanism not only
requires updating the priority of the task in CS, but handling
a complex data structure (not simply a stack) for storing the
set of priorities inherited by each task (one list for each task
and one for each mutex)
• Dynamic priority management implies dynamic reordering
of the task lists
completion time=13
Operating Systems background
• Releasing precedence constraints
completion time=16