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  • m2 Esem Eln. Num. Av. Vhdlfpga

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    19 views6 pages

    m2 Esem Eln. Num. Av. Vhdlfpga

    Uploaded by

    Hichem Hamdi
    mm

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    of 6
    Université M’hamed Boudhiaf M’sila ' Master 14 /S1/2019-2020 Faculté de Technologie Options : ESEM + STLC Département d’ électronique Le 26 / 01/2020 Examen : Electronique Numérique Avancée : FPGA + VHDL Exereice 1 : Réaliser les deux fonctions suivantes aveo U0 cireuit PAL qui posséde 3 variables @onirées, et deux termes OU avee chaque terme OU comporte 4 termes ET? 5 Fi(a,b,c) = abc ab.e + Fi@b,c) = abet Tbe Exereice 2 : Réaliser un additionneur complet avec un PAL? Exercice3: Soit le code VHDL suivant : library IEEE; use IEEE.std_logic_1164.alls entity exo_sis port (A, B, C: in std_logics Qi, Q2 : out std_logic); end exo_t architecture synth of exo_tis signal V, R: std_logic; pees CV, ©) _ parle Blake end process; R<=BxorC; : Flee process(A) - = _ g@oreLes p F&e begin if (A'event and A='s') then Qi<=C V<=R; end if; end process; end synth; a) Dessiner le systéme représenté par ce code. +) Compléter le diagramme des temps de la figure 1. Figure 4 Exercice 4: Ecrire le code VHDL structurel du circuit suivant : Comite ene QW) E btiowque Mucmsrten st Avancee ; FPG A+VApe. Most. 4 ESE M + STLC. Exerceice 4? b ¢ ‘BK: are eng By Rag ie Ad yoke) CK 2 AOS iss pares std Leste) cide oe aw 40 c xa ta Hee pels Sy wm Sy ~ eee Fronien BF Li “Libram ae Ace 5 w& we seee. etd_ “bag. AGL, bb Evita exe%, 4s yerk (Goce 5 an stl foyse wad Exo be * as

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