SISTEMAS DIGITALES 1

DESAFÍO
Nombre: Brayan Patricio Cepeda Leon

Se plantea la solución con código modularizado

//primera parte

library IEEE
use ieee.std_logic_1164.all;

use ieee.numeric_std.all;
use ieee.std_logic_textio.all;

use ieee.std_logic_unsigned.all;

entity multiplexor is
port(A : in std_logic_vector(2 downto 0);
 E: in std_logic_vector(1 downto 0);

F: out std_logic_vector(2 downto 0));

end multiplexor;

architecture arch_multiplexor of multiplexor is

begin
with E select

f<= (others => '0')when "00",A when "01", not A when "10",
(others => '1')when "11",(others=> '0')when others;

end arch_multiplexor;

//segunda parte
library IEEE

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use ieee.std_logic_textio.all;
use ieee.std_logic_unsigned.all;

entity binsum is

port (a,b: in std_logic_vector(2 downto 0);

car_in: in std_logic;
car_out: out std_logic);
out_binsum: out std_logic_vector (2 downto 0);

end binsum;

architecture arch_binsum of binsum is

signal aux_v: std_logic_vector (3 downto 0);

begin

aux_v <= ('0'& a)+('0'& b)+car_in;

car_out <= aux_v(3);

out_bitsum <= aux_v (2 downto 0);

end arch_binsum;

//tercera parte

library IEEE
use ieee.std_logic_1164.all;

use ieee.numeric_std.all;
use ieee.std_logic_textio.all;

use ieee.std_logic_unsigned.all;

entity suma_resta is
port(a,b: in std_logic_vector (2 downto 0);

enab: in std_logic_vector (1 downto 0);

car_in: in std_logic;

car_out: std_logic);
out_binsum: out std_logic_vector (2 downto 0);

end suma_resta;

architecture arch_suma_resta of suma_resta is

signal out_multiplexor: std_logic_vector(2 downto 0);
begin
u1: entity work.multiplexor(arch_multiplexor) port map (enab, b,
out_multiplexor);
u2: entity work.binsum(arch_binsum) port map (a, out_multiplexor, car_in,
out_binsum,car_out);
end arch_suma_resta;