library ieee;

use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity rom8x4 is
port (adresa : in std_logic_vector (2 downto 0);
cs_rom: in std_logic;
iesire : out std_logic_vector (3 downto 0));
end entity rom8x4;

architecture logica_rom8x4 of rom8x4 is

type matrice is array (0 to 7) of

std_logic_vector(3 downto 0);
constant m : matrice := ("1111","1100", "0011", "1010", "0101", "0000",
"1110","0111" );
begin
process(adresa,cs_rom)
begin
if(cs_rom='1') then
if(adresa="000") then
iesire<=m(0);
elsif(adresa="001") then
iesire<=m(1);
elsif(adresa="010") then
iesire<=m(2);
elsif(adresa="011") then
iesire<=m(3);
elsif(adresa="100") then
iesire<=m(4);
elsif(adresa="101") then
iesire<=m(5);
elsif(adresa="110") then
iesire<=m(6);
elsif(adresa="111") then
iesire<=m(7);
end if;
else
iesire<="XXXX";
end if;
end process;
end architecture;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity registru is
port(intrare: in std_logic_vector(2 downto 0);
mod_r: in std_logic;
iesire: out std_logic_vector(2 downto 0));
end entity;

architecture logica_registru of registru is

begin
process(intrare,mod_r)
variable inside: std_logic_vector(2 downto 0);
begin
if(mod_r='0') then
 inside:=intrare;
else
iesire<=inside;
end if;
end process;
end architecture;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity simulare is
port(intrare1: in std_logic_vector(2 downto 0);
mod_r1: in std_logic;
iesire1: out std_logic_vector(3 downto 0));
end entity;

architecture simulare1 of simulare is

component rom8x4 is
port (adresa : in std_logic_vector (2 downto 0);
cs_rom: in std_logic;
iesire : out std_logic_vector (3 downto 0));
end component rom8x4;

component registru is
port(intrare: in std_logic_vector(2 downto 0);
mod_r: in std_logic;
iesire: out std_logic_vector(2 downto 0));
end component;

signal iesire_r: std_logic_vector(2 downto 0);

signal cs_rom1: std_logic;
begin
cs_rom1<='1';
p1:registru port map(intrare1,mod_r1,iesire_r);
p2:rom8x4 port map(iesire_r,cs_rom1,iesire1);
end architecture;