2018 China International Conference on Electricity Distribution
2018
Development of a FPGA-based Protective Relay
in Active Distribution Networks
Weicong Gao1* , Yiqing Liu2, Guobin Chen2, Qifan Yang2
1. School of Information Engineering, Shandong Weihai University of Foreign Affairs
(*Corresponding author)
2. School of Electrical Engineering, University of Jinan
 Protective relay is the first defense against emergency
Abstract—Integration of distributed electric resources in
distribution network brings many challenges in protection. In this
paper, we develop a FPGA-based protective relay suitable for
active distribution networks. The overall scheme design and
implementation details of the relay are described. The relay is
implemented on Xilinx Spartan-6 FPGA programmed in Verilog
HDL. To enhance real-time, FPGA parallel processes SV and
GOOSE conforming to IEC61850 standard, with which the relay
will become smarter to meet the requirement of active
distribution networks. The relay simultaneously realizes such
functions by FPGA: analog-to-digital converting, digital filter and
voltage & current measurement, communication and protection
functions. The effectiveness of the proposed design is verified by a
closed-loop test method. Compared to DSP-based protective relay,
the proposed design is a more cost-effective solution.
Index Terms—FPGA; protective relay; IEC61850; SV;
GOOSE; active distribution networks
I. INTRODUCTION
D ISTRIBUTED electric resources (DERs) have been used
increasingly on a worldwide scale to deal with the fossil
fuel depletion. DERs are usually connected to the distribution
networks. This situation will turn the traditional distribution
network into a grid with multi power supplies, namely active
distribution network. Integration of various DER in distribution
network brings many challenges in reactive power regulation,
power quality, especially in protection [1].
Manuscript received July 10, 2018.This work was supported in part by the
Shandong Provincial Natural Science Foundation, China, under Grant
ZR2018MEE039.
W. Gao is with the School of Information Engineering, Shandong Weihai
University of Foreign Affairs, Weihai , China (e-mail: my_pikaqu@163.com).
Y. Liu is with the School of Electrical Engineering, University of Jinan,
Jinan 250022, China (e-mail: cse_liuyq@ujn.edu.cn).
G. Chen is with the School of Electrical Engineering, University of Jinan,
Jinan 250022, China (e-mail: 18366101539@163.com).
Q. Yang is with the School of Electrical Engineering, University of Jinan,
Jinan 250022, China (e-mail: yang7f@163.com).
CICED2018 Paper No. 201803260000004
978-1-5386-6775-0/18/$31.00 ©2018 IEEE
Tianjin, 17-19 Sep.
conditions of the distribution network. Nowadays, protective
relays usually are made by microcontroller or digital signal
processor [2]. The relays of such design are commonly used in
the high-voltage transmission grid. However, this is not an
economical choice in consideration of large amount of relays in
active distribution network [3]. In addition, traditional
protective relays are difficult to cope with the special situation
of the active distribution network.
In order to solve the problem of protection in active
distribution network, scholars have studied in depth from the
following two aspects. On the one hand, IEC61850 standards
are employed to improve the interoperability of relays and
share information between relays [4, 5]. On the other hand,
reducing the cost and the size of relays in the distribution
network is researched widely for engineering application [6].
In this study, field programmable gate array (FPGA) may be
a great substitute for digital signal processors and other
microcontroller unit [7, 8], because FPGA possesses a better
degree of parallelism and lower cost [9]. More important is that
only FPGA can be competent to hand SV and GOOSE that
conforms to IEC61850 standards and requires hard real-time
performance [10].
FPGA-based digital current and voltage relays have been
successfully developed for traditional power grid [11, 12], and
experiments in these references have verified that employing
FPGA is an optimal scheme.
In this paper, we develop a FPGA-based protective relay in
active distribution networks, which is realized by XILINX
Spartan-6 FPGA. The relay can perform the following
functions: data acquisition with SV and GOOSE,
analog-to-digital converting, digital filter and voltage & current
measurement, communication and protection functions. The
structure is organized as follows. Section II presents the overall
scheme design of the relay. Section III describes the
implementation details of the relay. Section IV carries test
cases and Section V concludes the paper.
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II. OVERALL SCHEME DESIGN
Field programmable gate arrays are comprised of
configurable logic blocks, input & output blocks and their
interconnection. This unique architecture offered by FPGA will
be useful in the development of protective relay. Among them,
In next section, the implementation of every module in
FPGA-based relay shown in Fig. 2 is described in detail.
Start
Algorithmic Description

the most advantage is parallel processing, namely FPGA can

create a pipelined architecture where analog-to-digital Programmed by Verilog HDL

converting, current & voltage calculation, and communication

can be implemented parallel in independent pipelines. Synthesis & function simulation

Parallel processing of FPGA can help developers to design

N
comprehensive functions. Realizing the same functions with Function correct?
microcontroller or DSP would require a more complicated and Y
expensive system due to their sequential characteristic.
In this paper, we select a Spartan-6 series FPGA - Placement on chip

XC6SLX45T made by XILINX Company. Spartan-6 FPGA N

Y
features sum as follows: Need to modify N Timing sequence
meeting requirements?
the design?
 Designed for low cost and optimized selection of I/O
Y
standards Y
 Low static and dynamic power Configuration on chip

 High-performance arithmetic and signal processing,

fast 18 x 18 multiplier and 48-bit accumulator, Finish
pipelining and cascading capability and pre-adder to Fig. 1. FPGA design flowchart.
assist filter applications
 Integrated memory controller blocks for DDR, DDR2,
DDR3 and LPDDR support with data rates up to 800 XC6SLX45T
Mb/s (12.8 Gb/s peak bandwidth) Parameter Setting Pipeline Controller
The flowchart of design in a universal FPGA-based system is
shown in Fig. 1. Firstly, the design requirements are determined Functions of Protective Relay & Monitoring Interface
and a high-level algorithmic description should be created.
After simulating the description, a digital circuit will be Voltage&Current
Calculation
synthesized at the gate level. Subsequently, placement and SV GOOSE
A/D
Controller
Binary
I/O
routing are implemented on the chip. Finally, timing sequence Digital Filter
should be verified. Once all steps are achieved, the actual
Communication Interfaces Analog Interfaces
functions on the chip can be tested.
The overall scheme design of the FPGA-based protective
Fig. 2. Function diagram of FPGA-based protective relay.
relay is shown in Fig. 2. The scheme consists of three parts: 1)
management module; 2) core function modules; 3) external III. IMPLEMENTATION OF PROTECTIVE RELAY
interfaces.
The management module is used to receive and check the A. Data Acquisition with SV and GOOSE
parameters that ensure the relay working normal, and manage Relays in active distribution networks should follow the
the pipeline of FPGA. IEC61850 standards; hence, the sampled values (SV) and
The second subsystem is a function module, which is the generic object oriented substation events (GOOSE) are used to
core of the relay. That is composed of protection module, exchange information between different devices. SV and
monitoring interface, analog-to-digital converter, binary GOOSE are transmitted through Ethernet. Due to their superior
input-output, IEC61850 SV and GOOSE processing module, real-time and reliability requirement, they must be directly
voltage & current calculation module and digital filters. mapped to MAC (media access control).
The external interface module is the last but important A finite state machine for Ethernet frame unpacking is
subsystem, which is the critical path for data transmission. To shown in Fig. 3. When it receives an Ethernet frame, FPGA will
cope with various data sources, the module provides two distinguish SV from other frames by the Ethertype field. The
interfaces: one is Ethernet communication interface for Ethetype of SV frame is equal to 0x88 BA and the Ethetype of
IEC61850 SV and GOOSE receiving; the other is analog GOOSE frame is equal to 0x88 B8. Other frames except SV
interfaces for AC and binary input.

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 2018 China International Conference on Electricity Distribution Tianjin, 17-19 Sep. 2018

and GOOSE will be filtered, which is used to resist network The connection between AD7606 and FPGA is shown in Fig.
storm caused by broadcast or abnormal conditions. 4. At the /convst_A and / convst_B, FPGA injects a
low-voltage level of 500 ns, the converter will start conversion
RXD
V=0
and save the digital results into the output buffer. After 45 ns
delays, the digital results are available, and the FPGA can read
1

Idle
e=
m
ra

the results from the data-bus. Finishing the whole processing

_f
AC

Write
M

FIFO requires about 5 us.

AD7606 XC6SLX45T

=1
OK
Preamble DB[0:15] FIFO

C_
Start
check

CR
CRC
/convst_A
RX Unpcak
DV /convst_B Controller with
=1 frame D
=0x5 /busy Finite State
RXD
/RD Machine
Fig. 3. Finite state machine for Ethernet frame unpacking. /CS

The field of smpSynch in an IEC 61850-9-2 frame is CLK

designed to synchronize sampled values from different devices.
Fig. 4. Block diagram of the connection between ADC and FPGA.
When smpSynch is equal to TRUE, it means that the sampled
values contained in SV frame are already synchronized by GPS. C. Digital Filter and Voltage & Current Measurement
Otherwise, when smpSynch is not equal to TRUE, an internal In protective relay, digital filter or discrete Fourier transform
time-synchronization mechanism is needed. Hence, an (DFT) is commonly employed to calculate the amplitude and
additional function to SV & GOOSE processing module is data phase of voltage and current. We use Eq. (2) to substitute for
interpolation for time-synchronization. DFT, when only fundamental component is required for relay.
In this paper, we use the Lagrange interpolation method,  N 1
2 2 
because it is easier than other algorithms of interpolation and it  I real   x( k )   N sin k N  (2)
k 0  
has been used in digital relay for smart substation.  N 1
 2
 I imag   x( k )   cos k 2 
Lagrange interpolation algorithm uses a Lagrange 
 k 0 N N 
polynomial function, as shown in (1), to get a sampled value,
which does not exist in SV sequence, from adjacent sampled where N is the sampled number per one fundamental period;
values. Such interpolation results will be time-synchronized. x(k) is the k-th sampled value; Ireal and Iimag are the real and
imaginary part of the current respectively.
 n

 sk .con   siCi , n (tk ) The parallel structure of FPGA possesses a unique advantage
 i 0 (1) for the calculation of the digital filter, as shown in Fig. 5. The
 n  t t 
coefficients of a(0), a(1), …, a(n-1) are DFT factors in (2).
Ci , n (tk )   
k j

 j 0 
 ti t j  Different from serialization DSP, FPGA can filter the sampled
 j i
values almost instantaneously.
where sk .con is the sampled value interpolated at t k ; Ci , n (tk ) x (k )

is a coefficient of Lagrange interpolation polynomial; si is the a (n  1) a ( 2) a (1) a (0)

sampled value at ti ; ti , t j , tk are the given time respectively.
Z 1 Z 1 Z 1 Z 1 y(k )
B. Analog-to-Digital Conversion and its Controller
Fig. 5. Digital filter diagram in FPGA.
Since XC6SLX45T FPGA is not embedded with internal
analog-to-digital convert, to access AC voltage & current The time consuming of voltage and current calculation is
collection by the relay, an external analog-to-digital converter shown in Table I, which is tested in XC6SLX45T FPGA at
AD7606 from Analog Devices is used on the FPGA board. It is 33MHz clock. In the same table, time consuming of
a high-speed 8-channel ADC with 16-Bit, bipolar, TMS320C6713 DSP at 198MHz clock (written in C language)
simultaneous sampling. is also added for the purpose of comparison. The test results
An external adjustment circuit is added to suit the current & show that the time consuming of FPGA is much shorter than
voltage transformers, because AD7606 cannot sense any DSP, and does not change with N.
voltage larger than ±10 V. Inner FPGA, an ADC controller is
designed to adjust sampling time interval, start-up ADC and
read digital conversion results.

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 2018 China International Conference on Electricity Distribution Tianjin, 17-19 Sep. 2018

D. Communication Interfaces Moreover, the last is distance protection, which is applied to a

The FPGA in protective relay provides not only Ethernet
interface for IEC 61850 SV and GOOSE, but also other
communication interfaces, which is designed for exchanging
information with the display and management module.
TABLE I.
TIME CONSUMING OF DFT
N FPGA / μs DSP / μs
24 0.6 8.5
48 0.6 13.2
96 0.7 18.9
Although FPGA provides powerful computation and logical
capability, it is not equipped for display and human-machine
interaction. Hence, an additional module of human-machine
interaction (HMI) is designed with 16-bit ARM chip. FPGA
sends the display information to HMI through a cached serial
port, which is the essential communication interface of FPGA.
Another external interface is designed for higher speed
transmission, which employs multipoint low voltage
differential signaling (LVDS). Such higher speed interface
often provides service to other FPGA modules in the same
protective relay.
E. Functions of Protective Relay
Active distribution network consists of DERs, energy
storage devices and different loads. The requirement for
protection in active distribution network is quite different from
those in traditional distribution network with a single power
supply. Furthermore, several special protection elements need
to be configured. In this section, protective functions of
proposed relay are described in Table II concisely
TABLE II.
FUNCTIONS OF PROTECTIVE RELAY
Relay No. Function description
21 Distance protection
25 Synchronism-check function
27 Under-voltage protection
Island detection for grid-connected DER
50 Instantaneous over-current protection
51 Inverse-time over-current protection
67 Directional element
These functions can be divided into 3 categories. The first is
about over-current protection. Due to multiple power sources in
active distribution network, the directional element becomes a
necessity in order to ensure selectivity. The second category is
used for DER island detection and synchronism-check.
higher voltage level or longer distribution lines. All the
functions are realized by logic gates in FPGA.
IV. SIMULATION AND TEST CASES
To verify the effectiveness of the design scheme, we carried
out several simulation cases in XILINX integrated
development environment. The typical timing diagram when
simulating the ADC controller is illustrated in Fig. 6.
The simulation results are fully conformed to the
requirement mentioned in AD7607 datasheet. A large number
of practical tests also indicate that FPGA and AD7606 work
well in collaboration.
Fig. 6. FPGA simulation timing diagram.
Besides simulation, we used a closed-loop test method [13]
for prototype verifications, which uses ATP/EMTP to generate
transient fault waveform and playback the waveform by static
test device.
In this test case, one 10kV active distribution network with
photovoltaic, double-fed induction generator and other
distributed generations is shown in Fig 7(a). The active
distribution network is connected to the power grid by CB1,
and a fault with phase-A and phase-B occurs at k1 when 0.238 s.
The FPGA-based protective relay is installed at CB3.
The voltage and current waveforms during the fault are
recorded by a fault recorder; at the same time a trip message in
GOOSE sent by FPGA-based protective relay and the position
of CB3 are also recorded. The information above is illustrated
in Fig 7(b).
It can be concluded that instantaneous over-current in
FPGA-base relay sends out a trip command at 0.259 s, i.e.
0.021 s after the fault occurs. Considering a computational data
window with one fundamental period (0.020 s under 50 Hz),
the time-consuming of computation and logical judgment is
less than 1 ms. In general, this time interval in a DSP-based
relay is at least 4-5 ms.

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 2018 China International Conference on Electricity Distribution Tianjin, 17-19 Sep. 2018

V. CONCLUSIONS [4] Y. Q. Liu, H. L. Gao, W. C. Gao, and et al, “Development of a

FPGA-based systems will offer a cost-effective solution to
intelligent electronic devices in power systems. In this paper,
we develop a protective relay based on FPGA and its software,
which are appropriate for active distribution networks. The
design is implemented on Xilinx Spartan-6 XC6SLX45T
FPGA programmed in Verilog HDL. The relay employs such
functions: data acquisition with SV and GOOSE,
analog-to-digital converting, digital filter and voltage & current
measurement, communication and protection functions. The
proposed scheme with parallel working in FPGA can reduce the
process time effectively compared to sequential in a digital
signal processor. The test cases on closed-loop test system
show the FPGA-based relay is a better choice for active
distribution networks.
CB2 Load1
CB1
CB3 CB4
Grid
10kV
k1
(a)
10
Voltage / kV
Substation-Area Backup Protective Relay for Smart Substation,” IEEE
Transactions on Smart Grid, vol. 8, issue 6, pp. 2544-2553, 2017.
[5] S. Lim, “A service interruption free testing methodology for IEDs in IEC
61850-based substation automation systems,” International Journal of
Electrical Power & Energy Systems, vol. 87, May, pp. 65-76, 2017.
[6] S. Karn, A. Malkhandi, and T. Ghose, “Laboratory Prototype of a Phasor
Measurement Unit using FPGA based Controller,” International
Conference on Electrical, Electronics, and Optimization Techniques, pp.
2029-2034, Chennai, India, 2016.
[7] M. Matar, and R. Iravani, “The Reconfigurable-Hardware Real-Time and
Faster-Than-Real-Time Simulator for the Analysis of Electromagnetic
Transients in Power Systems,” IEEE Transactions on Power Delivery, vol.
28, issue 2, pp. 619-627, 2013.
[8] D. Chengdi, L. Peng, W. Chengshan, and et al, “A Design and
Implementation of FPGA-Based Real-time Simulator for Distribution
System with DG Integration,” China International Conference on
Electricity Distribution, Xi’an, China, pp. 1-6, 2016.
[9] Y. C. Lin, G. Y. Lin, and Y. H. Lin, “Development of a FPGA-Based
Contactless Pulse Rate Detection System,” 2nd International Conference
on Intelligent Green Building and Smart Grid, Prague, Czech Republic, pp.
1-5, 2016.
[10] S. Ramadhan, F. I. Hariadi, and A. S. Ahmad, “FPGA Based Hardware
Implementation of Fault Detection for Microgrid Applications,”
CB5 CB6
International Symposium on Electronics and Smart Devices, Yogyakarta,
Load2
Indonesia, pp. 154-157, 2017.
[11] V. Maheshwari, B. D. Devulapalli, and A. K. Saxena, “FPGA-based
DER1 DER2
Digital Overcurrent Relay With Concurrent Sense-process-communicate
Cycles,” International Journal of Electrical Power & Energy Systems, vol.
55, issue 2, pp. 66-73, 2014.
[12] B. S. Venkateshmurthy, and Dr. K. R. Nataraj, “Design and
Implementation of High Speed FPGA for Under & Over Voltage

5
0
Protective Relay,” International Conference on Recent Advances in
Electronics and Communication Technology, pp. 76-80, Bangalore, India,
-5
2017.
-10
A B C
[13] Y. Q. Liu, H. L. Gao, X. Wei and et al, “Performance Testing of Complete
20 A Digital Relays Based on ATP-EMTP and IEC61850-9-2,” 4th
International Conference on Electric Utility Deregulation and
10
Restructuring and Power Technologies , pp.83-87, Weihai, China, 2011.
Current / kA

-10 Weicong Gao was born in Hebei Province, China. She received the B.S. degree
B in computer engineering from Tianjin University, Tianjin, China, in 2000, and
-20 the M.S. degree in electronics and communication engineering from Shandong
1 University, Jinan, China, in 2012. She is the corresponding author of this
Trip

0 paper.She is currently an Associate Professor with the School of Information

Engineering, Shandong Weihai University of Foreign Affairs. Her current
1 research interests include embedded systems and computer applications.
CB3

0
0.220 0.240 0.260 0.280 0.300 0.320 0.340
Time / s Yiqing Liu received the Ph.D. degree in electrical engineering from Shandong
University, Jinan, China, in 2012. He is currently an Associate Professor with
(b) the School of Electrical Engineering, University of Jinan, Jinan, China.
Fig. 7. (a) 10kV active distribution network; (b) Recording waveforms of
protective relay during fault. Guobin Chen received the B.S. degree from the School of Electrical
Engineering, University of Jinan, Jinan, China, in 2016. He is currently a
graduate student in University of Jinan, Jinan, China. His main research interest
is relay protection.
REFERENCES
[1] Y. Seyedi, and H. Karimi, “Coordinated Protection and Control Based on Qifan Yang graduated from Shandong Electric Power Junior College, Jinan,
Synchrophasor Data Processing in Smart Distribution Networks,” IEEE China, in 2012. He currently is a graduate student in University of Jinan, Jinan,
Transactions on Power Systems, vol. 33, issue 1, pp. 634-645, 2018. China. His main research interest is relay protection.
[2] J. H. He, Z. Q. Wang, Q. F. Zhang and et al, “Distributed Protection for
Smart Substations Based on Multiple Overlapping Units,” CSEE Journal
of Power and Energy Systems, vol. 2, no. 4, pp. 44-50, 2016.
[3] Q. Huang, S. Jing, J. Li, and et al, “Smart Substation: State of the Art and
Future Development,” IEEE Transactions on Power Delivery, vol. 32,
issue 2, pp. 1098-1105, 2017.

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