Name: ANGIRA GHOSH

ROLL NO: 1954022

COMPUTER ORGANIZATION AND ARCHITECTURE LAB,
INFO2253
IT, 2ND YEAR (ASSIGNMENT 4)

1. Understanding behaviour of associative cache from working

module.
2. Associative cache with one word, 2 bit memory address, 2 bit data
without replacement policy.

Truth table:-
3 BIT AND:-
INPUTS OUTPUTS
A B C
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
 1 1 1 1

SR flip flop:-
INPUTS OUTPUTS STATE
CLK S R Q
X 0 0 No Change Previous
1 0 1 0 Reset
1 1 0 0 Set
1 1 1 - Forbidden

OR:-
INPUTS OUTPUTS
A B
0 0 0
0 1 1
1 0 1
1 1 1

Comparator:-
INPUTS OUTPUTS(A=B)
A B
0 0 1
0 1 0
1 0 0
1 1 1