Level-shifted PWM for Cascaded Multilevel

Inverters with Even Power Distribution

Mauricio Angulo† , Pablo Lezana† , Samir Kouro† , José Rodrı́guez† and Bin Wu‡

†
Electronics Engineering Department
Universidad Técnica Federico Santa Marı́a
Av. España 1680, Casilla 110-V, Valparaı́so, CHILE
E-mail: samir.kouro@ieee.org
‡
Department of Electrical and Computer Engineering
Ryerson University
350 Victoria Street, Toronto, Ontario M5B 2K3, Canada

Abstract— Cascaded H-bridge multilevel inverters are com-
monly controlled using multicarrier Phase-Shifted PWM, since
it allows an even power distribution among the converter power
cells, which can lead to lower harmonic distortion in the input
current if an adequate transformer is used. However it is known
that other multicarrier methods, like Phase Disposition PWM (PD-
PWM) have better output voltage quality with lower distortion.
Nevertheless, when used with cascaded inverters, this method
produces uneven usage of the converter cells, that disables the har-
monic cancelations at the transformer input. This paper presents a
modified PD-PWM technique, that combines the benefits of both
modulation methods, achieving good output voltage and input
current quality.
I. I NTRODUCTION
Multilevel inverters are mainly devised for high power ap-
plications, due to higher voltage operating capability, lower
dv/dts and more sinusoidal outputs [1]–[4]. The Neutral Point
Clamped [5]–[7], Flying Capacitor [8]–[10] and the Cascaded
H-bridge inverter [11]–[13], are the most studied and com-
mercialized topologies. The Cascaded H-Bridge, also known
as multicell converter, has been particularly used in very high
power applications (over 4[KV] and several MW), due to its
modularity and attractive input current harmonics cancellation
[14].
Multilevel converters are mainly controlled with sinusoidal
PWM extended to multiple carrier arrangements of two types:
Level Shifted (LS-PWM), which includes Phase Disposition
(PD-PWM), Phase Opposition Disposition (POD-PWM)and
Alternative Phase Opposition Disposition (APOD-PWM) [15],
or they can be Phase Shifted (PS-PWM) [16].
Phase Shifted PWM is mainly conceived for multicell topolo-
gies, since each carrier can be related to a particular and
independent power cell. A proper phase shift is introduced
among the carriers in order to produce the typical multilevel
stepped waveform. For this reason, all the power cells operate
under the same switching conditions and therefore present
an even power distribution. In addition, when using an input
transformer with appropriate angle shifts between the windings,
some low order input current harmonics can be cancelled [14],
which is a very attractive feature for high power applications.
However, since the carrier signals are not synchronised, the
output line-line and load voltages have some additional dv/dts
that are not produced with Level Shifted methods where all the
carriers are in phase. This leads to a higher voltage distortion
[16].
On the other hand, Level Shifted methods are based on
amplitude shifts between carriers. Each carrier is associated to
a specific voltage level. When the reference is over one carrier,
the corresponding level is generated. Therefore, when LS-PWM
is used with cascaded H-bridge inverters, the cells will be used
only when the corresponding level is reached, producing a
uneven power distribution and switching conditions between the
cells. This will avoid the current harmonic cancellation at the
input, and increase the input current distortion. These harmonics
can be important due to the amount of power involved in high
power applications, making it more difficult to meet standards.
In this paper, a simple and effective modification is
introduced to PD-PWM or LS-PWM that rotates every
modulation cycle the carrier signals between the converter
cells. This imposes an even power distribution among the cells.
Therefore the proposed method achieves the same switching
pattern at the inverter output as with PD-PWM, and the same
input current harmonics cancellation obtained when operating
with PS-PWM. Results are shown for a 5 level inverter.
II. T HE C ASCADED H-B RIDGE I NVERTER
A. Topology description
The Cascaded H-Bridge multilevel inverter (CHB) is com-
posed by the series connection of H-bridge power cells. For
this reason, the CHB is also known as a multicell inverter.
Each cell includes a single phase three-level H-bridge inverter,
a capacitive dc-link, a rectifier and an independent or isolated
voltage source provided by transformer secondaries or batteries.
Usually the rectifier consists of a three phase diode full bridge
rectifier as shown in Fig. 1.

1-4244-0655-2/07/$20.00©2007 IEEE 2373

 TABLE I
Rectifier dc-link Inverter
F IVE LEVEL CASCADED INVERTER SWITCHING STATES .
N
S11 S12 Output Voltage Cell 1 Cell 2
va1 vaN S11 S12 va1 S22 S22 va2
Cell Cell
Vdc b1 c1 2Vdc 1 0 Vdc 1 0 Vdc
Vdc 1 0 Vdc 0 0 0
S11 S12 1 0 Vdc 1 1 0
0 0 0 1 0 Vdc
Cell a1 1 1 0 1 0 Vdc
Cell Cell Cell 0 0 0 0 0 0 0
a2 b2 c2 0 0 0 1 1 0
1 1 0 0 0 0
1 1 0 1 1 0
vaN 1 0 Vdc 0 1 −Vdc
0 1 −Vdc 1 0 Vdc
Cell Cell Cell −Vdc 0 1 −Vdc 1 1 0
am bm cm 0 1 −Vdc 0 0 0
0 0 0 0 1 −Vdc
a c 1 1 0 0 1 −Vdc
b
vab −2Vdc 0 1 −Vdc 0 1 −Vdc
van
ia TABLE II
n C ASCADED H- BRIDGE RELATIONS PER CELL .

Fig. 1. Cascaded H-Bridge multilevel inverter power circuit n◦ of n◦ of Shifts in Current Output
cells levels secondaries pulses Voltage
3 7 20◦ 18 2.30[kV]
+ 4 9 15◦ 24 3.30[kV]
0° 5 11 12◦ 30 4.16[kV]
m 2m + 1 60◦ /m 6m —
Utility +
grid -15°
is
-30°
+ link voltage of each cell. The different output voltage levels
-45°
can be determined by replacing in (1) all the posible binary
+
combinations of the switching states of each cell, obtaining in
Transformer
this way the inverter switching table. An example for one phase
of a two-cell, five-level CHB inverter is presented in Table I.
By increasing the number of cells, the converter can naturally
Fig. 2. Multipulse diode rectifier: 24-pulse, for a 4-cell, 9-level cascaded reach higher voltages with the same power semiconductors.
inverter.
This modularity is specially useful for high power applications
(several kilovolts and megawatts). In addition by increasing
The transformer secondary windings are usually shifted in the number of cells the overall power quality of the converter
angle among the cells of each inverter leg, in order to operate improves, at the input and output. The first is because there
with the diode bridges as a multipulse rectifier. In this way are more diode rectifiers and therefore the multipulse rectifier
the input current presents reduced harmonic content. The angle produces a more sinusoidal current, and the latter since more
shifts of the windings will depend on the number of cells of the different output levels can be generated, reducing the output
inverter. Figure 2 shows the suitable configuration for a 9-level voltage distortion. Table II summarises the relation between
CHB inverter. the number of cells and the converter parameters.
At the inverter side, the switching state of cell k is determined
by the logical value of two signals (Sk1 , Sk2 ), which can be “1” B. Cascaded H-Bridge Inverter Modulation
and “0” representing the “on” and “off” state of each switch
Phase Shifted PWM (PS-PWM) is the natural PWM method
respectively. This leads to four different binary combinations
for CHB [14], mainly due to the modularity of this topology.
that generate three different output voltages +Vdc , 0 and −Vdc .
Each cell is modulated independently using unipolar PWM with
Since the cells are connected in series, the total inverter output
the same reference signal. A phase shift is introduced across all
voltage, of phase a for example, is given by
the carrier signals of each cell in order to produce the stepped


m

m
multilevel waveform. The lowest output voltage distortion is
vaN = vai = Vdc (Si1 − Si2 ), (1) achieved with a 180◦ /m phase shifts between the carriers, for
i=1 i=1
a m-cell inverter. This operating principle is illustrated for a
where m is the number of power cells and Vdc is the dc- 7-level example in Fig. 3.

2374
 vcr -vcr 1
1

Input current [pu]

is
0.5
Cell 3 Output
Voltage [pu]

0
0

-0.5
-1
-1 0 0.01 0.02 0.03 0.04 0.05 0.06
o
va1 Time [s]
60
(a)
1
100

Input current spectrum

[% of fundamental]
0.5
Cell 2 Output

80
Voltage [pu]

0 60

-0.5 40
11
20 13
-1
va2 0
0 500 1000 1500 2000 2500
60o
1 Frequency [Hz]

0.5 (b)
Cell 3 Output
Voltage [pu]

100

Input current spectrum

[% of fundamental]
0
80
-0.5 Vdc 60 5

-1 40
va3 20
7
11
13
3 v* 0
2 0 500 1000 1500 2000 2500
3Vdc
Inverter Output
Voltage [pu]

1 Frequency [Hz]
0 (c)
-1 vaN
-2
Fig. 4. Input current at the primary of the transformer: a) 12-pulse current
waveform, b) 12-pulse current spectrum, c) 6-pulse current spectrum.
-3

Fig. 3. Three cell (7-level) PS-PWM waveform generation.

Since all the cells are controlled with the same reference and
same carrier frequency, the power is evenly distributed among
the cells, achieving input current harmonic reduction thanks to
the multipulse transformer-rectifier system. Each diode rectifier
drives the same average power to the converter output, therefore
the input currents reflected on the primary of the transformer,
with the corresponding phase shift, cancel low order harmonics
[14]. The input current for a 12-pulse diode rectifier used in a 5-
level CHB inverter is shown in Fig. 4a, with the corresponding
current spectrum in Fig. 4b. Note that only the 11th and 13th
harmonics are present in comparison to the 6-pulse case shown
in Fig. 4c, where 5th and 7th harmonics are still present.
On the other hand, since the carrier signals are not in phase,
the output line-line voltage (vab ) and load voltage (van ) have
some additional dv/dts that are not produced with Level Shifted
methods, like PD-PWM, where all the carriers are in phase.
This leads to a higher and undesirable voltage distortion [16].
The problem with PD-PWM is that no even power is driven
through the different diode rectifiers, and hence the input
current harmonics are not cancelled, despite the multipulse
configuration and windings angle shifts.
III. P ROPOSED MODIFIED PD-PWM
A. Traditional PD-PWM
The operating principle of traditional PD-PWM is illustrated
in Fig. 5a for a 5 level inverter. The general rule is that m − 1
carriers are needed for a m inverter, in this case 4 carriers.
The two outer carriers (vcr1 and vcr4 ) are used to generate the
switching signals for one power cell, and the two inner carriers
(vcr2 and vcr3 ) are used for the other. The reference signal is
compared to the carrier arrangement using a simple comparison
logic as shown in Fig.6a for a five level case. From Fig. 5a
it can be clearly appreciated that the cell output voltages va1
and va2 have a completely different switching pattern, and that
the power delivered by both cells is also uneven. This will, as
mentioned earlier, avoid the input current harmonics mitigation
and produce undesirable distortion.
In order to eliminate the drawbacks of both modulation meth-
ods (distortion at input current with PD-PWM and distortion
at output voltage with PS-PWM), a simple modification can be
introduced to PD-PWM.
B. Modification to PD-PWM
The exposed problem can be easily solved, by simply alter-
nating the level shifts between the carriers associated to each
cell. In this way, each cell will be equally represented by its
carrier in the total amplitude range covered by the reference

2375
 v* v*
vcr1 v~cr1
vcr2 v~cr2
vcr3 v~cr3
vcr4 v~cr4

va1 va1
} Vdc } Vdc

va2 va2
} Vdc } Vdc

vaN vaN

} Vdc } Vdc
} Vdc } Vdc

(a) (b)

Fig. 5. Modulation operating principle: a) Traditional phase disposition PWM, b) Modified rotative phase disposition PWM.

vcr1 v~cr1 higher carrier frequencies (usually > 1kHz), the reference does
vcr2 v~cr2 not change much over one or two carrier cycles. Therefore the
vcr3 v~cr3 average switching frequency and the average power flow from
vcr4 v~cr4 the converter cells of each phase can be considered almost equal
over a couple of carrier cycles. Hence, the operation with the
multipulse rectifier and the windings angle shift will produce
v* +
v* +
the harmonic mitigation at the input current.
vcr1 S11 v~cr1 S11 In addition the total output voltage waveform (vaN = va1 +
_ vcr1 +
_
va2 ) is identical to the one obtained with PD-PWM, since the
same carrier arrangement is used, only the cells change their
+ +
S21 S21 switching pattern according to the carrier rotation, as shown in
vcr2 v~cr2 Fig 5.
_
vcr2 +
_
Figure 6b show the modified modulation diagram for a five
+ + level inverter. Note that only a slight modification is necessary
S22 S22
vcr3 _
vcr3 +
v~cr3 _ to perform the rotation of the carriers. By just adding a square
waveform with half the frequency of the carriers and the
+ + necessary amplitude to perform the offsets.
S12 S12
vcr4 _
vcr4 +
v~ cr4 _
For a more generalised approach considering more levels,
the carrier shifts have to be performed in a repeating sequence,
covering all the levels of the inverter. Hence the added square
(a) (b)
waveform has to be replaced by a stair waveform.
Fig. 6. Modulation control diagram: a) Traditional phase disposition PWM,
b) Modified rotative phase disposition PWM. IV. R ESULTS
The proposed method is tested by simulations, and results
are presented for a 5-level inverter in Fig. 7.
signal. This strategy is illustrated in Fig. 5b, note that carriers Both methods, PD-PWM and the rotative-PD-PWM are
are alternated each modulation cycle. It is worth to mention that presented to establish a comparison across Figs. 7a and 7b
the level rotations are performed separately between positive respectively. A zoom to the carrier signal arrangement is shown
and negative carriers. The carrier signals shown in Fig. 5 in Fig. 7a1 and 7b1. The carrier frequency is 2[kHz]. Note how
are illustrated with lower frequencies than a typical practical the modified PD-PWM has the proposed alternating sequence
implementation, only for illustrative purposes, to show more between the carriers. The effect of this enhancement can be
clearly the commutation pattern. However, when considering clearly appreciated in the output voltages of each cell (va1

2376
 2 2
1.5 1.5
1 1
Carrier Signals

Carrier Signals
0.5 0.5
0 0
Ŧ0.5 Ŧ0.5
Ŧ1 Ŧ1
Ŧ1.5 Ŧ1.5
Ŧ2 Ŧ2
0.1 0.1002 0.1004 0.1006 0.1008 0.101 0.1012 0.1014 0.1016 0.1018 0.1 0.1002 0.1004 0.1006 0.1008 0.101 0.1012 0.1014 0.1016 0.1018
Time [s] Time [s]
(a1) (b1)

200 200
Va1 Va1
100 100
Voltage [V]

Voltage [V]
0 0

Ŧ100 Ŧ100

Ŧ200 Ŧ200
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17

200 200
Va2 Va2
100 100
Voltage [V]

Voltage [V]
0 0

Ŧ100 Ŧ100

Ŧ200 Ŧ200
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17

500 500
V* V*
Voltage [V]

Voltage [V]

VaN VaN
0 0

Ŧ500 Ŧ500
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17
Time [s] Time [s]
(a2) (b2)
150 150
V
Voltage Spectrum

V aN
Voltage Spectrum

aN

100 100

50 50

0 0
0 1000 2000 3000 4000 5000 0 1000 2000 3000 4000 5000
Frequency [Hz] Frequency [Hz]

(a3) (b3)
10 10
Io Io

5 5
Current [A]

Current [A]

0 0

Ŧ5 Ŧ5

Ŧ10 Ŧ10
0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17
Time [s] Time [s]

(a4) (b4)

Fig. 7. a) Traditional phase disposition PWM and b) Modified rotative phase disposition PWM: 1) Carrier signals, 2) Output voltages (Cell a1 output voltage
va1 , Cell a2 output voltage va1 , and inverter phase a output voltage vaN ), 3) phase a output voltage spectrum, 4) Load current ia .

and va2 ) presented in Fig. 7b2, showing clearly how both
cells present a similar switching pattern in comparison to the
classic PD-PWM output voltages shown in Fig. 7a2. However
both total output voltages (vaN ) are very similar in shape and
present the same frequency spectrum, as can be appreciated in
Fig. 7a3 and b3. This means that the proposed modification
achieves the same output quality as PD-PWM, which is better
than the traditional PS-PWM used for cascaded inverters. Since
both output voltage have the same harmonic content, both load
current waveforms (ia ) appear also similar in shape. They are

2377

(a)
(b)
Fig. 8. Phase a input current (Isa ), waveform and spectrum: a) Traditional
phase disposition PWM, b) Modified rotative phase disposition PWM.
very sinusoidal, as expected, since the low pass nature of the
R−L load filters the high frequency components in the voltage,
which is centered around the carrier frequency at 2[kHz].
Finally, Fig. 8a shows the input current (isa ) and the respec-
tive spectrum, for phase a at the primary of the transformer for
PD-PWM. Note how the uneven power distribution between
the cells disables the low order harmonic mitigation. The 5t h
and 7t h components are not eliminated like normally happens
with a 12-pulse rectifier with PS-PWM as shown earlier in
Fig. 4b, looking more like a 6-pulse rectifier current as the one
presented in Fig. 4c. However this effect does appear in the
modified rotative PD-PWM shown in Fig. 8b, where the 5th
and 7th harmonics are eliminated. In fact the current spectrum
obtained with the rotative-PD-PWM is quite similar as the one
obtained for PS-PWM, with only 11th and 13th harmonics.
2378
V. C ONCLUSION
A modified PD-PWM method is presented for cascaded H-
bridge inverters. The proposed method combines for cascaded
H-bridges the high points of PD-PWM and PS-PWM, which
are high quality output voltages and input currents respectively.
While it overcomes the drawbacks, mainly the uneven power
distribution and switch usage between cells produced with
regular PD-PWM.
ACKNOWLEDGMENT
The authors gratefully acknowledge financial support pro-
vided by the Chilean National Fund of Scientific and Techno-
logical Development (FONDECYT), under grant No. 1060423,
and by the Industrial Electronics and Mechatronics Millenium
Science Nucleus of the Universidad Técnica Federico Santa
Marı́a.
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