National Semiconductor DM74S289 64-Bit (16 x 4) Open-Collector RAM TRI-STATE® RAM General Description Those 64tit actve-clament momores are monoitic Schottyciamped asistorransistr loge (TTL) arrays Ganized as 16 words of 4 bits each. They ae uly coded nd feakre a chp-enabieingut to simply decoding e- ured to achieve the. desred system orgrizaton. Tho ‘memories feture PNP input ransistor tht reduce the low tovel input curert requirement to maximum of 25 mA ‘only one-ighth tnt of @ OMS standard iad factor. Tho chp-enabe culty is implemented wih minal delay times to compensate for added aystom decoding ‘Wie Cyce: The complement of te information atthe data input is writen ito the selected tcaton when both the chp-enabe Input and the read/write nput are low. Whi the read/write input slow, the ouput aren th igh impedence. state. When a number of the DM74S209 Connection Diagram Dusl-in-Line Package irvA onan ‘mrt wen Top View Order Number DM748200V oF DM74S269N ‘See NS Package Number J16A or NIGE outputs are bus connected, this high-impedance state will neither load nor drive the bus line, but it will low the bus ead Cyole: The stored information (complement of infor- mation applied at the data inputs during the write cycle) is jablo at the outputs when the read/write input Is high ‘the chip-onable is low. When the chip-enable is high, the outputs willbe inthe high-impedance state. Features = Commercial address access timo 25 ns ‘= Features opon-collector output ‘© Compatible with most TTL circuits '& Chip-enable input simpiities system decoding Truth Table i runction | onp- [Read] outut | nab | wee Woe oun] & | t [Hoimpeains Read L H_| Stored Data tnt |x | Hihmpedence = Fgh Laval = Low Level X = Dat Cae Sat egzSbZNdDM74S289 Absolute Maximum Ratings (nots 1) Operating Conditions It itary/Aerospace specified devices are required, Min = Max Unite please contact the National Semiconductor Sales ‘Supply Voltage (Voc) ‘Office/Distributors for availablity and specifications. DM74S289 475 6250 Supply Voltage, Voc Tov Temperature (Tx) Input Voltage sv 748289 ° +70 Output Voltage 65v ‘Storage Temperature Range 85010 +1500 Lead Temperature (Sokiering 10 Sec) +3006 DM74S289 Electrical Characteristics ‘Over recommended operating free-air tomperature range unless otherwise noted (Notes 2 and 3) ae ee a oe ei et : 3 in ae att he eae aa i Yoo [Hahei Gunde {Y= at s Se ety ee ee = | enemas ie a 2 e DM74S289 Switching Characteristics 745280 Switching Characteristics : ras mt want connor vo ees 2 [vfs a inne tou Disable Time from Chip-Enable_ 42 "20 ns. ut Disable Time from Read/Write 13 25 ns SN = s on 3 : = ene z = Ss Sen eae : = (ot aaa eee [esa ; : = fastens 3 : ‘Note 1 Absolute Maina Rags re ore vals beyond which We salt ol be davescaneol be qurriod Exon 6“ Operairg Tenparare Renge they ae rot ant 1 my at te Gece shou be epee al hee las. The lable of “EactieChracostieprovdeeconsane fr acu eves inspects mites apy aoe the 55 ta + 25°C para ange fre OMSASINS and aco the Co —7°C range 8. ypes wre gen or Vog ~ SOV an6 Ta = 25 Note 3 At curents nit deve pis shown 48 pont, ctf dove pi ak nape voape referenced ocd nus newt ete, A aun soar ‘rime or min on abet valve basa Note 4: lc macs wih al pus rude are he outs open, 52,DM74S289 Switching Time Waveforms Enable and Disable Time from Chip-Enable rT ww mote) gy, waverons (wore) aooness ‘wots wove yy oureur 180 oT README eet vegans i tw mere ere ne ok FIGURE2 Note : Wevetor i forthe cpt whiter condons su al he otis lw exon when abo ote 2 Wher mesauing dela tes rom adress inp, the chip ali lw aca rade mp ih ‘ote 2: When meaauing delay tes rom poral pu te dss inputs rods ae the rea/wrt pt ih ote & pit wavlome are spiny pose generates hg the folowing charactors | = 2564's 25Mn8 PAR < 1 MHE end Zour = 50m 513) 68ZSPZWGDM74S289 Block Diagram ‘svoness imeuTs) AC Test Circuit DECODERS. cnt enna ( EADIWRITE A) 01 o aTarnrurs 9. FIGURES. now ourrur UNSER TST wasne ano sense AMPLIFIER CONTROL row ww ourhurs ary