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    12 views58 pages

    Cache Datasheet For Test

    Uploaded by

    Gabriel Leite Roos

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    © All Rights Reserved
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    Ovis TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 VL82C386SX SYSTEM CACHE CONTROLLER FEATURES Optimized for TOPCAT™ 386SX and + ‘Supports memory configurations to. +25 MHz operation + Optimized for one or two dual 4K x 8 SCAMP™-LT chip sets 16MB + Improved i386SX™ and AM386SX™ + Programmable cache architecture system performance ~ Block size: 8 or 16 bytes = Fast look-aside architecture = Line size: 2 bytes = Zero wait state read-hit accass = Update strategies: single cycle cache data RAMs + Operates both in pipelinad and in non-pipelined modes = Reduces avarage processor wait {one line) ‘+ Builtin sol-tost and cache data RAM states to near zero «+ Wite-protec ragion support testability features + Muttiple cache organizations = Write-protect regions (#): 256 + Auto-tlush on EMS-update events = Two-way set associative: 16KB — Write-protect region size: a, — Two-way sot associative: 32KB ‘2KB botwaen 512K and 1M 100 lead MOFP + Memory update strategy + Non-cacheable region support = Write-thru = Non-cache regions (#): 504 + Least recently used (LRU) repiace- ‘ment algorithm — Non-cachoable ragion size: 64KB below 512K 2KB between 512K and 1M + Integrates complete cache directory 64KB above 1M on-chip BLOCK DIAGRAM xo DATA BUS TRANSCEIVER 388sx PROCESSOR INTERFACE INTERNAL, CONTROL BUS vus2ca31 BUS CONTROLLER INTERFACE NON-CACHEABLE WAITE-PROTECT AREA RAMS. & COMPARATORS PROCESSOR ADDRESS BUS Tagram SETA (CACHE DIRECTORY) ORDER INFORMATION Part Number VL820325-FC Package Metric Quad Flat Pack Note: Operating temperature range is 0° 10 470°C. CACHE DATA RAM CONTROLLER, ‘SYSTEM CONTROLLER viB2c3208 INTERFACE CONFIGURATION DIAGNOSTIC REGISTERS SeTB I366Sx is a vademark o intel Corp. ‘SCAMP and TOPCAT are a trademarks of VLSI Technology, Ine. AMBESX isa trademark of AMD Corp. www.DataSheet.in © VLSI TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 OVERVIEW ‘The VL820325 Memory Cache Controle isa high performance, highly Integrated cache controller for systems. bbased on the VLSI Technology, Inc.'s TOPCAT 386SX or SCAMP-LT chip sets, To implement a 32KB two-way set associative cache subsystem, all that is required is the VL82C325 and two 8k x 16 cache data RAMs. Tho VL820325 has bean designed to be an Intagral part of the TOPCAT386SxX chip set. This feature improves the overall ‘system performance by reducing the number of wait states during non-cache ‘cycles when compared to cache controllers which must pipeline all ‘cycles which can not be serviced by reading from the cache data RAM. The VL820320A TOPCAT System Control- ler or the VL820310 SCAMP Controller, and the VL82C325 operate in parallel to decode 386SX requests. The controller starts decoding the 386SX cycle simuttancously with the VL82C326 and is therefore able to actually start a memory cycle botora a miss indication is generated by the VL820325. ‘TOPCAT WITH CACHE SYSTEM BLOCK DIAGRAM PROCESSOR ADDRESS BUS 386Sx PROCESSOR vus2ca25 CACHE CONTROLLER D XD BUS MA 2 vuszea200 SYSTEM CONTROLLER 80 A xo veszess1 BUS CONTROLLER MA BUS. CACHE og DATA RAM CACHE A DATARAM PROCESSOR DATA BUS x MAIN SYSTEM DRAM ARRAY ‘SD BUS ‘SA BUS © VLSI TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 The VL820325 is a read allocate, write- thru cache. It maintains cache cohar- tency during non-386SX cycles by monitoring the VL82C320A/VL82C331 interface or VL820310 SCAMP-LT interface and the system address bus. Any HLDA cycle which writes to a memory location which is also cached will invalidate the line, HLDA read ‘oycles which result in a hit within the cache data have no effect. Read data for these cycles is not supplied by the cache data RAM. ‘The VL820325 supports 16KB or 32KB two-way set associative caches. On- chip high speed SRAM is used for the cache directory which is organized as, two 1024 entry directories. The line size is two bytes. Each cache directory entry defines the storage allocation for a block which is set to be four lines for 16KB cacho configurations or eight lines for 32KB caches. Each lina or ‘sub-block has its own valid bit within the cache directory entry. ‘System memory can be declared as cacheable or non-cacheable by setting CF clearing entries in the Non-Cache Table (NCT). The NCT has 504 entries which cover all of system memory (memory controlled by the system controller). In the area 512KB to 1MB, system memory is divided into 2KB regions, Each individual region can be declared cacheable or non-cacheable. In the remaining aroas of system memory, each 64KB region of memory can be individually selected as cach- able or non-cacheable. ‘System memory can be declared as write-protected (e.g., ROM space) by setting entrias in the Wrte-Protect Table (WPT). The WPT has 256 entries which cover the area of system memory from §12KB to 1MB. Each ividual 2KB region in this area can be declared write-protected. Writes to a write-protected region which result in a ccache-it will not update the contents of cache data RAM, ‘SCAMP-LT WITH CACHE SYSTEM BLOCK DIAGRAM PROCESSOR ADDRESS BUS 386SX PROCESSOR A CACHE DATA RAM VLe2c325 CACHE CACHE CONTROLLER A DATARAM OD PROCESSOR DATA BUS vis2c310 SCAMP-LT MAIN CONTROLLER MA BUS A SYSTEM DRAM A ARRAY © VLSI TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 PIN DIAGRAM vie2cs25 ~BUSBEL -BUSBEO HIDRIVE noc 8885883885 RBB5 BSS BBs wo Ly master Az 2 79 [] vssr voor (| 3 e 78 [5] x04 on 7 3 eo to 76 FE) voor ae C6 ew 75 [4 x02 ae 7 mf] 1 a7 ye 73 FY vssr ate C2 72 FQ x00 as (| 10 7 [ -Rovout vss (11 70 [4 Ne aw 2 e9 [Mss as 3 63 [ vssr az“ er [5 -EAE an 1s os FQ cer ao [| 16 es FA vssi ec? es [>] ~tce0 voor | 1¢ 63 [5] CAEN ae] 9 62 [] vssr 72 1 core as 2! eo [] -COEA as 2 so fF} voor 48 se) -cwee as [oy 4 s7 [] -cwea a2 56 F] vssr ay ss [|] -c8e0 vssa [—| 27 sa [5] -ceet -BHE [| 8 sa [Nc ue 2 [> NC fwsH Ts 88s 8858 FGF FF Fo Fs Begs sf HAO QUCUUUUUUUUUUUUOUUUU abe T4955 a © ‘VLSI TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 SIGNAL DESCRIPTIONS Signal Description Signal Pin Signal Name Number Type CPU AND TIMING INTERFACE PINS ROA 2,48, TL 10,1217 19°26, 100 ~BHE 28 om (em) -BLE 2 om (ema) -A0s a7 um wer 23 em w40 36 em pec 34 em HLDA 22 em “BLKA2D «42 um -nocye 48 ktpu -wecve 47 etpu -RovouT 71 om (em) -ROYIN 4s eT “FLUSH 20 LTPU HRO 51 em CACHE DATA RAM INTERFACE PINS ~CWEA 57 1O-TL (ema) ~CWEB 58 10-TTL (ema) ‘Address bus bits 23 through 1 - These signals are tied to the processor's address bus bits 23-1. Byte High Enable - This signal is tiad to the processor's byte high enable ‘output. itis used to select the upper byte of a 16-bit wide memory or 1O location, Byte Low Enable - This signal is tiad to the processor's byte low enable ‘output. It is used to select the lower byte of a 16-bit wide memory or VO location, ‘Address Status - This signal is tied to the processor's ~ADS output. Write and not Read - This signal is tied to the processor's W/-R output. Memory and not HO Cycle - This signal is tied to the processor's M-10 output. Data and not Code - This signal is tied to the processor's D/C output. Hold Acknowledge - This input is generated by the 386SX CPU, and indicates that the current hold acknowledge cycle Is for the DMA controller or other Bus Master. When active, the VL82325 ignores the CPU's status signals and monitors -MEMW to determine # the cycle will invalidate any cached item. ‘Address Bit 20 Enable - This active low input is tied to the -BLKA20 output of the VL82C320A System Controller and is used to deactivate A20. itis a decode of the AZ0GATE signal from the keyboard controller and Port A bit 1. Port Abit 1 may be written directly or set by a dummy read of UO por EEh. Refor to tho VL82C320A specification for more details. Non-Cache Cycle - This active low input may be driven by external circuitry during access to regions of memory which should not be cached. is ignored during memory write, VO, and hatvshutdown cycles. Write-Protect Cycle - This active low input may be driven by external circuitry during access to regions of memory for which cache data RAM ‘should be write-protected. Its ignored during memory read, VO, and hal shutdown cycles. VL82C325 Ready - This output is driven active for all cache read-hits and diagnostic operations. Its an input in the In-Circuit Test (ICT) Mode. Processor’s Ready - This input is tied directly to the processor's READY input pin Flush - This input is used to generate hardware-flush requests, When this input s driven active while the VL82C325 is enabled, the cache directory is, flushed. Hold Request - This input is tied to the processor's HOLD input. Cache RAM Write Enable A - This output is active low and is tied to the write enable(s) of the first set (A) of cache data RAMS. It is an input in the In-Circuit Test (ICT) Mode. Cache RAM Write Enable B - This output is active low and is tied to the write enable(s) of the second set (B) of cache data RAMS. is an input in the In-Circuit Test (ICT) Mode, 5 O VLSI TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 SIGNAL DESCRIPTIONS (cont) Signal Pin Signal Signal Name Number Type Description -COEA 60 foe ‘Cache RAM Output Enable A - An active low signal which is tied to the (ema) ‘output enable(s) of the frst set (A) of cache data RAMS. It is an input in the In-Circuit Test (ICT) Mode, -COEB 61 lo ‘Cache RAM Output Enable B - This activo low signal which is tiod to the (ama) ‘output enable(s) of the second set (B) of cache data RAMs. lis an input in the In-Circuit Test (ICT) Mode. CALEN 63 fom Cache RAM Address Latch Enable - An active high signal which opens the (ama) input address latches on all of the cache data RAMs. Itis an input in the In-Circuit Test (ICT) Mode. ~CCEO 64 ° Cache RAM Chip Enable 0 - An active low signal which is tied to the chip (ama) cenabla(s) of the least significant 16KB of cache data memory. -CCEt 66 ° Cache RAM Chip Enabie 1 - An active low signal which is tied to the chip (mA) tenable(s) of the most significant 16KB of cache memory. This pin is not ‘connected in the 16KB configuration. ~CBEO 55 ° Cache RAM Byte Enable 0 - An active low signal which is tiod to the chip (ema) soleci(s) of the cache data RAMs corresponding to data bits 0-8. ~CBEI 54 ° Cache RAM Byte Enable 1 - An active low signal which is tied to the chip (mA) selact(s) of the cache data RAMs corresponding to data bits 8-15, ‘SYSTEM AND BUS CONTROLLER INTERFACE PINS XD7- XD0 72, 74, 1o-TTL X Data Bus - These signals are tied to the XD bus in TOPCAT systoms 75,77, (12/24_mA) and the SD bus in SCAMP systems. This bus is used to read and write 78, 82-84 the VL82C325's internal configuration registers. -Miss 69 fom Miss - This active low output indicates that the current memory cycle (ma) request can not be serviced by the VL82C325. Its an input in the In- Circuit-Test (ICT) Mode. ~EALE 67 ° Bus ALE - This output is tied to the ~EALE input of the VL82C331 Bus (mA) Controller. itis used to strobe the byte enables into the bus controller. RSTORV 40 AT Power-on Reset Input - This active high input is driven by the VL82C33t Bus Controllers RSTDRV output. It indicates that a hardware reset signal has been activated. This is the same signal which is output to the ISA bus. This signal is used as the power-on reset source and is used to reset all internal logic. RESCPU a Tm Reset CPU - This input signal is tied directly to the processor's RESET input. tis used by the VL82C325 to synchronize its internal clock tothe processor's clock. The internal configuration registers are not initialized from RESCPU, cLK2. 86 FeMos Clock - This signal is tied to the processor's clock input. —TAI 38 HTPU ‘Three state - This input is used to put all of the VL82C325's outputs and bidirectional pins into the three-state mode for testing. -MEMW 44 HTL Memory Write - This input is driven by the -MEMW signal from the VL82C331 Bus Controller. When itis active during hold acknowledge, it indicates that a write oparation is taking place to system memory during DMA or Bus Master operations. -10R 43 us VO Read - This input is driven by the ~IOR signal from the bus controller. It indicates that an UO read operation is taking place. The VLB2C325's, internal configuration registers are accessed via VO reads and writes. v VLSI TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 SIGNAL DESCRIPTIONS (cont) Signal Pin Signal Signal Name Number Type Description =10W 50 Hm VO Write - This input is driven by the -IOW signal from the bus controller. It indicates that an VO write operation is taking place. The VL82C325's internal configuration registers are accessed via Y/O reads and writes. HIDRIVE 81 FTPU High Drive - This input is a wire-strap option. When low, the XD7-XD0 ‘outputs will sink the full 24 mA. When high, they sink 12 mA. Note that all AC specifications are specified at 24 mA drive, -HIDRIVE has an internal pull-up and can be lett open if 12 mA drive is desired, -BUSBEO 88 1o-TL Bus Byte Enable 0 - An active low output which drives the ~BEO/AO input (@ mA) of the VL82C331 Bus Controller. indicates that the low byte of the processor's data bus (D7-D9) is to be used in this cycle -BUSBEY 89 fom Bus Byte Enablo 1 - An active low output which drives the ~BE1/BHE (@may input of the VL82C331 Bus Controller. It indicates that the high byte of the processor's data bus (D15-D8) isto be used inthis cycle. “MASTER 80 irPu Master - This input is tied tothe bus controller's -MASTER input. i permits Master Mode DMA access to the VL82C325's internal configura- tion ragisters. if Master Mode access is not desired, then this pin can be lott unconnactes or pulled up. POWER SUPPLIES AND “NO CONNECT" PINS voor 3, 95, 59, PWR VO Ring Power Supply inputs, nominally +5 V. 76, 87 vssR 27, 48,58, GND VO Ring Ground returns, nominally 0 V. 62, 68, 73, 79, 85 voo! 18, 43, 95 PWR Internal Power Supply inputs, nominally +5 V. vssi GND Internal Ground returns, nominally 0 V. Ne No Connects - All no connects” must be left unconnected. Never Connect these pins to signal nets or to power nets. Ovisi TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 SIGNAL LEGEND Signal Signal Type | Description Type | Description HITL | TTL evel input 0-00 | Open drain ETPD | Input with 30k ohm pull-down resistor ° CMOS and TTL level compatible output ETPU_ | Input with 30k ohm pull-up resistor O-TL | THLievel output FTSPU | Schmittrigger input with 30k ohm pull-up resistor O-TS | Three-state level output Lemos] CMOS level input " Input used for testing 1O-TTL | TTL level inpuvoutput GND | Ground TT-OD | TTL level inpuvopen drain output pwr | Power 10-00 | Inputopen drain, slow turn-on DEFINITION OF TERMS For tho sake of consistency. a set of share the same values in set be updated wih he Gatitoa's included hore, Those tho upper to thor a Conti thew. temas orgeizs in op-down Grosses Typialy tee oe rane as hey aotypealy sed 0 Sone og RAM ery or Rea.) An update poly which | dose the Nerarhy of tho seh bloce and thre sro See cee eae Wtazesess meal tog serge mille ssbbloastoce atocted onion ead posecitviy The number fens in a Subleck This is th thd lve Cycles do ot loca acolo wiichone a {wen ofthe Merarchy Spoce nthe cache Shots could posi bo Wiehe safer sreut Seco meppes.eg haere: Claman WNChICO>.——Lookasde thorceney onal Way conte each a Gated arcnon. Ins. Uankatde Ths poly enables Gress mapsto oro ace chp cache conto tis yee be sated foment, item awe ithe some as ine yam cone, wes olae sect wees barecan be for pare win ihe Sresscouldbo monet bis at ttaltag storage Vug26225, een blow two beatone reaueed wih sti cache hime hat Set ‘The set of tags is the ‘evel of hiararchy. reduce average cache- highest leelotthecacho Line Same as subbock or i- meses tenes momeryerganzaton Ne tegetod caches (neo as : archy. There is one set levels of hierarchy), for a Leat Recently Used reves to the algorithm which is for each degree of asso- direct mapped caches to replace items ir Single ameryes sthanetaltgsbeage used vepaca ama associative cache has two (two levels, its the same a ceaminieeete Seschae which we wipe “Amemey be Serazsciatn che Snsecd pul ne Sgetuneecuntar tet arte cnt aes wantin possson fxtalacomant onan made of a number of Write-thru This policy forces a write which least recently ere cocaine cycle to external memory generated a cache-hit Block _This is the second level of (ORAM) for each write (ead or write) willbe hierarchy, it consists of a performed by the proces- chosen for replacement number of items (sub- sor. The cache data RAM blocks or ings) which all (SRAM) might or might 8 Oo VLSI TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 FUNCTIONAL DESCRIPTION RESPONSE TO CYCLE TYPES The VL82C325 will cache only the memory which exists in the main memory controlled by the VL82C320A ‘System Controller and VL82C310 SCAMP Controller. This includes all memory segments which have been ‘shadowed as well as memory (ROM or RAM) which exists on the ISA bus. The VL820325 is a look-aside cache controller. it operates in conjunction with the system controller. The system controller is able to bagin a cycle in main memory while the VL82C325 simultaneously determines whether the cycle hit or missed in the cache data memory. Hf a cache-miss occurs and the cycle is cacheable, then the VL820325 disables the cache data RAMs outputs, and allows the system controllar to complete the cycle. This is accomplished by asserting the -MISS signal to the system controller. The system control leris responsible for terminating miss cycles with READY. It the cycle was a read, then the \VL82C325 allocates a block for the new data in the cache directory. At the end of the cycle, the VL82C325 writes the new data into the cache data RAMS. the cycle was a write, then the ‘VL82C325 does nothing, because directory space is only allocated on read-miss cycles (read-allocate) Wa cache-hit occurs, then the \VL82C325 must complate the cycio in the cache data RAMS, ie., it ads from ‘or writes to cache data memory. tthe cycle was a read, then the cycle in the system controller must be aborted. This is accomplished by negating the MISS signal to the system controller (indicating a hit). In this case, the \VL820325 must terminate the cycle with READY because the aborted cycle in the system controler will not provide a READY. Ht the cycle was a write, then the cycle in the system controler is allowed to ‘complete as normal (write-thru), and the data is simultaneously written into the cache data RAMs. This maintains coherency between main memory and cache data memory. In this case, the state of the -MISS signal is ignored by the system controller. The system controller provides the READY. ‘The VL820325 will assert -MISS during non-cacheable read cycles. All such ‘eycles must complete in the system controller. Data is not read from cache data RAMs, and the cache directory is Unaltered. Write cycles are always considered to be cacheable. ‘The VL820325 naver allocates cache space for HLDA cycles. Howover, if a HLDA write hits in the cache, then ‘some action must be taken to prevent the cache data memory trom bacoming stale. Therefore, the cache directory valid bit for that ling is invalidated. The remaining valid bits for the other lines in the same block are unattered. Tables 1 and 2 summarize the \VL820325's and system controller's responses to all cycle types. oO VLSI TECHNOLOGY, INC. TABLE 1. RESPONSE TO CPU CYCLES Bus Cycle Type Cache Response Cntig| Data | Direc Wo} pi-c | wAR| s86cycle | Conditions | -miss| Reg | RAM | RAM | VL82C320A Response o | o o | NTA ° INTAto 331 o | o 1 | Undefined ° Hal/Shutdown onl 0 | voRead 325 Reg 0 | Read VO Readto "331 Other ° of 4 1 | vO Write 325 Reg oO | Write VO Write to 331 Other ° 1 |o 0 | Memory Hit 1 Read Aborted Memory Read Code Read | Miss 0 Write | Update | Memory Read (16, 2x8) Non-cache | 0 1 | o 1 | Hatshutdown o HatShutdown 1 1 0 | Memory Hit 1 Read Aborted Memory read DataRead | Miss ° Write | Update | Memory Read (16, 2x8) Non-cache | 0 Memory Read (8, 16, 2x8) 1 1 1 | Memory Hivwriteable| 0 write Memory Write (8, 16, 2x8) DataWrte | Hivwrite-prot| 0 Miss 0 TABLE 2. RESPONSE TO HLDA CYCLES Bus Cycle Type Cache Response Cnfig} Data | Direc 386 Cycle Conditions | -miss| Reg | RAM | RAM Memory Read ° Memory Write Hit ° Invalidate Miss ° WO Read ° VO Write ° © ‘VLSI TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 CACHE ORGANIZATION ‘The VL82C325 is a two-way set associative cache controller. lt sup- ports cache sizes of either 16KB or 32KB, arranged as 2x 4K x 16-bit or 4 x 4K x 16-bit respectively (refer to Figure 4), Table 3 gives a summary of the cache directory structure in each mode. Figure 1 depicts the manner in which main memory maps to the cache data mamory. Main memory is divided into ages, each page being the size of one set of cache data memory. Pages are further divided into 1024 blocks each. Ablock of main memory at offset X in page W always maps to a block at offset X in either of set Aor sot B of cache data memory. Because there are two sets, two such block Xs (each from a different page) may reside in ‘cache data memory simultaneously. Howovor, if a third accoss is made to yet another block having offset X in a third and different page, then one of the ‘original blocks is discarded to make space for the new one. A least recently Used (LRU) algorithm is used to determine whether it will map to set A orto set B. The page number associated with each ‘cached block is retained in the cache directory. The directory contains one tentry per block. Thus, there are two directories (one for each set) each ‘containing 1024 entries, Blocks are further divided into sub- blocks or lines. Each directory entry also contains a valid bit per sub-block, ‘The sub-block valid bits reduce the umber of accesses to main store by allowing the VL82C325 to fetch only those lines which have been requested by the processor. Hivmiss is determined as follows: ‘The biock number of the memory address is used to extract an entry trom ‘each of the sot diractories. The memory address is then compared to ‘each entry in parallel, Hf either entry ‘compares true, then a hit has occurred, Iris not possible for both entries to com- pare rue, The look-up function is depicted in Figures 2 and 3. TABLE 3. CACHE DIRECTORY CONFIGURATIONS. Cache Block | Sub-Block Hot Sie | #of | Sie| Size tot Directory (Ke) | Sets | (B) | (Line)(6) | (KB) | Pages | Entries per Set 16 2 8 2 8 2048 1024 32 2 | 16 2 16 1024 1024 1" Ovisi TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 FIGURE 1. TWO-WAY SET ASSOCIATIVE CACHE ORGANIZATION CACHE DATA MEMORY BLOCK NUMBER = 1023 SETA [BLOCK NUMBER « 1023, MAIN SYSTEM MEMORY STB ADD = FFFFFF HEX PAGEN ‘SUB-BLOGK=N att ee i : PAGE = W, BLOCK = 1023 & 8 SHOEI — = : : LOCATION A : = SUB BLOGK-0 5 4 PAGE ~ W. BLOGK=0 ‘BLOCK NUMBER = 0 vie2cs25, CACHE DIRECTORIES sere. BLOCK NUMBER = 1023 PAGEO seta [BLOCK NUMBER = 1023 ‘ADD = 000000 HEX |_| stock NuMBER =x ‘BLOCK NUMBER = 0 suB-BLOcK=¥ TAO), | DIRECTORY ENTRY LOCATION A ADDRESS PARTITIONING Face = wiles aock VAD ETS 12 O VLSI TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 FIGURE 2. 16KB CACHE LOOK-UP LINE, BLOCK LINE BLOCK PAGE Ai-At2 AQ AGRI2 AI3-A23 CACHE DATA CACHE DIRECTORY RAM 4K x 168 VALID TAG at COMPARE oO VLSI TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 FIGURE 3. 32KB CACHE LOOK-UP LINE, BLOCK LINE BLOCK PAGE A-AI3 ANAS AGAIS A14-A23 ‘CACHE DATA RAM 8k x 168 VALID TAG ‘CACHE DIRECTORY et COMPARE Do-D15 -Miss © VLSI TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 NON-CACHEABLE & WRITE- PROTECT REGIONS ‘Sometimes it is undesirable to cache contain areas of memory, o.g., areas who's contents may change invisibly to the processors local bus. Examples are VO controllers or dual ported memories in mutt-processor systems. Two ‘machanisms are provided for tho definition of non-cacheable regions. The first is a dedicated input signal to the controller. The user may dacode non-cacheable addresses outside the controller, and provided that the -NCCYC signal is asserted with the correct timing, then the cycle will be treated as non-cacheable. In addition, non-cacheable regions can be user-defined in a look-up table within the VL820325. Non-cacheable regions can be established in 2KB increments in area A (between 512KB and 1MB), and in 64KB increments in area B (below 512K8 or above 1MB). Immedi- ately following power-on reset, al of ‘memory is configured to be cacheable, ht may also be necessary to declare cortain areas of memory write-pro- tected. For example, when caching OM. Two mechanisms are provided for the definition of write-protected regions. The first is a dedicated input signal to the controller. The user may decode write-protected addresses outside the controller, and provided that the =WPCYC signal is asserted with the correct timing, then the cycle will be treated as wrte-protected In addition, write-protected regions can be user-delined in a look-up table within the cache controller. Write-protect regions can be established in 2KB increments in area A (between 512KB ‘and 1MB). Write-protect regions cannot be established in area B of system memory. Immediately following power- fon reset, all of memory is configured to bbe non-wrte-protected. Prior to enabling the VL820325 by setting the CENA bit, in the Cache Configuration Register the bits corre- sponding to the non-cacheable regions and to write-protect regions should be Sot, as desired, in the Non-Cache Table (NCT) and in the Write-Protect Table (WPT) respectively. Prior to setting up the NCTWPT, the NCTPGM bitin the Cache Control Register (CCTRL) must be set tot to enable programming of the tables. ‘Altar all non-cache areas and write- protect areas are defined, NCTPGM ‘should be cleared and the NCTENA, bit of the CCTAL, should be set to enable the NCTAVPT comparators. Table 4 shows how the NCTWVPT tables interact with the W/-R, -NCCYC, and =-WPCYC pins and with the NCTENA bit in the COTRL Register. TABLE 4. NCT/WPT INTERACTION WITH OTHER SIGNALS. Nc |er} Cacheable | |-we| oT Writeable win | cyc|ENA| NCT @ eye} ena] wer | (2) 1 fx tx] x Y o}x| x N o Jolx | x N 1 to] x Y Obes |itaa| OF |e Y rfr]o Y ofrfrfo Y ee N ofrfata N TABLE 5. NCT/WPT (AREA A) DEFINITION 512KB s MAIN MEMORY ADDRESS < 1M Ontset Non-Cache Region Starting Address in hex, A23-A0 (re) | 07 05 05s sss oo 081800 081000 00800 080000 01 083800 033000 082800 082000 3E oFD800 oF D000 oFca00 oFc000 oF oFFa00 oF F000 oFE800 oFE000 wer | nor 15 oO VLSI TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 TABLE 6. NCT (AREA B) DEFINITION MAIN MEMORY ADDRESS « 512KB or 21M aaa TNon-Gache Region Starting Address In hex, A22-A16 (nex) | 07 06 DS Ds 03 D2 DY ooo oo | o7 | os | os | o¢ | os | oz | o: | 00 o1 Not Used (see Area A) oe | 17 | te | as | 1 | ss | 2 | | to oo «| | | w | ic | we | ta | wo | te we |e | re | 5 | re | ra | fe | Fr | ro iw | re | re | wo | rc | ee | ra | ro | Fe Y VLSI TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 CPU AND TOPCAT INTERFACES 386SX PROCESSOR INTERFACE The VL820325 monitors the 386SX bus cycle definition signats to determi Which oycles ican service totally (memory reads trom cache data RAM) or must participate in (cache-miss, etc.) Figure 4 ilustrates the interconnect between the processor and the \VL820326. The processor and the \VL82C325 share the samo CLK2 signal ‘The VL82C325 has two reset input sig- nals. RSTDRV is used as the global power-on reset signal within the ‘VL820325 and when itis asserted, it causes all the internal registers and state machines to assume their initialization state. Any data stored in an internal register, diroctory, or NCT will ba lost and must be restored after RSTDRV has been negated. RSTCPU is used to synchronize the VLB2C325's internal processor state machines to CLK2 and the 386SX processor. Asserting RSTCPU with RSTORV not asserted does not initialize the \VL82C325's Configuration/Control Registers, directory or NCT. ‘The 386SX processor's Next Address Request (-NA) input may be driven ac- cording to the rules of the 386SX CPU. ‘The VL82C325 does not control NA, but it will operate both in pipelined and in non-pipelined modes. ‘When one of the VL82C325's internal registers is referenced by the 386SX, the peripheral data bus is used for the ‘ata transfer (XD bus). /O read and write cycles are used for these trans- fers; all of which execute with slot bus type cycle timing. VL820320A SYSTEM CONTROLLER INTERFACE The system controller is responsible for ‘executing all on-board cycles (ORAM). When a cycle misses in the cache, the system contoller may have to complete the cycle. In order to minimize the average wait states of miss cycles, the VL82C320A System Controller starts to docode the cycle even before the VL82C325 indicates a miss. The VL820225 issues the -MISS signal to the system controllar which than aborts, the cycle on a cache-hit or allows the system controller to continue on miss and write cycles. During a read-hit, the VL82C325 will provide the READY to terminate the cycle. However, for cyclas which ‘complete in the system controler, the system controller must terminate the cycle. The CPU's READY input signal Indicates to the VL82C325 that the cycle is completa and that the data is available on the data bus (read cycles). ‘Tho VL82C325 can then negate the write strobe to the cache data memo- Figs to update the cache during cach. ‘eable read-missos. . ‘The VL820325's internal configuration ragisters are accessed via VO reads and writes, During those cycles, the data is transferred tofrom the CPU by means of the peripheral data bus (XD7- XD0 bus). The VL82C325's Configura: tion Ragisters are not accessible during DMA cycles, but may be made access: able in Mastor Mode DMA cycles by ‘connecting the -MASTER input signal. VLg2c331 BUS CONTROLLER INTERFACE The bus controler is responsible for ‘executing all of-board cycles (includes FOM and UO cycles which are consid- ered off-board). When a cycle misses in the cacho, the bus controller may have to complete the cycle, The bus controller is not connected to the VL820325's -MISS signal, soit can not tell whether the cycle was a hit or a miss. However, itis “slaved! to the ‘systom controller, and so the system controller will not command the bus controller on cache-hit cycles. During read-miss cycles the VL820325 requires that a full 16-bit line be fetched, even if the CPU asked only for single byte. The bus controller's byte ‘enable inputs are generated by tho \VL820325 (-BUSBE1 and -BUSBEO) The VL820325 converts 8-bit read- misses to 16-bit reads by manipulating the bus controller's byte enables. The cycle is converted to 16-bit only ifthe address of the cycla is determined to be in a cacheable region. Tables 7 and 8 summarizes the conversions for various cycle types. The VL820325 also supplies the ~EALE signal to the bus controller. This ensures that the bus controller samples the VL82C325 genorated byte enables with the correct timing, During HLDA cycles, the bus controler ‘must control the CPU's byte enables, Therefore, the VL82C325 reverses the direction on its -BHE, -BLE, -BUSBE1, and -BUSBEO pins; allowing the bus controller to drive the byte enables through the VL82C325. HLDA writes which hit into the cache in- validate the cached line. The ‘VL82C325 uses the -MEMW signal from the bus controller to detect these cycles. On the rising edge of -MEMW (when HLDA true), ifthe memory address hits in the cache, the cached line is invalidated, 7 OQvisi TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 FIGURE 4. CPU AND TOPCAT INTERFACES pa =SADY (Farsi Se7ROY_ visece2s = -ROVIN CACHE CONTROLLER AOYOUT} a JASTORV ~or| RsTopupe—————BSToPU _)_|_stastopu ow cuxa| cue. louKe wens] a8} =A0s ADs ae wen pat w10. a onc. t ~BHE, -BLE| - A2aat LDA’ + HOLD! 386SX___D15-D0-—+ PROCESSOR RSTCPU myouKe =}-A0s x07:x09| Wik M10 -READY| D0 iow ae] A23.45 08 + Pore, BLE 01: P1500 yeacazoa HULDA SYSTEM| w|iina CONTROLLER] STORY x07-x09| ~EALE ~BHE, -BL| Ig $$$ az3.as —wem| {tn 00] vie2ca1 Bus ~OR| CONTROLLER, 18 oO VLSI TECHNOLOGY, INC. ADVANCE INFORMATION VL82C325 TABLE 7. 8-BIT TO 16-BIT CONVERSION - CPU CYCLES Bus Cycle Type mio} pic | wi-R | 386 cycle | Conditions Size o | o o | NTA o | o 1 | Undetined ofa o | vORead of 4 1 | vowrie ee 0 | Memory Code Fetchis | 16 Code Read | Always 16-bit ee 1 | Hal/shutdown 1 1 0 | Memory Non-Cache Data Read Cache Convert to16-bit 1 1 1 | Memory Data Write TABLE 8. 8-BIT TO 16-BIT CONVERSION - HLDA CYCLES: Bus Cycle Type 986 Cycle Conditions Size Memory Read Memory Write VO Read VO Write Og VLSI TECHNOLOGY, INC. CE INFORMATIO! VL82C325 CACHE DATA RAM INTERFACE ‘The VLB20325 directly controls the cache data RAMs with no external logic required. The intertace is optimized for use with dual 4k x 16 cache data RAMs. Each RAM is capable of ‘operating in a two-way set associative mode, with each set being 4K x 16-bit ‘Therefore, a 16KB cache can be imple mented using only one RAM chip, or two chips for a 32KB cache. ‘The VL820325 produces two chip enable signals, -CCE1 and ~CCEO, ‘one each for the least significant and ‘most significant 16KB of RAM. ~CCE1 is not used in the 16KB configuration. Two byte enables, ~CBE1 and ~CBEO, allow the cache data RAMs to perform byte write operations. -CBEO is ‘connected to the chip select inputs corresponding to the least significant byte of each cache data RAM (bits 0-7). ~CBE1 enables the most significant byte (bits 8-16). A raad- oF write-hit into set A causes set ‘Ato be read or written with -COEA or ~CWEA respectively. Similarly for sot B using ~COEB or ~CWEB. The cache data RAMs have on-chip address latches which must be strobed. The processor's -ADS signal is unsuit- able for this due to the pipelined mode of the 386SX. The VL82C325 produces the signal CALEN which is used to latch the cache data RAM addresses. ‘The data inputioutputs of the RAMs are tied directly to the processor's data bus. This provides for the fastest possible ‘access time to the data RAMs. Only during a reaé-hit are the data outputs enabled. The remainder of the time they are disabled, thus allowing normal ‘operation of the processor data bus. FIGURE 5. Rstcpu;<———BSICEU »} ‘tke Cure s86sx PROCESSOR Reon 15-09 -cwes| 7 we tiene) ee =SOeN (K299) pea i. caten] GALEN Tied Aviso] a1t-k0pee—t ce} cep cara -cs0| -cso}— COE! -csi]-cs1 vege 203 {240 CONMURATIN | sera [cos a (eke 16) -O88 CACHE DATA RAM INTERFACE ‘16KB/32KB TWO-WAY SE STORY Mwto M30 __etiwio oc} be __o| -BHE,-BLE_- >| T ASSOCIATIVE lAStoRV cae RstcPu -cce!, -cce9| lcuxe ‘CALEN aos -coEB, -coeal wer OWED, -CWEA) -c9o} pec -oHe,-BLE a23-a1 vusaca2s| cacHe| conTROLLER| Azat [SNT4AGT2140A, 7OY183, HME2168 owen) SETA (26319) “oe bo | | We ~c08A CALEN Ast-Ao] CAEN AtAo SNTAACT2N408, 70183, HME2I68 ae ce} -cef cst] | eso] -cs0 coe

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