TOSHIBA MOS MEMORY PRODUCTS bw bo [robo [Output taabia eo Outpoe in Wegi-t | - | 30] = = [tou Output Data Hold Time 3 = xo = wate COL T ‘eens vant-ae]sovsannamc-ie frosseora rina emer panateter TodeEdodpt-at| roceabrapt~is eesaleunieas | yar vats [wits [ts [nate | atm | na fue |Welte tycle Tine as [| - [soo | - [ago - eve [vette Pulse wach Cs ee fou [otto Selection eo id of wie | és |= | oo | - | 100 tas |Addvess Get up Time oO = of [Hik lide Recovery Tine s[-[s |= = | Front eo Ootput. High-e ae ee ee Fons [RP to Output Loe 2 w | - pol - [POS [data Set up Time _ 40 = 50 [ = [Fou Josta Hokd Time of-t eL= A.C. TEST CONDITIONS Cutput Load + 100pF + 1 TTL Gate Input Folge level : 0.6, 2.40 Timing Nessurenents 0,8V, 2.20 Reference Level 0,BV, 242V try te sng _ 1-46-23-14 >TC55257APL-85/APL-10/APL-12 ‘TCS52570FL-85/AFL-10/AFL-12 TTINTNG KAVEFORNS Reap cect <1) ‘ao vo ae "a te co ‘oo ~ vo tt 1 Poor (OE COVIFUE HATA. VAETD — wmrce creus 1 C4) (R/u contvotted Wette) sme tf 7 cot he ng fe = Dat 1-46-23-14HUDDZD/APL-BO/APL-TU/APLTZ ——______, TC55257AFL-O5/AFL-1O/AFL-12 7=46-23-14 verre crete 2 4) (GE controlled Wests) Powe L » a Vian —. ee Yn = ra — B/W 4s High for Read cycle. Assuming that UE low eransition occurs coincident with ar after B/W Tow transition, Cutpute renein in a high impedance state. Aneuning that UE igh transition occurs coincident with ox prior to B/W High transition, Outputs renain in a high inpedance state, Assuming that UE 12 High for Urita Cycle, Outputs are in kigh impedance state during this period. . — p42 —TCSSZ57APL-BG/APL-1O/API-12 ©“ T-a6-25-14 > ‘TC55257 AFL-G5/AFL-10/AFL-12 TATA RETENTION CPARACTERTSTIES] (reno 70°e) seo, FARANETER wea. | ree, | wax. | wee Vou | date retention supply Voltage ao | - [55 | ¥ Yorsow | - | - | 50 i Standby supply Current as vA 0s 7 Ser vorsav | - | - [100 teon | Chip Deselection to Data Retention Mode of-|- | 8 Ls Revovery Time tec] - | - Note (1): Read Cycle Pine, EE controtied Data Retention Node vio DATA RETENTION MOOR TE the Vi of OF Le 2.20 fn operation, Yupsi cuerent lowe during the period that eha Upp voltage Se golng davn fon 4.50 eo 2.0,TE55257APL-65/APL-10/APL-12 T46-23-18 TO55257AFL-85/AFL-10/AFL-12 DIP 28 PIN OUTLINE DRAWING (6028A-P) Ct 3 3] E Tiss * essary Lee 4 Mote: Lead piteh is 2.54 and colerance is 0,15 ageinat theoretical center of each iead that ta obtained on the basis of Novi and Wo.28 Leads. MEP 28 PIN OUTLINE DRAWING (F2EGA-P) UDDANnnonAno nn eussioa oter Lend péteh 15 1,27 and toloranca to 40-12 againee teeorarteal wor of cach iead that 4a obtained on the baste of No.1 a io 28 Leads, — Daa —