740 Exercises 555 hat ac rrays, substantially improved formance—can be obtained. The example on 1 simple change of loop structure could li Historical Perspective and Further Reading nis hi 0 an overview of memory technologies, from mercury delay line RAM, the invention of the memory hierarchy and protection mechanisms, and concludes with a brief history of operatin includin CSS, MULTICS, UNIX, BSD UNIX, MS-DOS, Winde inus, Cai cemmepnaraneneteerat206 Co) : & et7.10. Exercises 557 cd blocks. Cache ¢ miss pen Chis mem he miss penalty for C2 is 11 memory bus clock ssuim the caches are initially empty, find a reference hich 147 Blo Moret fe ne 748 a rage Memory Access T 7.49 6 jemory Acc 7.20 (10) mea mi em that supports interleaving either four ead ites, Given the following memory addresses in order as they ap. ary bi 1371 H hich one It 7.21 7. cache simulator to simulate several difere ions for t million references in a trace of gcc. Both dinero lator) andl vr f he Preface book for n r me an instruction cache of 32 KB and ea B using the same organization, You should choose at le 1 an es. Draw a diagram like that in Figure 1 page 503 that shows t organization with the best hit rate 7.22 You are commissioned to design a cache for a new s k nd requires separate instru ta cach, Th Ish ne nsand a size of 32K rs practice: Cachy tion BB For More Practice: Cach ation Associativity usually improves the put not alway {address references 1 90- Way Set ive nent would experience more misses irect-mapped 7.29 pose a computer's address f r . ice size is § bytes, the block size is B bytes, ane et sociative, Assume that BB et of tw Figure out what ing quantities are in terms of S. B, A the num u umber of index bits in he number of bits needed t ie cache [see Exercise 7.12), $5 1B For M Cache Configurations 3> [Bl For More Practice: Cache ( rations. Cache 2: Direct-mapped with four-word blo. Cache 3: Two-way set associative with four-word bl he following miss rate measurements have been m . Instruction miss rate is 49%; data miss rate is 1m Cache 2: Instruction miss rate is 2%: data miss rate isd a Cache 3: Instruction miss rate is 29% data miss rate is For these processors, one-half of the instructions contain a data a that the cache miss penalty is 6 + Block size in words, ‘The CPI for this work s measured on a processor with cache | and was found to be 2.0. Detern7.0 Exercises 559 e : i iecess using the same format as Figure following C program is run (with no optimizatio rocessor with a cache that has eight 3 icks and he bytes of data ache ac nerated by ref to the area sume th wihat is the expected miss rate cach irect mapped and strc yw about if stride ~ 255? Would either « 7.36 i Cache Configuration 7.37 1 1 ice: Memory Hierarch 7.38 [4 hours} fe want to use a cache simulator to simulate several c Band virtual memory organ Use the first | million refe of gcc for this evaluation. We want t he TLE miss rate for eack k LBsand es PLB with full associativity and 4 KB g Lu ull associativity and 8 KB page ry TLB with ei ociativity and 4 KB pages r h four-way associativity and 4 KB 7.39 74> Consider a virtual 1 stem with th roper woke 36-bit physical byte adel What is the total sizeof the page t ncess on this processor, assum hat the valid, protection, dirty, and otal of 4 bits and that allt nal rein ume that d tored w table.)560 Exploiting Memory Hierarchy 7.40 [15] <$74> Assume that th al memory system of Exercise mented with a two-way set-associative TLB with a tot B enttie Show the virtual-to-physical mapping with a figure like Figure 7.24 on j Make sure to label the width of all fields and signals, 7.44 (10) A processor has a 16-entry TLB and pat a the performance consequences of this memory system if a pr atleast 2 MB of memory at atime? Can anything be done to improve perform: 7.42 |10| <97.4> Butler overflow common exploit used to gain conte system. Ifa buffers allocated on the stack, a hacker could overflow the butler an insert a sequence of malicous instructions compromising the system, Can you hink of a hardware mechanism that could be used to prevent this? 7.43 [15] <974> Fo Practice: Hierarchical Page Tabl 7.44 [15] <974> B Fe Practice: Hierarchical Page Tables 748 IFall misses are classified into one of three categories—com sory, capacity, or conflict (as discussed c 13) —which misses are likely reduced when a program is rewritten so as to require less memory? How abo the clock rate of the processor that the program is runnin ncreased about if the associativity of the existing cache is increased 7.48 ng C program could be used to help vonstructa ¢ sim pes have not been defined, but the cod: descr lace during a read access toa direct-mapped , t Your task is to modily this eode to produce an accurate description of the actie that take place during a re s to a direct-mapped cache with multiple740 Exercises 561 1 Answers To rt nih wal Rad oe ena Check Yourself