IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO.

7, JULY 2017 5035

A Solid State Variable Capacitor With

Minimum Capacitor
Runruo Chen, Student Member, IEEE, Yunting Liu, and Fang Zheng Peng, Fellow, IEEE

Abstract—A solid state variable capacitor (SSVC) with mini-

mum capacitor is proposed. A variable ac capacitor (with capac-
itance varied from 0 to Ca c ) is traditionally implemented by an
H-bridge inverter and a large electrolytic dc capacitor, whose ca-
pacitance is 20 times of the ac capacitor’s value, in order to absorb
the ripple power pulsating at twice the line frequency (2ω ripple
power). The proposed SSVC system consists of an H-bridge and an
additional phase leg connected to an ac capacitor with fixed capac-
itance Ca c and can reduce the dc capacitance to minimum value
for absorbing switching ripples. The ac capacitor absorbs the 2ω
component and theoretically can eliminate 2ω ripples to the dc ca- Fig. 1. Ideal variable capacitor.
pacitor completely. The total capacitor size is reduced by 13 times
if same type capacitors (film) are used. Moreover, the proposed
SSVC shows special advantages in terms of the switches’ current
and voltage stress compared to other applications and the total
device power rating is only 1.125 times of H-bridge. Since the pro-
posed SSVC only has a small dc capacitor, a novel control system
directly based on ripple power is also proposed to achieve stable dc
voltage and fast dynamic response. Simulation and experimental
results are shown to prove the effectiveness of the proposed SSVC
with minimum capacitor.
Index Terms—H-bridge, power decoupling, minimum capacitor,
solid state variable capacitor (SSVC), 2ω ripple power.

Fig. 2. Variable capacitor implemented by an H-bridge inverter.

I. INTRODUCTION
HE concept of flexible ac transmission systems (FACTS)
T has been widely accepted as a breakthrough for modern-
izing today’s power grids because FACTS devices can enhance
the network stability, reliability, and controllability, which in
turn, improve grid transmission capability and power quality
[1]–[7]. Essentially, all FACTS devices, such as series com-
pensator, shunt compensator, and unified power flow controller
(UPFC) could be theoretically represented by “ideal” variable
capacitors. Fig. 1 shows an ideal variable ac capacitor, of which
the capacitance can vary continuously from zero to a fixed value
Cac . However, variable capacitors are not available for power
grid applications, where kilo- to mega-volt-amps are needed.
A variable capacitor can be implemented by an H-bridge
inverter as shown in Fig. 2. By controlling the angle between
Manuscript received January 16, 2016; revised July 4, 2016; accepted August
31, 2016. Date of publication September 13, 2016; date of current version Febru-
ary 27, 2017. Recommended for publication by Associate Editor T. Shimizu.
R. Chen and F. Z. Peng are with the Department of Electrical and Computer
Engineering, Michigan State University, East Lansing, MI 48824 USA (e-mail:
chenrunr@msu.edu; fzpeng@msu.edus).
Y. Liu is with the Michigan State University, East Lansing, MI 48824 USA
(e-mail: yunting9@gmail.com).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2016.2606582
the input voltage vs and the input current is , the inverter acts
as a pure capacitor. Meanwhile, by controlling the amplitude
of is , the inverter can achieve continuous variable capacitance.
As a result, the inverter can be taken as a variable capacitor.
The variable capacitor circuit is used for series compensator
module in distributed power flow controller applications [2]–
[3] and cascade multilevel inverter module in static synchronous
compensator (STATCOM) and UPFC applications [6]–[7].
The dc capacitor has to absorb the 2ω ripple power and the
required dc capacitance can be calculated by
Vs Is
Cdc conv = . (1)
ωΔVdc Vdc
For the variable ac capacitor, the maximum capacitance is
expressed as
Is
Cac = (2)
Vs ω
where ω is line angular frequency, Vs is rated grid voltage, Is
is rated current voltage, Vdc is the mean voltage across the dc
capacitor, ΔVdc is the allowed peak-to-peak voltage ripple.
For conventional H-bridge converter design, the voltage rip-
ple ΔVdc is small. In order to absorb the 2ω ripple power from
mimicking a variable capacitor with capacitance (0 − Cac ), a
bulky and expensive dc capacitor bank (normally electrolytic

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5036
Fig. 3. Proposed SSVC system configuration.
capacitors are used) with 20 times of the ac capacitance Cac is
needed to make ΔVdc within 2.5% Vdc if the maximum modula-
tion index 1 is used for simplification of the analysis. The bulky
electrolytic dc-link capacitors are the limiting components that
determine the lifetime of the single phase system [10], [24].
In order to achieve high reliability (long operational lifetime),
a great deal of research has been done to reduce the required
capacitance for dc-link capacitor, in order to replace electrolytic
capacitor with film capacitor, which has lower energy density,
however, much higher reliability [9]–[25].
In [9], a low capacitance H-Bridge circuit is proposed for
multilevel STATCOM by allowing large voltage ripple on dc
capacitor. The dc capacitor size is significantly reduced; how-
ever, a relative complex control system is required for dc voltage
regulation and grid current control due to the voltage regulation
on the high-magnitude low-order capacitor voltage harmonics.
Another approach is to add an extra circuit to absorb ripple
power in another energy-storage capacitor. One effective way
to evaluate the topology and control method is to compare the
energy requirement of energy-storage capacitor, EC , which is
a direct indicator of the capacitor size [9], and the total device
power rating (TDPR), which is an indicator of total silicon
area for the semiconductor devices. A detailed analysis and
comparison of existing methods will be provided in Section II.
Based on the power rating of the system, the minimal capac-
itor energy storage energy requirement Ecm in can be calculated
by integrating the 2ω ripple [9]
S tem based on ripple power is presented in Section III. Simulation
ECm in = (3)
2πfo
where S is the apparent power of the system and fo is the line
frequency and the minimal energy storage energy is equal to the
maximum energy stored in the variable ac capacitor.
In [19], circuit in Fig. 3 is proposed for pulse width modu-
lation (PWM) rectifier application. By adding the extra leg to
conventional H-bridge inverter, an ac capacitor with minimal
energy requirement is controlled to absorb 2ω ripple power.
However, the system requires higher dc voltage than convention
H-bridge system, an extra leg with the same current stress as
H-bridge system, and a dc capacitor with the same capacitance
value of ac capacitor. A control method based on phasor dia-
gram analysis is proposed in [19] to achieve power decoupling
control with 2-kHz switching frequency. However, in order to
get the accurate voltage and current reference for ac capacitor,
the control method requires complicated mathematic calcula-
tion for the ac capacitor reference, which puts a lot of burden
on digital controller.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 7, JULY 2017
In this paper, the same circuit is used for SSVC application
and a new control strategy is proposed to implement SSVC with-
out requiring a bulky electrolytic dc capacitor bank. In addition,
compared with PWM rectifier application, SSVC application
shows special benefits in terms of voltage and current stress on
switches. In other words, the total device power rating for SSVC
application is much smaller, only 1.125 times of H-bridge, which
indicates the lower cost on semiconductor devices. First, the dc
voltage requirement for SSVC is the same as the conventional
H-bridge, which is much lower than PWM rectifier. Second, the
current stress on shared leg (connected to both ac capacitor and
grid side) is much smaller for SSVC: with rated power, only
switching ripple current goes through the shared leg. Since the
current stress on the shared leg is much lower, the conduction
and switching loss on the shared leg will also be smaller, which
is beneficial to the efficiency of the SSVC system.
The proposed SSVC system only has a very small dc capac-
itor to absorb the uncompensated ripple power during sudden
load change transition, which brings new challenge to SSVC
control system. In this paper, a novel control system directly
based on ripple power is proposed for SSVC application with
10-kHz switching frequency to compensate ripple power and
stabilize dc voltage. The ac capacitor voltage and current ref-
erence is directly calculated based on grid side ripple power
and dc capacitor ripple power without complicated mathemat-
ics calculation. The control system can achieve fast dynamic
responses with very small dc capacitor (smaller than one-third
of ac capacitor).
As a result, only a minimum ac capacitor (equal to the maxi-
mum capacitance value of ideal variable ac capacitor, Cac ) to ab-
sorb 2ω ripple power and a very small dc capacitor to smooth the
switching ripple are needed. Therefore, longer lifetime, higher
reliability, and higher power density can be achieved.
The rest of this paper is organized as follows. First, theoretical
analysis of the proposed SSVC system with minimum capacitor
is conducted from energy point of view and the comparison of
PWM rectifier and SSVC application in terms of devices’ volt-
age and current stress is presented in Section II. As a result, pro-
posed method for SSVC application has the minimal power de-
vice rating and minimal capacitor energy requirement among the
existing methods. The proposed control system for SSVC sys-
and experimental results that illustrate the operation of SSVC,
effectiveness of the control system are given in Section IV.
Finally, conclusions from this paper are presented in Section V.
II. SSVC SYSTEM CONFIGURATION AND THEORY
TO ELIMINATE 2ω RIPPLE
A. Proposed SSVC System Configuration
Fig. 3 shows the proposed SSVC system configuration. In the
circuit, a fixed ac capacitor controlled by the additional phase
leg is used to absorb the 2ω ripple power and theoretically
can eliminate 2ω ripple power to the dc capacitor completely.
As a result, only a small fliting capacitor is needed on the dc
side to absorb switching ripples. The ac capacitor (with a rated
voltage of Vs ) is fully utilized to store 2ω ripple energy since it
can be fully charged to its rated voltage (+Vs ) and discharged
fully to its minus rated voltage (−Vs ). Therefore, the proposed
CHEN et al.: SOLID STATE VARIABLE CAPACITOR WITH MINIMUM CAPACITOR 5037

Fig. 5. Phasor diagram of SSVC.

Fig. 4. Equivalent circuit of proposed SSVC.

SSVC only requires a minimum ac capacitor and a minimum dc

capacitor to implement its function.

B. Theory of Eliminating 2ω Power to DC Capacitor

An analysis based on instantaneous power balance is con-
ducted. The three phase legs can be modeled as controlled
voltage source; for power analysis, only the components with
line frequency are taken into consideration. The equivalent
SSVC circuit is shown in Fig. 4.
Suppose the grid voltage and the grid side current without Fig. 6. Magnitude of the shared leg’s current ib with different grid current.
considering the switching ripple to be
 √
vs = 2Vs sin(ωt) the voltage and current of Cac with rated grid current will be
√ (4)  √ √
is = 2Is sin(ωt + π2 ) vCac = 2VCac sin(ωt) = 2Vs sin(ωt)
√ √ (12)
then, the expression of grid power is iC ac = 2ICac cos(ωt) = 2Is rated cos(ωt)
ps = vs is = Vs Is sin(2ωt). (5) and the current and voltage stress of the system will be
minimized.
Suppose the capacitor voltage and current to be
 √
vCac = 2VCac sin(ωt + θ) C. Operation of SSVC
√ √
iC ac = 2ICac cos(ωt + θ) = 2ωCac VCac cos(ωt + θ). Based on the previous analysis, the phasor diagram of the
(6) SSVC is shown in Fig. 5.
Then, the total ripple power absorbed by the ac capacitor is The phase A and phase C’s current stress is determined by Is
√ Icac . Based on (11), the current stress of phase A and C is
and
pCac = ωCac VCac 2 sin(2ωt + 2θ). (7) 2Is rated .
To simplify the analysis, the power on the filter inductors According to the three phases’ current relationship, we can
Lf , (which are normally less than 0.05 p.u.) is neglected. By get
controlling the power of Cac equal to the grid 2ω ripple power I˙b = −(I˙a + I˙c ) = I˙s − I˙Cac . (13)
pCac = ps (8) Based on (9) and (10), the ac capacitor current icac can be
the 2ω ripple power to the dc capacitor is totally eliminated. expressed based on the grid side current
√ 
Based on (4)–(8), (9)–(10) can be obtained iC ac = 2 Is · Is rated cos(ωt) (14)
θ = 0, (9) and the phase B’s current ib can be expressed as
ICac2 √ 
Vs Is = ωCac VCac 2 = . (10) ib = is − iC ac = 2(Is − Is · Is rated ) cos(ωt). (15)
ωCac
Fig. 6 shows the current magnitude of the Ib with different
by designing ac capacitor to be magnitude of grid side current Is . With rated power, is and iC ac
Is rated are equal, then phase B’s current ib is zero. In real system, since
Cac = (11) the grid side current and ac capacitor current all have switching
ωVs
5038
Fig. 7. Phase diagram of PWM rectifier for SPWM.
ripple, phase B’s current will be the switching current difference
between is and icac . When the grid side current is smaller than
rated current, the maximum magnitude of ib happens when
Is = Is rated /4. (16)
√ [14]. If the capacitor voltage reference is a full-wave rectified
Therefore, the current stress of phase B is only 2Is rated /4,
which is one-fourth of the conventional H-bridge system’s cur-
rent stress.
According the phase-to-phase voltage relationship, the volt-
age phasor of the three phases satisfy
V̇a = V̇s /2
V̇b = −V̇s /2
V̇c = V̇b + V̇cb = V̇Cac − V̇s /2. (17)
With rated power V̇s and √ V̇Cac being equal, the magnitude
of V̇a , V̇b , V̇c are all equal to 2Vs /2. When the grid current is
smaller than rated current, the magnitude of V̇Cac are smaller
than V̇s . None √ of the magnitude three-phase voltage phasor is
larger than 2Vs /2. Therefore, the minimum dc link voltage
for the proposed SSVC is expressed as
√ √
Vdc SSVC = 2 · 2Vs /2 = 2Vs (18)
which is the same as the conventional H-bridge.
In other words, by designing the ac capacitor based on (11),
the switches’ current and voltage stress of the proposed SSVC
can be minimized.
D. Comparison of SSVC and PWM Rectifier Application
For PWM rectifier application, the phasor diagram is shown
in Fig. 7 [19]. With
√ rated power, the current stress of phase A
and C is equal to 2Is rated , and the current stress of phase B
can be calculated by
 ripple power compensation with one leg of the H-bridge inverter
Ic = Is2 + Is2 − 2 cos 45◦ Is2 = 0.765Is (19)
which is more than three times of the current stress of SSVC
application.
According to the triangle relationship, the magnitudes of volt-
age phasors with rated grid current satisfy
Va = Vs /2
Vb = Vs /2
 capacitor works in ac mode. Since the ac capacitor voltage can
Vc = (Vs /2)2 + Vs2 − cos 45◦ Vs2 = 0.737Vs . (20)
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 7, JULY 2017
The minimum dc voltage determined by the peak value of va ,
vb , vc . Since vc has the maximum peak voltage, the minimum
dc voltage for PWM rectifier application is expressed as
√
Vdc rectifier = 2 2Vc = 2.085Vs (21)
which is 47% larger than the dc voltage of SSVC application.
E. Comparison of Proposed SSVC With Existing Methods
The TDPR of H-bridge is given by
√
TDPRH −bridge = 4Vdc · 2Is . (22)
√
Since the minimum Vdc for H-bridge is 2Vs , the minimum
TDPRH −bridge is 8S, where Is and Vs are the RMS value of ac
current and voltage, respectively.
In Fig. 8(a), a dc capacitor Cd is used as the energy-storage
capacitor. Cd is connected to the dc link by means of a bidirec-
tional buck converter, and the capacitor voltage is unipolar [13],
sine wave, the 2ω ripple power can be fully transferred to the
capacitor. Since the capacitor voltage can be fully charged to
Vdc and discharged fully to 0, the energy storage requirement
EC is Ecm in . The required minimum dc voltage of the circuit
is the same as the H-bridge and the current stress of switches is
equal to ac peak current. Therefore, TDPR of the circuit is 1.5
times of TDPRH −bridge .
However, the full-wave rectified sinusoidal reference, which
contains rich harmonics, is difficult for the control system to
track. Although it is possible to lower the harmonic content in the
reference by increasing the energy-storage margin (therefore,
the voltage does not go down to zero), this will sacrifice the full
utilization of the energy-storage capacitor. Therefore, in real
application EC will be larger than the ideal case Ecm in .
In Fig. 8(b), the single-phase inverter system consists of an
H-bridge and a half-bridge circuit for ripple power compensa-
tion [15]. The total power of C1 and C2 is controlled to be equal
to the 2ω ripple power on grid side. The advantage of this cir-
cuit is that C1 and C2 are also used for the dc filter capacitor.
However, in order to keep the switches’ current stress the same
as the H-bridge, the required dc voltage of the circuit is double
of H-bridge’s dc voltage. Therefore, TDPR is three times of
TDPRH −bridge . Since the voltage of C1 and C2 has a dc com-
ponent of half-dc link voltage to maintain a constants dc voltage,
which is the sum of the voltage of C1 and C2 , the energy of C1
and C2 are not fully used for 2ω ripple power compensation and
the energy storage requirement EC is significantly increased,
which is four times of Ecm in .
In Fig. 8(c), the circuit combines the half-bridge circuit for
in Fig. 8(b) [16]. Therefore, the circuit has the minimum com-
ponents. Another advantage is the current stress of the shared
leg is only 1/4 of H-bridge inverter, and the TDPR is reduced
to 1.25 times of TDPRH −bridge . EC of the circuit is still four
times of Ecm in .
A single-phase inverter system with the power decoupling
ripple-port shown in Fig. 8(d) is proposed in [18]. By adding
any extra H-bridge to interface the energy-storage capacitor, the
be fully charged to Vdc and discharged to −Vdc , the energy
CHEN et al.: SOLID STATE VARIABLE CAPACITOR WITH MINIMUM CAPACITOR 5039

Fig. 8. SSVC based on other existing methods.

TABLE I III. CONTROL STRATEGY

COMPARISON OF Ec AND TDPR FOR DIFFERENT TOPOLOGIES
Topologies Ec TDPR
SSVC based on Fig. 8(a) >Ec m in 1.5 TDPRH −b r i d g e
SSVC based on Fig. 8(b) 4E c m i n 3 TDPRH −b r i d g e
SSVC based on Fig. 8(c) 4E c m i n 1.25 TDPRH −b r i d g e
SSVC based on Fig. 8(d) Ec m in 2 TDPRH −b r i d g e
Proposed SSVC Ec m in 1.125 TDPRH −b r i d g e
In [19], the ac capacitor’s voltage and current reference are
calculated based on grid voltage and current phasors’ magni-
tude and phase angle, which requires complicated mathematic
calculation. For SSVC system with a very small dc capacitor, a
novel control system with fast response is needed with higher
sampling frequency application (20 kHz). The proposed control
system calculates ac capacitor voltage and current reference di-
rectly based on grid side ripple power and dc capacitor ripple
power, without complicated mathematic calculation. The feed-
forward part of the ac capacitor power is calculated by grid
ripple power, which is updated with the sampling frequency
(20 kHz) to achieve fast dynamic response and maintain table
dc voltage during sudden load change transition. The feedback
part of the ac capacitor power is calculated based on dc capac-
itor ripple power. By using discrete Fourier transform (DFT),
the dc capacitor ripple power can be calculated based on the dc
voltage ripple and updated with twice line frequency (120 Hz),
to achieve better steady-state ripple power compensation per-
formance.

A. Cac Voltage and Current Reference Based on AC

Capacitor Power
First, the ac capacitor reference based on ac capacitor power
is analyzed. In order to compensate the grid side ripple power,
the power reference of Cac , pC ac should be controlled equal to
the ripple power pripple and the energy of Cac , EC ac should be
Fig. 9. Relationship between C a c voltage and ripple power.
  
1 2
Ecac = Cac vCac = pC ac = pripple = vs is . (23)
storage requirement EC is ECm in . Since the circuit adopts two 2
H-bridge inverters, TDPR is two times of TDPRH −bridge . Ideally, the ripple power is equal to grid side power ps and
The energy storage requirement EC and total device power can be directly calculated based on vs and is .
rating TDPR for circuits in Fig. 8(a)–(d) and proposed SSVC are The voltage of Cac should satisfy
summarized in Table I. Among the five methods, the proposed  
SSVC has the minimal EC and TDPR, in other words, the 2
|vCac | = pC ac . (24)
capacitor size and cost of semiconductor devices is minimized. Cac
5040 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 7, JULY 2017

Fig. 10. Control system for SSVC.

Fig. 11. Closed-loop compensation for ac capacitor voltage reference.

TABLE II reference for phase C is derived in (27)

KEY PARAMETERS
1 ∗
DC-link voltage, V d c 200 V
va ∗ = −vb ∗ = vab (26)
2
Switching frequency, f s w 10.8 kHz
DC capacitance, C d c 85 μF (0.27 p.u.) vc ∗ = vb ∗ + vcb ∗ . (27)
Grid voltage, V s 120 VAC (60 Hz)
AC capacitance, C a c 300 μF (1 p.u.) The feedforward part of the ac capacitor power reference is
Filter inductance, L f 0.4 mH (0.015 p.u.) directly calculated based on grid voltage and current reference.
The grid power reference pgrid is expressed as
∗
By changing the polarity of the voltage reference properly, pgrid = vab · i∗s . (28)
Cac can work in ac mode.
The grid power reference pgrid has two parts: dc component,
The current reference of Cac is
which is the power loss of the total system, and 2ω ripple ac
dvC ac component, which is the ripple power needed to be compensated
iCac = Cac . (25) by ac capacitor. By using a high-pass filter, the 2ω ripple power
dt
for ac capacitor power reference p∗C ac fdf can be obtained based
The ac capacitor voltage and current reference is accurate on pgrid .
and simple to calculate directly based on power reference. The feedback part of ac capacitor power reference p∗C ac fdk is
Fig. 9 shows the relationship of grid voltage/current, ac ca- calculated based on dc ripple power and is described in details
pacitor power, energy, and voltage reference. in the following section.

B. Control System C. Feedback Compensation for AC Capacitor Power

Fig. 10 shows the control system, which consists of grid side
current control, dc voltage control, ac capacitor voltage, and
current control, and feedforward and feedback compensation
for the ac capacitor power reference. The dc voltage controller
is to maintain the dc-link voltage Vdc by controlling the phase
angle of grid current ϕ. The grid side current controller is used
to regulate the reactive power by controlling the magnitude of
grid current Is∗ . A proportional-resonant (PR) controller is used
for the capacitor voltage/current control.
The reference voltages for phases A and B are expressed in
∗
(26). vcb is the reference to control the ac capacitor. Then, the
Reference
Considering parameter deviation in practical applications and
steady-state error in the capacitor voltage and current control, it
is difficult to eliminate ripple power to the dc capacitor only by
feedforward control. Therefore, the relationship between power
mismatch and dc-link ripple voltage need to be investigated
in order to design the closed-loop compensator for capacitor
voltage reference.
Assume the dc-link voltage to be expressed as
vdc = Vdc + ΔVsin sin(2ωt) + ΔVcos cos(2ωt) (29)
CHEN et al.: SOLID STATE VARIABLE CAPACITOR WITH MINIMUM CAPACITOR 5041

and the ripple power to the dc capacitor is expressed as

dvdc
pdc r = Cdc vdc
dt
≈ 2ωCdc Vdc (ΔVsin cos(2ωt) − ΔVcos sin(2ωt)). (30)
The ripple power to the dc capacitor is the mismatched power
between grid side ripple power and ac capacitor power. Based
on the mismatched power, the ac capacitor’s reference can be
compensated to fully absorb ripple power.
Fig. 11 shows the closed-loop compensation for ac capacitor
voltage reference. DFT is used to calculate ΔVsin , ΔVcos from
the dc ripple voltage. PI controllers then regulate ripple voltage
components toward zero by changing the power compensation
terms p∗cos , p∗sin . According to the relationship between power
mismatch and dc voltage ripple, the compensated ac capacitor
power should be
p∗C ac com p = −p∗sin sin(2ωt) + p∗cos cos(2ωt). (31)
Since the capacitor voltage reference is obtained based on
sinusoidal reference, the capacitor current reference can be di-
rectly calculated by derivation of the capacitor voltage reference
without introducing noise.

IV. SIMULATION AND EXPERIMENTAL RESULTS

To verify the effectiveness of the proposed SSVC and active
power decoupling control strategy, a 1.5-kVA SSVC is designed.
The key parameters are listed below in Table II.
For conventional H-bridge system, if the allowed dc voltage
ripple is 2.5%, the dc capacitance is 4.6 mF (15.5 p.u.). For
the proposed SSVC system, since the 2ω ripple power can be
absorbed by the ac capacitor, theoretically the dc capacitor only
needs to absorb switching current ripple, of which the capac-
itance is 50 μF (0.17 p.u.) [27], [28]. However, in practice,
considering the control system error, the dc capacitance is de-
signed to be 85 μF (0.27 p.u.). The ac capacitor calculated based
on (11) is 300 μF (1 p.u.). Since the capacitor voltage rating of
proposed SSVC and conventional H-bridge system is the same,
the total capacitor size is directly proportional to the capacitance
value of the required capacitor if the same type of capacitors is
used. Compared to conventional H-bridge system, the proposed
SSVC system reduces the total size of the capacitor including
dc capacitor and ac capacitor by 13 times.
Fig. 12 shows the simulation results of the proposed SSVC
with full rated power and half rated power. ma , mb , and mc are
modulation signals for controlled voltage sources va , vb , and vc .
The ripple power to the dc capacitor is completely eliminated,
thus the dc capacitor voltage has only switching ripple. The
average value of vdc is 200 V and the ripple voltage is within
5 V (2.5%).
Fig. 13 shows the simulation results of the proposed SSVC
with voltage or current harmonics. For cases of grid current
Fig. 12. Simulation results.(a) Half rated (b) Full rated
with 30% third-order harmonics and grid voltage with 10%
third-order harmonics, the proposed methods can effectively
control ac capacitor to compensate the ripple power with not is 200 V and the voltage ripple is within 5 V (2.5%). Fig. 15
only double line frequency but also other harmonics frequency. shows the dc voltage fast Fourier transform (FFT) analysis of
A 1.5-kVA SSVC prototype based on Fig. 3 has been built. SSVC with half rated and full rated power. The 2ω (120 Hz)
Fig. 14 shows the experimental key waveforms of the proposed voltage is within 0.5 V. According to (28), the 2ω ripple power
SSVC with half and full rated power. The average dc voltage to dc capacitor is smaller than 1 W, which is 0.067% of the rated
5042
Fig. 13. Simulation results with voltage or current harmonics.(a) Grid current
with 30% third harmonics (b) Grid voltage with 10% third harmonics
power (1.5 kW), indicating that the proposed control system has
effectively absorbed the 2ω ripple power. Fig. 16 shows the dy-
namic response to sudden load changes. The control system can
fast track the current and voltage reference. During sudden load
change, there is no excessive dc voltage overshoots. After the
load changes, the feedforward control will automatically change
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 32, NO. 7, JULY 2017
Fig. 14. Steady-state experimental waveforms. (a) Half rated (b) Full rated
the ac capacitor voltage and current reference to compensate the
ripple power; and the feedback compensation for voltage refer-
ence will work instantaneously to further reduce ripple voltage
on dc capacitor. The DSP clock frequency is 60 MHz. The com-
putation time including ac capacitor voltage & current control
CHEN et al.: SOLID STATE VARIABLE CAPACITOR WITH MINIMUM CAPACITOR
Fig. 15. DC voltage FFT analysis.
Fig. 16. Transient response to sudden load changes.
and 2ω ripple compensation is less than 10 µs; and the references
for ac capacitor are updated with 50-µs sampling cycle.
Figs. 17 and 18 show the loss and efficiency comparison of
proposed SSVC, PWM rectifier [19] and conventional H-bridge.
Since the system is design for reactive power compensation, the
efficiency of the system is defined as
Ploss
η =1− (32)
S
5043
Fig. 17. Power loss comparison between proposed SSVC and conventional
H-bridge.
Fig. 18. Efficiency comparison between proposed SSVC and conventional
H-bridge.
where Ploss is the active power consumed by the system and S
is the apparent power of the system.
As shown in Fig. 17, compared to H-bridge, the additional
power loss of the proposed SSVC is not significantly increased
with higher grid power. Since the shared leg’s current magnitude
is decreasing with higher grid power, when grid power is large
than 1/4 of the rated power as shown in Fig. 6, the power loss
on shared leg is also decreased. Therefore, the total power loss
caused by the added leg is relatively low with higher grid power.
Compared to PWM rectifier application, the current stress on
shared leg is much lower and the power loss is significantly
reduced.
V. CONCLUSION
A SSVC with minimum capacitor is proposed. By adding an
additional phase leg connected to an ac capacitor, the 2ω rip-
ple power to the dc-link is completely eliminated and the total
capacitor size has been reduced by 13 times is compared to
the conventional H-bridge system with 2.5% dc voltage ripple.
As a result, only a minimum ac capacitor to absorb 2ω ripple
5044
power and a minimum dc capacitor to absorb the switching rip-
ple power are needed. Furthermore, the proposed SSVC shows
special benefits in terms of switches’ current and voltage stress
and efficiency compared to other applications. A novel control
system directly based on grid ripple power and dc capacitor rip-
ple power is also proposed to achieve stable dc voltage and fast
dynamic response. The simulation and experiment have verified
the theoretical analysis the effectiveness of the proposed SSVC
with minimum capacitor.
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Runruo Chen (S’13) received the B.S. degree in
electrical engineering from the Nanjing University
of Aeronautics and Astronautics, Nanjing, China, in
2011. He is currently working toward the Ph.D. de-
gree in electrical engineering at Michigan State Uni-
versity, East Lansing, MI, USA.
His research interests include single phase power
conversion, gate driver, topology, and control of dc–
dc converters.
Yunting Liu was born in Hubei Province, China. She
received the B.E. degree from the Huazhong Univer-
sity of Science and Technology, Wuhan, China, in
2013. She is currently working toward the Ph.D. de-
gree at Michigan State University, East Lansing, MI,
USA.
Her research interests include single phase power
conversion.
Fang Zheng Peng (M’92–SM’96–F’05) received the
B.S. degree in electrical engineering from Wuhan
University, Wuhan, China, in 1983, and the M.S. and
Ph.D. degrees in electrical engineering from the Na-
gaoka University of Technology, Nagaoka, Japan, in
1987 and 1990, respectively.
From 1990 to 1992, he was a Research Scien-
tist with Toyo Electric Manufacturing Co., Ltd. From
1992 to 1994, he was a Research Assistant Professor
at Tokyo Institute of Technology, Tokyo, Japan. From
1994 to 1997, he was a Research Assistant Professor
at the University of Tennessee, Knoxville, TN, USA. From 1994 to 2000, he was
a Staff Member at Oak Ridge National Laboratory. In 2000, he joined Michigan
State University, East Lansing, MI, USA, where he is currently a Full Professor.