INTEL CORP (UP/PRPHLS) 20 D Mm 482b175 0079078 6 mm
2 PRELIMINARY
intel
MCS®-51 T-#4-44-07
8-BIT CONTROL-ORIENTED MICROCOMPUTERS
8031/8051
8031AH/8051AH
8032AH/8052AH
8751H/8751H-8
‘ig Internal Timers/Event Counter m Bit-Addressable RAM -
‘32 1/0 Lines (Four 8-Bit Ports) Cae
i Security Feature Protects EPROM Parts ™ 64K Data Memory Space
Against Software Piracy
‘Tho MCS®-1 products are optimized for contol applications. Gyte-processing and numerical operations on
stnall data structures are fecitated by a varialy of fast adroasing modes for accessing tho internal RAM, The
instruction sot provides a convenient menu of &bitarilhmatc Instructions, including multiply and digo instruc-
tions. Extensive on-chip suppor Is provided for one-itvarablos as a separate data type, allowing dct bit
‘manipulation and testing in control and logic systems that require Boolean processing.
“Tho 8051 isthe cxignal momber ofthe MCS-5t family. The 8051AH is kdentical othe 6051, but Ris fabricated
with HMOS I technology.
‘Tho 8761H Is an EPROM vorsion of the 8051AH; that is, the on-chip Program Memory can be electrically
programmed, and can be erased by exposure to ulravolt ligt. Its uly compatibie wih ts predecessor, the
£8751-0, but incorporates two new Tealures: a Program Memory Securty bit that can be used to protect the
EPROM against unauthorized read-out, anda programmable baud rate modification bit (SMOD). The 6751H-8
[a Montiel to the 8751H but only operates up to 8 MHz.
‘Tho, 8052AH is an enhanced varsion of tho BOS1AH, Its backwards compatible with the GOS1AH and is
fatiieated with HMOS Il technology. The B052AH enhancements are listed inthe table below. Also refer to this
table for the FIOM, ROMloss, and EPIOM versions of each produc.
Internal Memory Timers/
Device Interrupts
Program Data ceca "
08eAH ‘8Kx8 ROM 286x8 RAM ax 168i 6
B051AH 4K x8 ROM 128x8 RAM 2xt6sit 8
e051 aK x8 ROM 428x8 RAM 2x16sit 5
‘s032AH none 256x8 RAM 3x 168i 6
031A one. 1288 RAM 2x16 5
8031 none. 428x0RAM 2x 168i 5
875iH 4K x8 EPROM 128x8 RAM 2x test 8
87518 4K x8 EPROM 4208 RAM 2x16. 5
748 ‘onder hbo ene
tINTEL CORP (UP/PRPHLS) 20E O mm 4826175 0079079 T mm
intel wesest PRELINOHARY
T-49-19-07
Figure 1, MCS®-61 Block Diagram
Pakage Port PrtO an Bi open anes! f0
sa peptic tment rye
Part | Prefie | Package Type Fon 7 Art por aco
sosin |b ose
fetal |. | SEBRGERDE” | oto pins hat hav 1 weten hem fos andi
: R_| donee’ Bat sto can bo ued ao ngesnpesane ete
woaaan | P| atin Past
ert so he mulled ower acess and
Gooea |B | soeMCEROR | Feet ctr emeacre nti: aan and
Baa Moor tc apices coo soe
wa |—D | aoaincenoe —] _alaMamory ns ppicaton Een evong
seine | R | Saeed nal mulupa wan om
Pot dress he cae ye dura pore
PIN DESCRIPTIONS ry othe SER pata al sats
Sih dong progam vntenion ae ROM Sok
Voc: Sv votage Chem pate Cura pute we ated ng
program verification.
Ves: Circuit ground.
7.45,i
INTEL CORP (UP/PRPHLS) 20E
D mi 426175 0079080 6 mm
intel coos PRELIMINARY
T-49-19-07
TBs
Etat
sea
rene SBE
Bag SBA
mae ol
ane SBeits
aad
maelt
Et ee
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rn
‘EPROM only: (eoosPice)
Ps ory
Port 1: Port 1 is an S-bit bidirectional /O port with
Internal pulups. The Port 1 output butters can sinks
sourco 4 LS TTL inputs. Port pins that have 1s
writen to thom are pulled high by the internal pull-
‘Ups, and in that stato can bo used as Inputs. AS
Inpits, Port 1 pins that aro extornally boing pulled
tow will source current, on the data sheet) be-
case ofthe Intanal pulps.
Port 1 also receives tho low-order addross bytes
during programming ofthe EPROM parts and during
‘rogram verication ofthe ROM and EPROM parts.
ln the 8032AH and 8052AH, Port 1 pins P1.0 and
Pt also serve tho T2 and T2EX functions, respec
thal.
Port 2: Port 2 isan 8-it bidirectional I/O port with
Internal pulups. Tho Port 2 output butfors can sinks
‘source 4 LS TTL inpuls. Por 2 pins that have 1s
vwilten to them aro pulled high by the internal pull
Ups, and in that stato can Be used as inputs. As
Input, Port 2 pins that are externally being pulled
tow wil source current (i, on the data sheet) be-
‘cause ofthe Intonal pulps.
Port 2 omits the high-order addross byte during
{etchos from external Program Memory and during
faccassas to axtoral Data Memory that uso 16-5
addrossos (OVX @DPTR). in this application it
‘uses strong inlernal pulups when omitting 18. Dur-
Ing accesses to external Data Memory that uso bit
‘addresses (MOVX @Ri), Port 2 emits the contents of
the P2 Special Function Register.
Port 2 also receives the high-order adoss bits dur.
ing programming of the EPROM parts and during
program vertication of the OM and EPROM parts.
ort 3: Port 3 isan 8.itbidrectional 1/0 port with
Infernal pulups, The Port 3 output buffers can sink!
source 4 LS TTL inputs. Port 8 pins that have 13,
‘atten to them are pulled high by the intornal pul-
Ups, and in that stato can be used as inputs. As
Inputs, Port 3 pine that are external being pulled
tow will source curront (l, on the data sheet) be-
‘cause ofthe pulups.
Port 9 also serves the functions of various special
Tealures of the MCS-51 Famiy, as Isted below:
Por
oy ‘Alternative Function
P30 | AXD (sora input por}
3.1 | TXD (coil output por
3.2 | INTO extemal interrupt 0)
3 | INT (extemal intertupt 1)
a4 | To (Timer extemal inpud)
Pas mar 1 external input)
a | WA extornal data memory writ strobe)
3:7_| RD (oxernal data momory read strobe)
7480
20k Dp m= 482b175 0079081 & mm
INTEL CORP (UP/PRPHLS)
intel
[RST: Reset input A high on ths pin fortwo machine
cycles while the osclator Is running resets the do-
veo,
ALE/BROG: Addross Latch Enable output puso for
latching tho low byte of the address during accosses
to extarnal memory, This pin fs also the program
pulso input during programming’ of the
EPROM parts.
{in normal operation ALE is omitted at a constant
rato of Ye tho oscilatorfrequancy, and may bo used
for extemal timing or clocking purposes. Note, Row-
‘over, that ono ALE pulse is ekpped during each ac-
{C088 to external Data Memory
PBER: Program Store Enable Is the read strobe to
‘extemal Program Memory.
When the device is executing codo ftom external
Program Memory, PSEN Is activated twice each ma-
chine oycla, except that two PSEN activations are
‘skipped during each accoss to external Data Memo
¥.
ER/pp: External Accoss onable EA must bo
‘Strapped to Vgs in order to onable any MCS-51 do-
Vi to fetch codo trom extornal Program mamary
locations stating at O000H up to FFFFH. EA must
bo strapped to Vag for intemal program execution
‘Noto, however, that If tho Socurly Bit in tho EPROM
vices is programmed, the device will not fotch
‘code rom any location In external Program Memory.
‘This pin also receives the 21V programming supply
Voliago (VPP) during programming of the EPROM
parts,
uc = ane st0pe ccs
TOF LSP lect recwre
Figure 8. Oscillator Connections:
Mose.s1
rar
PRELIMINARY
T-49-19-07
XTALt: Input to the inverting escllator ampli.
XTAL2: Cutput tom tho inverting esitator amit
OSCILLATOR CHARACTERISTICS
XTAL! and XTAL2 are the input and output, respec-
tively, ofan inverting ampitior which can ba cong.
lured Yor use as an on-chip osclator, as shown in
Figure 3. Elthor a quartz crystal or ceramic resonator
‘may be used. More detaled information concerning
tho use of the on-chip osllater ie avaliable n Appi
callon Note AP-185, “Oscllalors for Microcontol-
fore"
To dive the device from an external clock source,
XTALt should be grounded, while XTAL2 is driven,
fas shown in Figure 4. Thore are no requirements on
the duty eyco of the external clock signal, sine the
Input to tho internal clocking creuty is Vough
100 pF), th noen puso on the ALE Ine may
Sy ALE witha Schenit Tigger, ores an ares latch with & Seni
‘Tigger STROE put
748INTEL CORP (UP/PRPHLS) 20k Dp m= 4826175 0079083 1
intel wes®.st PRELIMINARY
T-49-19-07
AC. CHARACTERISTICS 1) = C0 +70°0; Veo = 8V + 10%; Vos
Load Capacitance for PortO, ALE, and PSEN
‘oad Capacitance fr ll Other Outputs = 80 pF
100 pF:
an a 12 MHz Oscillator Variable Oseilator | yas
Min] Max Min Max
T/TOLGK. | OselatorFrequenoy 35 120 | Me
TTUHLL | ALE Pulso Width 127 BTOLCL— a0 8.
TTAVLL | Address Validto ALE Low | 49. TeLcL=40 6
TLLAX | Address Hold after ALE Low | 48) TOLCL=35 ns
TLL | ALE Low to Vali Instn
o75iH 189 aToLcL-160 | ns
AlOthers 233 4TOLCL—100 | ns
TLLPL_| ALE Low to PSEN Low s TOUGL=25 8
TPLPH | PSEN Pulso With
o751H 190 aToLcL—60 ne
Al Othors 215 STOLCL=35 a8.
TPL | PSEN Low to Vaid inairin
‘a751H $00 sToLot—150 | ns
All Others $25 STOLCL—125 | ne
TPXK | Input net Hold after PSEN | O. 2 ne
"TPXIZ | Input inst Float after PSEN. S ToLGL=20 | ne
TTPXAV | PSEN to Addross Valid % ToLGL—8 im
TAVIV | Addross to Valid instr In
‘751K 287 sTo.ot~160 | ns
Al Others 02 sTouct—115 | ne
TTPLAZ_| PSEN Low to Adsress Float 20 a 20, ne
TALAH | RD Pulse Width 400 eTOLGL— 100 ne
TWwiwe_| WA Pulse Wiath 400 BTOLGL—100 ne
TRLOV | RD Low to Valid Datain 22 BTCLOL—165 | ns
TTRHOX | Data Hold aftr AD o 2 ns
"TRHOZ | Data Float ator FD. a 2roLoL=70 [ns
"TLLDV __[-ALE Low to Vali Data in 517 eToLoL=150 | ns
TAVOV | Address to Valid Data in 685 | ‘TOLOL— 165 | ns
TLLWL | ALELowioRDorWALow | 200 | 900 | sToLoL—s0 | sTc.cL+s0 | “ns
TAVWL_ | Address to RO or WALow | 208 aTOLCL=130 rm
TQVWX | Data Valid to WR Transition
‘O7S1H. 13 ToLoL-70 ns
Al Others 23 ToLCL—60, ns
; TOVWH__| Data Vaid to WA High 483 TTCLOL = 160 ns
i TWHOX__| Data Hold after WA 38 TOLOL=50 8
TTRLAZ | FD Low to Addeoss Float 2 2 nm
TWHLH | FD or WA High to ALE High
‘e751 aa | ts | Touoi-so | Totci+s0 | ns
Al thors 4a__|_i2a_| roucr—ao | rouse | ns
Note:
"This table doesnot inde the 8761-8 AC, cheracestes (soe next pag).
7.49
4INTEL CORP (UP/PRPHLS)
206 D mm 4826175 0079064 3 mm
intel woot PRELIGIGARY
T-49-19-07
ols ony for the e751H-8
A.C, CHARACTERISTICS Ty = 0°C to +70°C; Voc = SV + 10%; Veg = OV;
{ea Gapastenc for Rot, ALE and POEN ~ 100
Load Gepectancs fr Al Othor ulputs = 805
cymal = ‘uM Osctator | _Varlable Oscliator | yang
iain [ax | win Max
T7reLoe | Oscar requnay 38 0 te
TuHuL_| ALE Pulse wan zo FO. rn
TAVLL | Adoss Vato ALE Low | 05 To.ol=40 5
TuLaX | Adoss Hod ator ALE Low | 00 ToLc.=38 nm
Tuuv | ALE Lowro Va nsrin = wTeLGL= 180 [ns
TLLPL | ALE Low to FREN Low 18 TeLoL= a5 m1
TPLPH | FSEN Piso Wan a8 eTeuct=e0 7
TPLUV PSEN Low to Valid Instr In 225 STCLOL—150 | ns
TPH | patina Holder PEN | 0 a =
Tex | Inputs Fost lr PSER 108 ToueL=00_| ne
Thxay | FSEN wo Adress vasa i Taoi=8 m7
Tau —| Adress to Vk sn we wreLci 160 | ns
TPLAZ | PEER Low to Atos oat 2 2 [one
TARA | AO Pulse Wit eo TOLL 109 =
Twi | Pulse wath 0 eTOLGL=100 ry
TALDY _| FO Low Vaid Oatain a ero. | re
TAHOK | ata Hol er FO 3 a im
TAHOZ | Gna Fest ater 1 wreLai—70 | ne
TLLDV | ALE Low o Vad ataln 0 eTo1c.160.| ns
TavOV | Ads o Vat ata a 60 eTOLGL— 165 | ne
TLuLWL | ALELowtoAD or WA Low: 325 425 | sTCLCL—60 | STCLCL+60 | ns
Tay | Adcoss oD or WR Low | —<70 TOL 190, =
TVW | Data Vala to WTranstion | 55 ToLGL=70 =
TavWit_| Data Vaid wo Woh 728 Troi. 180 i
“TWHOK | Daa Hold ater WR ® ToLo.=80 rm
TRLAZ | RD Low wo Adcoss oat A 2 [os
TWHLH | RD or WA High to ALE High 6 475 TOLCL—60 | TOLCL+50 ns
70INTEL CORP (UP/PRPHLS) 206 p mm 4826375 0079085 5 mm
intel cse.st PRELIMINARY
EXTERNAL PROGRAM MENORY READ CYCLE “5 ag. 9.07
751INTEL CORP (UP/PRPHLS)
intel
cs®-s1
EXTERNAL DATA MEMORY READ CYCLE
206 D mm 4826175
0079086 7 mm
PRELIMINARY
T-49-19-07
: -
EXTERNAL DATA MEMORY WRITE CYCLE
mm
KX isi)
782Foe reer TTT
INTEL CORP (UP/PRPHLS) 20€ D WM 4426175 0079087 9
intel a7 PRELIGAIOIARY
T-49-19-07
‘SERIAL PORT TIMING—SHIFT REGISTER MODE
‘Tost Conctons: Ta = °C to 70°C; VOC = BV 10%; VSS = OV; Load Capacitance = 80 pF
symbol = 12 Miz Oscillator Variable Oscllator | urns
Min [Max Min Max
FTxLXL_[ Serial Port Glock Gycle Time 10 s2TCLCL Hs
FTavvxti | Output Data Setup to Glock Rising| 700 toTCLCL— 139] ne
Edge
FTXHOX | Output Data Hold attr Glock cy aroLcL— 7 ne
ising Edge,
FTXHOX | input Data Hold after Cock Rising | 0 ° 18
Edge
FTAHBY | Giock Rising Edge to Input Data 700 voroLci— 193] ve
Val
SHIFT REGISTER TIMING WAVEFORMS:
Se et eo ee |
“UU
ae a
bellow |
a eve
ate acs f I ee
a OBE O BORO REOSGOAOEX
7
7580 Ee
INTEL CORP (UP/PRPHLS) 206 D mm 4s2b175 0079088 om
intel PRELIMIOARY
T-49-19-07
EXTERNAL CLOCK DRIVE i
Symbol Par win [Wor [ Ute
Wrcict | Oxciator Frequency excptaretey | 06 | 12 | wre
arsine 3 3 he
Toe | ia Tne 2 13
ToioK Towne 2 .
ToLot! Fite Te A =
ToHOL Fal Tino 2 1:
EXTERNAL CLOCK DRIVE WAVEFORM
‘AG. TESTING INPUT, OUTPUT WAVEFORM.
we
e.g Fe eee aa
java oge a
754INTEL CORP (UP/PRPHLS) 20E D MH 4826175 0079089 2 mm
intel on PRELIMINARY
T-49-19-07
EPROM CHARACTERISTICS 7
“Table 3. EPROM Programming Modes
Mode [RST ue |X | pay | pas |pas [pea
Progam | 1 o [or | vee | [0 |x |x
int + ° + [ox [ooo x x
Very 1 ° + [ooo x x
Securly Set 1 of [er [a x x
tg Hh for that pa ep" = 421V 208y
‘or = tet oral “AE pte ot 8
Seo ata
Programming the EPROM ‘Not that the ER/VPP pin mus not be allowed to go
‘To be programmed, the part must be running with a
4 to 6 Miz oscillator. (The reason the oscilator
‘Reods to bo running is thatthe internal bus s being
Used to transfer adaress and program data to appro-
priate internal registers) Tho adress of an EPROM
location to bo programmed is applied to Port 1 and
pins P2.0-P2:3 of Port 2, while the cod byto to bo
programmed ino that location I applied to Port 0,
‘The other Port 2 pins, and RST, PSEN, and EA
should be held at th “Program” loves indicated in
Table 3, ALE s pulsed low for 50 ms to program the
code byte into tha addressed EPROM location. The
setup is shown in Figure 8.
‘Normally ER is held at a logis high until just before
‘ALE Is fo bo pulsed, Thon EA le raised to + 21V,
ALE Is pulsed, and thon EA Is roturned to @ loge
bigh. Waveforms and detailed timing spocificaions
‘are shown in later sections of this data sheet.
Figure 6, Programming Configuration
‘above tho maximum specified VPP level of 21.5V for
any amount of ie. Even @ narrow gltch above that
voltage level can cause permanent damage to the
7.55FS EEX’ CSiCSCS~SE OO a,
INTEL CORP (UP/PRPHLS) 20€ PD M 4426175 0075050 9 me
intel _ PRELIMINARY
T-49-19-07
EPROM Security 9 :
‘Tho secur feature consists ofa locking” bit which
‘when programmed denies electrical access by any
external means to the onchip Program Memory.
‘The bit fs programmed as shown in Figure 7. Tha
‘solup and procedure aro the samo as for normal
EPROM programming, except that P26 Is held ata
logic high. Porto, Port 1, and pins P2.0-P2.3 may be
in any stata, The other pins should be held at the
"Security" loves Indicated In Table 3.
‘Onco tho Secuiy it has baen programmed, it can
bo cleared only by full erasure of the Program Mom-
‘ory. While itis programmed, the intanal Program
device can not bo
Rot execute out of
Erasure Characteristics
‘The recommended erasure procedure i expos
"aay of the EPROM bag o ac whgn he eter ig at ss07 agua fan og
1 slight with wavelengths shorter eq dose of at least 18 W-soc/em2. Exposing the
than approximately 4,800 Angstroms, Since sunight EBC wa unsudin ang oF 12000 aiiTone
‘and fluorescent lighting have wavelengths in this rating for 20 to 80 minutes, at a distance of about 1
range, exposure to these light sources over an ex- | faunSor fe 10 So manute
tended time (about 1 week in sunight, of 8 years int
roomaval urescent ight) could cause nadver-
{ont erasuro i an application subjects the device to
this type of exposure, itis suggested that an opaque
labo! be placed over the window.
Erasure leaves the aray in an all ts stato,
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS.
Ta = 21°C 0 27°C; VOC = BY +10%; VSS = OV
Symbol Parameter Win Max Unite
VPP Programming Supply Vliage 205 218 v
PP, Programming Supply Curent 0 mA,
TOLL ‘Osellator Froquancy 4 6 Miz
TAVGL ‘Address Sotup to PROG Low: warcic,
TGHAK ‘Address Hold aftor PROG 4sTOLCL,
TDVGL Data Setup to PROG Low asTolcl.
TGHOX ata Hold after PROG. asToLcl.
TTEHSH P27 (ENABLE) High to VPP ‘asTOLcL
TSHGL \VPP Setup to PROG Low 10 HS
TGHSL VPP Hold after PROG. 10 Hs
TGLGH. PROG With ro 5 ms.
Tavav, ‘Address to Data Valid aeTousL,
TELav [ENABLE Low to Data Vaid 4STOLOL,
TEHOZ Data Float aftor ENABLE, 2 STOLL,
7.56INTEL CORP (UP/PRPHLS) 20€ 9 M@@ 4426175 0079091 0
intel mese.s1 PRELIMINARY
T-49-19-07
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
‘rerrcanion|
For poning conn sa Fe 8 Fo vnoten canto see Fee 8 :
DATA SHEET REVISION SUMMARY
‘Tho following are the key diferences botwean this and the -008 version ofthis data shes:
4. Inoduction was expanded to include product descriptions,
2, Package table was added,
‘8, Design Considerations added,
4, Test Conditions for and ly specifications added to the DC Characteristics.
5, Data Shoot Revision Summary added,
787
i