SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005


 
 
    
 

FEATURES APPLICATIONS
D Operating Input Voltage 2.25 V to 5.5 V D Networking Equipment
D Output Voltage as Low as 0.7 V D Telecom Equipment
D 1% Internal 0.7 V Reference D Base Stations
D Predictive Gate Drivet N-Channel MOSFET D Servers
Drivers for Higher Efficiency D DSP Power
D Externally Adjustable Soft-Start and D Power Modules
Overcurrent Limit
D Fixed-Frequency Voltage-Mode Control DESCRIPTION
− TPS40007, 300 kHz
The TPS4000x are controllers for low-voltage,
− TPS40009, 600 kHz
non-isolated synchronous buck regulators. These
D Source/Sink with VOUT Prebias controllers drive an N-channel MOSFET for the
D 10-Lead MSOP PowerPadt Package for primary buck switch, and an N-channel MOSFET
Higher Performance for the synchronous rectifier switch, thereby
D Thermal Shutdown achieving very high-efficiency power conversion. In
addition, the device controls the delays from main
D Internal Boostrap Diode
switch off to rectifier turn-on and from rectifier
turn-off to main switch turn-on in such a way as to
minimize diode losses (both conduction and
recovery) in the synchronous rectifier with TI’s
proprietary Predictive Gate Drivet technology. The
reduction in these losses is significant and increases
efficiency. For a given converter power level, smaller
FETs can be used, or heat sinking can be reduced
SIMPLIFIED APPLICATION DIAGRAM or even eliminated.

VIN
TPS40007
TPS40009
1 ILIM BOOT 10

2 FB HDRV 9

3 COMP VOUT
SW 8
4 SS/SD
VDD 7

5 GND LDRV 6

UDG−03161

PowerPADt and Predictive Gate Drivet are trademarks of Texas Instruments Incorporated.
 
 
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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

DESCRIPTION (continued)
The current-limit threshold is adjustable with a single resistor connected to the device. The TPS4000x
controllers implement a closed-loop soft start function. Startup ramp time is set by a single external capacitor
connected to the SS/SD pin. The SS/SD pin is also used for shutdown.

ORDERING INFORMATION
TA FREQUENCY PACKAGED DEVICES MSOP(1) (DGQ)
300 kHz TPS40007DGQ
−40°C to 85°C
600 kHz TPS40009DGQ
(1) The DGQ package is available taped and reeled. Add R suffix to device type (e.g.
TPS40007DGQR) to order quantities of 2,500 devices per reel and 80 units per tube.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(2)
TPS4000x UNIT
BOOT VSW + 6.5
COMP, FB, ILIM, SS/SD −0.3 to 6.5
Input voltage range, VIN SW −3 to 10.5 V
SWT (SW transient < 50 ns) −5
VDD 6.5
Operating junction temperature range, TJ −40 to 150
Storage temperature, Tstg −55 to 150 °C
C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260
(2) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DGQ PACKAGE(3)(4)
(TOP VIEW)

ILIM 1 10 BOOT
FB 2 9 HDRV
COMP 3 8 SW
SS/SD 4 7 VDD
GND 5 6 LDRV

ACTUAL SIZE
3,05mm x 4,98mm
(3) See technical brief SLMA002 for PCB guidelines for PowerPAD packages.
(4) PowerPADt heat slug should be connected to GND (pin 5).

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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

ELECTRICAL CHARACTERISTICS
temperature range, TA = −40_C to 85_C, VDD = 5.0 V, TA = TJ; all parameters measured at zero power dissipation
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
VDD Input voltage range 2.25 5.5
V
VHGATE High-side gate voltage VBOOT − VSW 6
Shutdown current SS/SD = 0 V, Outputs off 0.25 0.45
IDD Quiescent current FB = 0.8 V 1.4 2.0 mA
Switching current No load at HDRV/LDRV 1.5 4.0
UVLO Minimum on-voltage 1.95 2.05 2.15 V
Hysteresis 80 150 220 mV
OSCILLATOR
TPS40007 250 300 350
fOSC Oscillator frequency 2.25 V ≤ VDD ≤ 5.00 V kHz
TPS40009 500 600 700
VRAMP Ramp voltage VPEAK − VVALLEY 0.80 0.93 1.07
V
Ramp valley voltage 0.24 0.31 0.44
PWM
TPS40007 87.0% 94.0%
Maximum duty cycle(2) FB = 0 V, VDD = 3.3 V
TPS40009 83.0% 93.0%
Minimum duty cycle 0%
Minimum controllable pulse width(1)(3) 100 150 ns
ERROR AMPLIFIER
Line, Temperature 0.690 0.700 0.711
VFB FB input voltage V
TA = 25°C 0.693 0.700 0.707
IFB FB input bias current 30 130 nA
VOH High-level output voltage FB = 0 V, IOH = 1.0 mA 2.0 2.5
V
VOL Low-level output voltage FB =VDD, IOL = 0.5 mA 0.08 0.15
IOH Output source current COMP = 0.7 V, FB = GND 2 6
mA
IOL Output sink current COMP = 0.7 V, FB = VDD 3 8
GBW Gain bandwidth(1) 5 10 MHz
AOL Open loop gain 55 85 dB
SHORT CIRCUIT CURRENT PROTECTION
ISINK ILIM sink current VDD = 5 V 11 15 19 µA
ISINK ILIM sink current VDD = 2.25 V 9.5 13.0 16.5 µA
VOS Offset voltage SW vs ILIM(1) 2.25 V ≤ VDD ≤ 5.00 −20 0 20 mV
VILIM Input voltage range 2 VDD V
tON Minimum HDRV pulse time in overcurrent VDD = 3.3 V 220 330 ns
SW leading edge blanking pulse in over-
current detection(1) 100 ns

tSS Soft-start capacitor cycles as fault timer(1) 6

(1) Ensured by design. Not production tested.
(2) Derate the maximum duty cycle by 3% for VDD < 3 V
(3) Operating at PWM on-times of less than 100 ns could lead to overlap between HDRV and LDRV pulses.

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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

ELECTRICAL CHARACTERISTICS
temperature range, TA = −40_C to 85_C, VDD = 5.0 V, TA = TJ; all parameters measured at zero power dissipation
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT DRIVER
VBOOT−VSW = 3.3 V,
RHDHI HDRV pull-up resistance ISOURCE = −100 mA 3 5.5

VBOOT − VSW = 3.3 V,

RHDLO HDRV pull-down resistance ISINK = 100 mA 1.5 3 Ω
RLDHI LDRV pull-up resistance VDD = 3.3 V, ISOURCE = −100 mA 3 5.5
RLDLO LDRV pull-down resistance VDD = 3.3 V, ISINK = 100 mA 1.0 2.0
tRLD LDRV rise time 15 35
tFLD LDRV fall time 10 25
CLOAD = 1 nF ns
tRHD HDRV rise time 15 35
tFHD HDRV fall time 10 25
PREDICTIVE DELAY
VSWP Sense threshold to modulate delay time −350 mV
TLDHD Maximum delay modulation range time LDRV OFF − to − HDRV ON 45 70 95
Predictive counter delay time per bit LDRV OFF − to − HDRV ON 2.8 4.3 6.2
ns
THDLD Maximum delay modulation range HDRV OFF − to − LDRV ON 50 80 110
Predictive counter delay time per bit HDRV OFF − to − LDRV ON 3.0 4.8 6.6
SHUTDOWN
VSD Shutdown threshold voltage Outputs OFF 0.21 0.26 0.31
V
VEN Device active threshold voltage 0.25 0.29 0.35
SOFTSTART
ISS Soft-start source current Outputs OFF 2.0 3.7 5.4 µA
VSS Soft-start voltage to begin VOUT start 0.35 0.65 0.95 V
BOOTSTRAP
VDD = 3.3 V 50 100
RBOOT Bootstrap switch resistance Ω
VDD = 5 V 35 70
VOUT PRE-BIAS
Recommended VOUT pre-bias level as
% of final regulation(1)(4) FB percent of 700 mV 90%

SW NODE
ISW Leakage current in shutdown 2 µA
THERMAL SHUTDOWN
tSD Shutdown temperature(1) 165
°C
Restart from thermal shutdown(1) −15
(1) Ensured by design. Not production tested.
(2) Derate the maximum duty cycle by 3% for VDD < 3 V.
(3) Operating at PWM on-times of less than 100 ns could lead to overlap between HDRV and LDRV pulses.
(4) Prebiased output greater than 90% of final regulation may lead to sinking current from the prebias output.

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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

Terminal Functions
TERMINAL
I/O DESCRIPTION
NAME NO.
Provides a bootstrapped supply for the topside MOSFET driver, enabling the gate of the topside
BOOT 10 O
MOSFET to be driven above the input supply rail
COMP 3 O Output of the error amplifier
FB 2 I Inverting input of the error amplifier. In normal operation the voltage at this pin is the internal reference level of 700 mV.
Power supply return for the device. The power stage ground return on the board requires a separate path from other
GND 5 −
sensitive signal ground returns.
This is the gate drive output for the topside N-channel MOSFET. HDRV is bootstrapped to near 2 × VDD for good en-
HDRV 9 O
hancement of the topside MOSFET.
A resistor is connected between this pin and VDD to set up the over current threshold voltage. A 15-µA current sink at
the pin establishes a voltage drop across the external resistor that represents the drain-to-source voltage across the
ILIM 1 I top side N-channel MOSFET during an over current condition. The ILIM over current comparator is blanked for the
first 100 ns to allow full enhancement of the top MOSFET. Set the ILIM voltage level such that it is within 800 mV of
VDD; that is, (VDD − 0.8) ≤ IILIM ≤ VDD.
LDRV 6 O Gate drive output for the low-side synchronous rectifier N-channel MOSFET
Soft-start and overcurrent fault shutdown times are set by charging and discharging a capacitor connected to this pin.
A closed loop soft-start occurs when the internal 3-µA current source charges the external capacitor. There is a 0.65-V
offset between external SS pin and internal soft-start voltage at the error amplifier input. This allows the device to be
SS/SD 4 I enabled before starting VOUT, thus ensuring that VOUT soft starts smoothly. When the SS/SD voltage is less than 0.25
V, the device is shutdown and the HDRV and LDRV are driven low. In normal operation, the capacitor is charged to
VDD. When a fault condition is asserted, the soft-start capacitor goes through six charge/discharge cycles, restarting
the converter on the seventh cycle.
Connect to the switched node on the converter. This pin is used for overcurrent sensing in the topside N-channel
MOSFET, and level sensing for predictive delay circuit. Overcurrent is determined, when the topside N-channel MOS-
SW 8 O
FET is on, by comparing the voltage on SW with respect to VDD and the voltage on the ILIM with respect to VDD.
This pin is also used for the return of the topside N-channel MOSFET driver.
VDD 7 I Power input for the chip, 5.5-V maximum. Decouple close to the pin with a low-ESR capacitor, 1-µF or larger.

FUNCTIONAL BLOCK DIAGRAM

VDD
VDD 7 VDD THERMAL
SHUTDOWN LDRV
UVLO
2V
ERROR AMPLIFIER PWM COMP 10 BOOT
FB 2
+ HI
+
0.7 V UVLO 9 HDRV
OSC CLK PWM PREDICTIVE
REF GATE
0.65 V
DRIVE
COMP 3 PWM
UVLO
3.7 µA LOGIC
(VDD−1.2 V)
SS ACTIVE FAULT 8 SW
SOFT FAULT
SS/SD 4 OC
START COUNTER VDD
DISCHARGE
LO 6 LDRV
0.26 V 100 ns DELAY
SHUT DOWN
EN

GND 5 CURRENT 1 ILIM

LIMIT COMP
15 µA

UDG−03162

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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

APPLICATION INFORMATION

The TPS4000x series of synchronous buck controller devices is optimized for high-efficiency dc-to-dc
conversion in non-isolated distributed power systems. A typical application circuit is shown in Figure 1.
The TPS40007 and TPS40009 are the controllers of choice for general-purpose synchronous buck designs.
They are designed to startup into applications where the output voltage is pre-biased, and without having the
synchronous rectifier interfere with the pre-bias condition. PWM pulses are enabled when the soft-start voltage
crosses the feedback level dictated by the pre-bias output. Moreover, the pre-biased output ramps up smoothly
from its pre-bias value and into regulation.

VDD
3.0 V to 5.5 V 100 µF 10 µF

20 kW

TPS40007

1 ILIM BOOT 10
Si4866DY

2 FB HDRV 9
IHLP5050CE−01 VOUT 1.8 V
3.6 nF 7.68 kΩ 10 A
100 nF
3 COMP SW 8

470 µF 10 µF 243 Ω
100 pF 4 SS/SD VDD 7 Si4866DY
4.7 nF 15.7 kΩ
3.3 nF
5 GND LDRV 6

10 kΩ

UDG−03159

Figure 1. Typical Application Circuit

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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

APPLICATION INFORMATION

ERROR AMPLIFIER
The error amplifier has a bandwidth of greater than 5 MHz, with open loop gain of at least 55 dB. The COMP
output voltage is clamped to a level above the oscillator ramp in order to improve large-scale transient response.

OSCILLATOR
The oscillator uses an internal resistor and capacitor to set the oscillation frequency. The ramp waveform is a
sawtooth at the PWM frequency with a peak voltage of 1.25 V, and a valley of 0.31 V. The PWM duty cycle is
limited to a maximum of 94%, allowing the bootstrap capacitor to charge during every cycle.

BOOTSTRAP/CHARGE PUMP
There is an internal switch between VDD and BOOT. This switch charges the external bootstrap capacitor for
the floating supply. If the resistance of this switch is too high for the application, an external schottky diode
between VDD and BOOT can be used. The peak voltage on the bootstrap capacitor is approximately equal to
VDD.

DRIVER
The HDRV and LDRV MOSFET drivers are capable of driving gate-to-source voltages up to 5.5 V. At VIN, = 5 V
and using appropriate MOSFETs, a 20-A converter can be achieved. The LDRV driver switches between VDD
and ground, while the HDRV driver is referenced to SW and switches between BOOT and SW.

SYNCHRONOUS RECTIFICATION AND PREDICTIVE DELAY

In a normal buck converter, when the main switch turns off, current is flowing to the load in the inductor. This
current cannot be stopped immediately without using infinite voltage. In order to provide a path for current to
flow and maintain voltage levels at a safe level, a rectifier or catch device is used. This device can be either a
conventional diode, or it can be a controlled active device if a control signal is available to drive it. The TPS4000x
provides a signal to drive an N-channel MOSFET as a rectifier. This control signal is carefully coordinated with
the drive signal for the main switch so that there is minimum delay from the time that the rectifier MOSFET turns
off and the main switch turns on, and minimum delay from when the main switch turns off and the rectifier
MOSFET turns on. This scheme, Predictive Gate Drivet delay, uses information from the current switching
cycle to adjust the delays that are to be used in the next cycle. Figure 2 shows the switch-node voltage waveform
for a synchronously rectified buck converter. Illustrated are the relative effects of a fixed-delay drive scheme
(constant, pre-set delays for the turn-off to turn-on intervals), an adaptive delay drive scheme (variable delays
based upon voltages sensed on the current switching cycle) and the predictive delay drive scheme.
Note that the longer the time spent in diode conduction during the rectifier conduction period, the lower the
efficiency. Also, not described in Figure 2 is the fact that the predictive delay circuit can prevent the body diode
from becoming forward biased at all. This results in a significant power savings when the main MOSFET turns
on, and minimizes reverse recovery loss in the body diode of the rectifier MOSFET.

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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

APPLICATION INFORMATION

GND

Channel Conduction

Body Diode Conduction

Fixed Delay
Adaptive Delay
Predictive Delay UDG−03166

Figure 2. Switch Node Waveforms for Synchronous Buck Converter

SHORT CIRCUIT PROTECTION

Overcurrent conditions in the TPS4000x are sensed by detecting the voltage across the main MOSFET while
it is on.
Basic Description
If the voltage exceeds a pre-set threshold, the current pulse is terminated, and a counter inside the device is
incremented. If this counter fills up, a fault condition is declared and the device disables switching for a period
of time and then attempts to restart the converter with a full soft-start cycle.

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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

APPLICATION INFORMATION

Detailed Description
During each switching cycle, a comparator looks at the voltage across the top side MOSFET while it is on. This
comparator is enabled after the SW node reaches a voltage greater than (VDD−1.2 V) followed by a 100-ns
blanking time. If the voltage across that MOSFET exceeds the programmed voltage, the current-switching pulse
is terminated and a 3-bit counter is incremented by one count. If, during the switching cycle, the topside
MOSFET voltage does not exceed a preset threshold, then this counter is decremented by one count. (The
counter does not wrap around from 7 to 0 or from 0 to 7). If the counter reaches a full count of 7, the device
declares that a fault condition exists at the output of the converter. In this fault state, HDRV and LDRV are turned
off, and the soft-start capacitor is discharged. LDRV is maintained OFF during fault timeout to effectively support
pre-bias applications. The counter is decremented by one by the soft start capacitor (CSS) discharge. When the
soft-start capacitor is fully discharged, the discharging circuit is turned off and the capacitor is allowed to charge
up at the nominal charging rate. When the soft-start capacitor reaches approximately 1.3 V, it is discharged
again and the overcurrent counter is decremented by one count. The capacitor is charged and discharged, and
the counter decremented until the count reaches zero (a total of six times). When this happens, the outputs are
again enabled as the soft-start capacitor generates a reference ramp for the converter to follow while attempting
to restart.
During this soft-start interval (whether or not the controller is attempting to do a fault recovery or starting for the
first time), pulse-by-pulse current limiting is in effect, but overcurrent pulses are not counted to declare a fault
until the soft-start cycle has been completed. It is possible to have a supply attempt to bring up a short circuit
for the duration of the soft start period plus seven switching cycles. Power stage designs should take this into
account if it makes a difference thermally. Figure 3 shows the details of the overcurrent operation.

(+) VTS (−)

Internal PWM Short Circuit Protection

Threshold Voltage

VTS
0V

External
Main Drive
Normal Overcurrent
Cycle Cycle UDG−03165

Figure 3. Short Circuit Operation

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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

APPLICATION INFORMATION

Figure 4 shows the behavior of key signals during initial startup, during a fault and a successfully fault recovery.
At time t0, power is applied to the converter. The voltage on the soft-start capacitor (VCSS) begins to ramp up.
At t1, the soft-start period is completed and the converter is regulating its output at the desired voltage level.
From t0 to t1, pulse-by-pulse current limiting is in effect, and from t1 onward, overcurrent pulses are counted
for purposes of determining a possible fault condition. At t2, a heavy overload is applied to the converter. This
overload is in excess of the overcurrent threshold. The converter starts limiting current and the output voltage
falls to some level depending on the overload applied. During the period from t2 to t3, the counter is counting
overcurrent pulses, and at time t3 reaches a full count of 7. The soft-start capacitor is then discharged, the
counter is decremented, and a fault condition is declared.

VDD

VCSS
~ 1.3 V
~ 0.6 V 0.6 V

FAULT

ILOAD

VOUT
t
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

COUNTER 0 6 5 4 3 2 1 0

1 2 3 4 5 6 7
UDG−03160

Figure 4. Overcurrent/Fault Waveforms

When the soft start capacitor is fully discharged, it begins charging again at the same rate that it does on startup,
with a nominal 3.7-µA current source. When the capacitor voltage crosses 1.3 V, it is discharged again and the
counter is decremented by one count. These transitions occur at t3 through t9. Not shown in Figure 4 is that
between t3 and t9, LDRV is maintained OFF. At t9, the counter has been decremented to 0. The fault logic is
then cleared, the outputs are enabled, and the converter attempts to restart with a full soft-start cycle. The
converter comes into regulation at t10.

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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

APPLICATION INFORMATION

SETTING THE CURRENT LIMIT

Connecting a resistor from VDD to ILIM sets the current limit. A 15-µA current sink internal to the device causes
a voltage drop at ILIM that becomes the short circuit threshold. Ensure that (VDD−0.8 V) ≤ VILIM ≤ VDD. The
tolerance of the current sink is too loose to do an accurate current limit. The main purpose is for hard fault
protection of the power switches. Given the tolerance of the ILIM sink current, and the RDS(on) range for a
MOSFET, it is generally possible to apply a load that thermally damages the converter. This device is intended
for embedded converters where load characteristics are defined and can be controlled.
A local capacitor (with a value 50 pF to 150 pF) placed across the resistor between VDD and ILIM may improve
coupling a common mode noise between VDD and ILIM.

SOFT-START AND SHUTDOWN

These two functions are combined on the SS/SD pin. There is a VBE offset (0.65-V) between the external SS/SD
pin and internal soft-start voltage at the error amplifier input, allowing the device to be enabled before starting
VOUT as shown in Figure 5. This reduces the transient current required to charge the output capacitor at startup,
and allows for a smooth startup with no overshoot of the output voltage.

SS/SD
(200 mV/ div)

FB
(200 mV/ div)

t − Time − 1 ms/div

Figure 5. Offset Between SS/SD and FB at Startup

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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

APPLICATION INFORMATION

A shutdown feature can be implemented as shown in Figure 6. The device shuts down when the voltage at the
SS/SD pin falls below 260 mV. Because of this limitation, it is recommended that a MOSFET be used as the
controlling device, as in Figure 6. During shutdown, the total leakage current on the SW pin (ISW) is less than
2 µA. When VSS/SD is greater than 290 mV, the device is enabled with normal SW active bias currents.

TPS40007/9

3.7 µA

SS/SD
ERROR AMPLIFIER
4
+
0.7 V + COMP
C SS R FB
SHUTDOWN

SDN
0.26 V +
UDG−01163

Figure 6. Shutdown Implementation

Long soft start times may experience extended regions where the PWM pulse width is less than 100 ns. This
could lead to momentary overlap between HDRV and LDRV. As a result, there is a momentary increase in
ground or supply noise. It is important to ensure that the ground return of the synchronous rectifier be connected
directly to the ground return of the input bank of bypass capacitors, in order to minimize ground noise from
interfering with the controller during soft start. Also, if an external shutdown transistor is used in the application,
it is important to place a local bypass capacitor between its gate and source on the board in order to minimize
noise from interfering with the controller during soft-start.

OUTPUT PRE-BIAS
The TPS4000x supports pre-biased VOUT voltage applications. In cases, where the VOUT voltage is held up by
a pre-biasing supply while the controller is off, full synchronous rectification is disabled during the initial phase
of soft starting the VOUT voltage. When the first PWM pulses are detected during soft-start, the controller slowly
activates synchronous rectification by starting the first LDRV pulses with a narrow on-time. It then increments
that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1−D), where D is the duty cycle
of the converter. This scheme prevents the initial sinking the pre-bias output, and ensures that the VOUTvoltage
starts and ramps up smoothly into regulation. Note, if the VOUT voltage is pre-biased, PWM pulses start when
the error amplifier soft-start input voltage rises above the commanded FB voltage.
Figure 7 depicts the waveforms of the HDRV and LDRV output signals at the beginning PWM pulses. When
HDRV turns off, diode rectification is enabled. Before the next PWM cycle starts, LDRV is turned on for a short
pulse. With every cycle, the leading edge of LDRV is modulated, and the on-time of the synchronous rectifier
is increased. Eventually, the leading edge of LDRV coincides with the falling edge of HDRV to achieve full
synchronous rectification.
At most, synchronous rectifier modulation takes place for the first 128 cycles after PWM pulses start. Note that
during the synchronous rectifier modulation region, the controller monitors pulse skipping. If the main HDRV
skips a pulse, the controller also skips a LDRV pulse. Pulse skipping could be experienced if the loop response
is much faster than the commanding soft-start ramp, especially when soft start times are long. The output
voltage ratchets up as the soft-start ramp catches up to it. Appropriate setting of loop response curbs this effect.
During normal regulation of the VOUT voltage, the controller operates in full two-quadrant source/sink mode.

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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

APPLICATION INFORMATION

Figure 8 shows startup waveforms of a 1.2-V VOUT voltage under different pre-bias scenarios. The first trace
is when the output voltage starts with zero pre−bias. The second and third traces, respectively, the pre-bias
levels are 0.5 V and 1.0 V.

VIN = 5 V
VOUT = 1.2 V
(200 mV/div)

PREBIAS = 1 V

VHDRV
PREBIAS = 0.5 V

VLDRV PREBIAS = 0 V

t − Time − 2 µs/div t − Time − 500 µs/div

Figure 7. Figure 8.
MOSFET Drivers at Beginning of Soft-Start Startup Waveforms

The recommended VOUT voltage pre-bias range is less than or equal to 90% of final regulation. That is, a
pre-bias level between 90% and 100% of final regulation could lead to sinking the pre-bias supply. If the VOUT
voltage is initially set to higher than 100% of final regulation, the controller forces sinking current at the end of
soft-start in order to bring the output quickly into regulation.
The following pages include design ideas for a few applications. For more ideas, detailed design information,
and helpful hints, visit the TPS40000 resources at http://power.ti.com.

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SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

APPLICATION INFORMATION

VDD
3.3 V 22 µF 22 µF

15 kΩ TPS40009

1 ILIM BOOT 10 FDS6894A

2 FB 9 1.0 µH
HDRV
1 nF 8.66 kΩ 1 µF VOUT
1.2 V
3 COMP SW 8 5A
2.2 Ω
22 µF 22 µF
68 pF 4 SS/SD VDD 7 FDS6894A
4.7 nF
5 GND LDRV 6
0.0033 µF
PWP 1 µF

12.1 kΩ
470 pF
1 kΩ

16.9 kΩ

UDG−03164

Figure 9. Small-Form Factor Converter for 3.3 V to 1.2 V at 5 A.

14 www.ti.com
 VDD

3.3 V

+ + 22 µF
22 µF 22 µF
330 µF 330 µF 11 kΩ

TPS40007 Si4866DY
1 µF
1 ILIM BOOT 10

1.5 µH
2 FB HDRV 9
2.2 nF 6.19 kΩ
VOUT
3 COMP 8 1.2 V
SW
10 A
2.2 Ω
22 µF 22 µF 22 µF 22 µF
4 SS/SD VDD 7

www.ti.com
82 pF
Si4866DY
10 nF
4.7 nF 5 GND LDRV 6
PWP 1 µF
10 kΩ
APPLICATION INFORMATION

1200 pF
392 Ω

14 kW

Figure 10. High-Current Converter for 3.3 V to 1.2 V at 10 A.

UDG−04014
SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005





15




SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

APPLICATION INFORMATION

VDD
BAT54 22 µF 22 µF
2.5 V
15 kΩ
FDS6894A
TPS40009
1 µF
1 ILIM BOOT 10

2 FB HDRV 9 1.0 µH VOUT

L1 1.2 V
1500 pF 5.62 kΩ 5A
3 COMP SW 8

2.2 Ω
4 SS/SD VDD 7
100 pF 22 µF 22 µF
4.7 nF
FDS6894A
5 GND LDRV 6
PWP 3.3 nF
1 µF

6.19 kΩ

536 Ω 1000 pF

8.66 kΩ
UDG−04028

Figure 11. Ultra-Low-Input Voltage Converter for 2.5 V to 1.2 V at 5 A

16 www.ti.com




SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

APPLICATION INFORMATION

VIN = 3.3 V

1
2 + +
J1 3 C5
C2 C3 C4
C1 22 µF
4 330 µF 330 µF 22 µF 22 µF

R2 C6
16.2 kΩ TPS40007DGQ 1 µF
Q1
1 ILIM BOOT 10 Si4866DY
L1
1.0 µH
2 FB HDRV 9 VOUT = 2.5 V
C7 R4
1.5 nF 5.9 kΩ 10 A
3 COMP SW 8 1
R3
Q2 2.2 Ω + + 2
4 SS/SD VDD 7 Si4866DY 3 J2
C11 C13 C8 C9
C12 4
180 pF 4.7 nF 470 µF 470 µF
5 GND LDRV 6 10n F
C14
PWP
1 µF
R6
10 kΩ

R7 C15
698 Ω 6.8 nF

R8
3.92 kΩ

UDG−03169

Figure 12. TPS40007EVM−001 Ultra-High-Efficiency Converter for 3.3 V to 2.5 V at 10 A

www.ti.com 17




SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

APPLICATION INFORMATION

Layout Considerations
Successful operation of the TPS4000x controllers is dependent upon proper converter layout and grounding
techniques. High current returns for the SR MOSFET’s source, and ground connection of the input and output
capacitors, should be kept on a single ground plane. Bypassing capacitors at the device should return closely
to the GND (pin 5) of the device. The GND (pin 5) and PowerPAD should connect together at the device and
return to the main ground plane.
Proper operation of the Predictive Gate Drive circuits is dependent upon detecting low-voltage thresholds on
the SW node. To ensure that the signal at the SW pin accurately represents the voltage at the main switching
node, the connection from SW (pin 8) to the main switching node of the converter should be kept as short and
as wide as possible. If the SW trace should traverse multiple board layers between the device and the
MOSFETs, multiple vias should be used.
Gate drive outputs, LDRV and HDRV, should be kept as short as possible to minimize inductances of the traces.
While the controller does not require the usage of external resistors between the driver pins and the gates of
the MOSFETs, adding small resistors in series with very high gate charge MOSFETs could minimize the effects
of high frequency ringing.
The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. The circuit
board must have an area of solder-tinned-copper underneath the package. The dimensions of this area depend
on the size of the PowerPAD package (See Thermal Pad Mechanical Data on page 21)

18 www.ti.com




SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

TYPICAL CHARACTERISTICS

OSCILLATOR FREQUENCY PERCENT CHANGE OSCILLATOR FREQUENCY PERCENT CHANGE

vs vs
INPUT VOLTAGE TEMPERATURE
6 1

∆fOSC − Change in Oscillator Frequency − %

∆fOSC − Change in Oscillator Frequency − %

5 0

−1
4

−2
3
−3
2
−4

1
−5

0 −6
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 −50 −25 0 25 50 75 100 125
VIN − Input Voltage − V Temperature − °C
Figure 13 Figure 14

FEEDBACK VOLTAGE FEEDBACK VOLTAGE

vs vs
INPUT VOLTAGE TEMPERATURE
0.7010 0.707

0.705
VFB − Feedback Voltage − V

0.7005
VFB − Feedback Voltage − V

0.703

0.701
0.7000
0.699

0.697
0.6995

0.695

0.6990 0.693
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 −50 −25 0 25 50 75 100 125
VIN − Input Voltage − V Temperature − °C

Figure 15 Figure 16

www.ti.com 19




SLUS589B− NOVEMBER 2003 − REVISED FEBRUARY 2005

TYPICAL CHARACTERISTICS

CURRENT LIMIT SINK CURRENT CURRENT LIMIT SINK CURRENT

vs vs
INPUT VOLTAGE TEMPERATURE
15.5 16.0

15.0
ILIMIT − Sink Current Limit − µA

ILIMIT − Sink Current Limit − µA

15.5

14.5

14.0 15.0

13.5

14.5
13.0

12.5 14.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 −50 −25 0 25 50 75 100 125

VIN − Input Voltage − V Temperature − °C

Figure 17 Figure 18

SHORT CIRCUIT PROTECTION

SS/SD Node

SW Node

t − Time − 1 ms/div
Figure 19

20 www.ti.com
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS40007DGQ ACTIVE HVSSOP DGQ 10 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 40007

TPS40007DGQG4 ACTIVE HVSSOP DGQ 10 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 40007

TPS40007DGQR ACTIVE HVSSOP DGQ 10 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 40007

TPS40007DGQRG4 ACTIVE HVSSOP DGQ 10 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 40007

TPS40009DGQ ACTIVE HVSSOP DGQ 10 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 40009

TPS40009DGQG4 ACTIVE HVSSOP DGQ 10 80 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 40009

TPS40009DGQR ACTIVE HVSSOP DGQ 10 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 40009

TPS40009DGQRG4 ACTIVE HVSSOP DGQ 10 2500 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 85 40009

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jul-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS40007DGQR HVSSOP DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TPS40009DGQR HVSSOP DGQ 10 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jul-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS40007DGQR HVSSOP DGQ 10 2500 364.0 364.0 27.0
TPS40009DGQR HVSSOP DGQ 10 2500 364.0 364.0 27.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
TM
DGQ 10 PowerPAD HVSSOP - 1.1 mm max height
3 x 3, 0.5 mm pitch PLASTIC SMALL OUTLINE

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224775/A

www.ti.com
 PACKAGE OUTLINE
DGQ0010D SCALE 3.700
PowerPAD TM - 1.1 mm max height
PLASTIC SMALL OUTLINE

C
5.05
TYP SEATING PLANE
4.75

A PIN 1 ID
AREA 0.1 C

8X 0.5
10
1

3.1
2.9 2X
NOTE 3 2

5
6 0.27
10X
0.17
3.1 0.08 C A B 1.1 MAX
B
2.9
NOTE 4

0.23
TYP
0.13

SEE DETAIL A

EXPOSED
THERMAL PAD

4
5
0.25
GAGE PLANE
1.89
1.69

0.15
0.7 0.05
8 0 -8 0.4
1
DETAIL A
1.83 TYPICAL
1.63

4218842/A 01/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA-T.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGQ0010D PowerPAD TM - 1.1 mm max height
PLASTIC SMALL OUTLINE

(2.2)
NOTE 9
(1.83) SOLDER MASK
SOLDER MASK DEFINED PAD
OPENING
SEE DETAILS
10X (1.45)
10X (0.3)
1
10

(1.3)
TYP (1.89)
SYMM SOLDER MASK
OPENING
8X (0.5) (3.1)
NOTE 9

5 6

(R0.05) TYP

( 0.2) TYP SYMM METAL COVERED

VIA BY SOLDER MASK
(1.3) TYP

(4.4)

LAND PATTERN EXAMPLE

SCALE:15X

SOLDER MASK METAL UNDER SOLDER MASK

OPENING METAL
SOLDER MASK OPENING

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4218842/A 01/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
DGQ0010D PowerPAD TM - 1.1 mm max height
PLASTIC SMALL OUTLINE

(1.83)
BASED ON
0.125 THICK
STENCIL
10X (1.45)
10X (0.3)
1
10

(1.89)
SYMM BASED ON
0.125 THICK
8X (0.5) STENCIL

5
6
(R0.05) TYP
SEE TABLE FOR
SYMM DIFFERENT OPENINGS
METAL COVERED FOR OTHER STENCIL
BY SOLDER MASK THICKNESSES
(4.4)

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:15X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.05 X 2.11
0.125 1.83 X 1.89 (SHOWN)
0.150 1.67 X 1.73
0.175 1.55 X 1.60

4218842/A 01/2019

NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

www.ti.com
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