Program block:-

● Testbench code is written in program block(program testbench_name

endprogram)
● A program cannot have any hierarchy such as instances of modules, interfaces, or other
programs.
● We cannot put always block in program block.
● In SystemVerilog, routines still use static storage by default, for both modules and
program blocks. But program blocks(and their routines) use automatic storage by putting
the automatic keyword in the program statement.
● The program block, running in the Reactive region, retriggers the Active region during
the same time slot.

Clocking block:-
● specify the timing of synchronous signal signals relative to the clocks.
● Mainly used by testbenches
● single clock expression in each clocking block
○ @(posedge clk) for a single edge clock
○ @(clk) for DDR clock
● signals are always synchronous and can be declared as logic and wire. But use logic
datatype to avoid compiler multiple structure datatype error and verbosity of code.

Now comparison point:

If our DUT has races like

1. Erroneous use of blocking assignments for sequential logic. You have a race within your
DUT regardless of the race between our testbench and DUT.

2. Erroneous use of non-blocking assignments in combinational gated clock logic. You may
have a race within your DUT regardless of the race between our testbench and DUT.

3. The races caused by non-zero delay skews introduced by gate-level propagation.

But as a user if we don't know about the races in between the DUT we face the same races in
testbenches.

SystemVerilog also introduces the program block to hold your testbench and to reduce race
conditions between the device under test and the testbench. From above mentioned three
races, program block only solve the first two. So It gives only a false sense of security of race-
free testbench.

With a clocking block in an interface, our testbenches will drive and sample design signals
correctly relative to the clock. Using a clocking block by itself takes care of the same testbench
to DUT races that a program block addresses, plus it takes care of the races caused by non-
zero delay skews introduced by gate-level propagation. It does this by the use of the input
skews for sampling and output skews for driving.