THE SR FLIP-FLOP

EXPERIMENT NO. 10

I. OBJECTIVES
• To demonstrate the operation and characteristic of a set reset flip-flop

II. MATERIALS
7400
Digital trainer
Solid hookup connecting wires

III. PROCEDURE

1.1 The 7400 SR Flip-flop

1.1.1 Mount the 7400 IC on the breadboard
1.1.2 Refer to Figure 1.1 for the connection
1.1.3 Complete Table 1.1

1.2 The 7400 SR Flip-Flop with enable input

1.2.1 Mount the 7400 IC on the breadboard
1.2.2 Refer to Figure 1.2 for the connection
1.2.3 Complete Table 1.1

IV. EXPERIMENTAL CIRCUIT FOR EXPERIMENT NO.1

D1 D2

Figure 1.1
IN1 IN2

D1 (S)

D2 (R)
D3
V. DATA AND RESULTS TABLE 1.1 IN2

Figure 1.2
IN1

Inputs Outputs

D1 D2 IN1 IN2

TABLE 1.2
Inputs D3=0 D3=1

D1 D2 IN1 IN2 IN1 IN2

0 0

0 1

1 0

1 1

VI. PROBLEMS
For Figure 1.1
1. What input signals are needed to produce a high across IN1?
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What input signals are needed to produce a high output across IN2?
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3. What are the output signals (IN1/IN2) when both are zero?
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For Figure 1.2

4. What happens to the output when the clock input is low?
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What happens to the output when the clock input is high?
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