Objectives

● Design and Implement the microcode sequencer

● Learn to use the microassembler
● Write some simple microcode to test your system.
 Procedure
● Download the 'microcode_rom_example.asm' file
● This file contains a template for the microcode we will use.
● Place this file in your project directory
● From a Command prompt
● 'cd' into the project directory where the microassembler and the
example file are.
● Run the assembler on the example file:
.\uasm microcode_rom_example.asm
 Procedure
● If all goes well, the assembler will create the following files:
microcode_rom_example.lst
microcode_rom_example.mif
microcode_rom_example.v
microcode_rom_example.vhd
 Procedure
● Each of the files has a specific purpose:
● .lst – Listing of your assembled file.
● .mif – Memory information file to load into the online
microarchitecture simulator.
● .v – Verilog implementation of the ROM.
● .vhd – VHDL implemenation of the ROM.
 Procedure
● If you edit the microcode_rom_example.asm file:
● You will need to run uasm on it again to re-generate the .v and .vhd
files.
● You will also have to recompile the resulting .v or .vhd file in
Modelsim.
 Procedure
● Copy your ALU and REGFILE code into the project, along with
their respective test benches.
● Use the provided cpu.v or cpu.vhd template which
implements the datapath shown on the following slide.
● To complete this lab, you should only have to modify code in the
cpu.v, cpu.vhd, and the microcode_rom_example.asm files.
● NOTE: If your ALU and register file don't pass all the vectors in the
testbenches supplied, your full CPU might not work well.
Procedure – Diagram of Data Path
NOTE:
DMUX allows the register file to
be fed from a the data field of the DATA DATA_I
microcode ROM. IR LDIR
RFMUX allows the register file to
be controlled by bits in the fetched DMUX 1 0
instruction.

RFMUX
REGFILE RIN DIN

ASEL
BSEL 0
ASEL NOTE:
DSEL
BSEL Microcode control
1 DSEL fields are
IR[8:0]
highlighted in BOLD

RST RST
CLK CLK
Processor
ABUS BBUS
Status
LDMAR MAR Flags
ABUS BBUS
Z UPZ
ALU ABU BBU
FSEL FSEL S S S
Z,S,C,V UPS
C CIN
FOUT C UPC

FOUT V UPV

DATA_O
 Procedure – Verilog
● Your Verilog version of the processor should include the
following files in the project:
● test_cpu.v
● ram.v
● regfile.v
● alu.v
● cpu.v
● microcode_rom_example.v
 Procedure – VHDL
● Your VHDL version of the processor should include the following
files in the project:
● test_cpu.vhd
● ram.vhd
● regfile.vhd
● alu.vhd
● cpu.vhd
● microcode_rom_example.vhd
Procedure – Module Hierarchy

TEST_CPU

RAM CPU

REGFILE ALU MICROCODE_ROM

 Procedure
● Using a combination of sequential and combinational blocks
build the control logic for the CAR, and the muxes.
● These blocks belong in the cpu.v and cpu.vhd files.
 Procedure – CAR block
● The block sensitive to the rising edge of the CLK should:
● Reset CAR to 0 when RST is asserted low.
● Increment CAR when MUX2 output is '0'
● Load the value of the output of MUX1 when MUX2 output is '1'
● When implementing this block take care to ensure that you don't
accidentally infer pipeline flip flops.
● This happens if you use a reg/signal as an intermediate result inside
the clocked block.
 Procedure – MUX1 and MUX2
● The combinational block(s) should implement:
● MUX1 – The output should be the DATA field from the microcode ROM
when the MUX1 signal is '0', or the EXT_ADDR input when the MUX1
signal is '1'.
● MUX2 – The output should be a selection from the list of status bits
and constant values based on the MUX2 output from the microcode
ROM. (See next slide for truth table)
● In Verilog, be sure to use the blocking assignment operator '=' in
combinational blocks.
● Make sure all input signals appear in the sensitivity list.
 Procedure – MUX2 Truth Table
MUX2 Selection Output Comment
0000 0 NEXT – Unconditionally advance CAR
0001 1 LAD – Load CAR from MUX1 output
0010 C LC – Load CAR when Carry flag is set
0011 C LNC – Load CAR when Carry flag is not set
0100 Z LZ – Load CAR when Zero flag is set
0101 Z LNZ – Load CAR when Zero flag is not set
0110 S LS – Load CAR when Sign flag is set
0111 S LNS – Load CAR when Sign flag is not set
1000 V LV – Load CAR when Overflow flag is set
1001 V LNV – Load CAR when Overflow flag is not set
1010 S⊕V LLT – Load on S XOR V, Signed less than
1011 S⊕V LGE – Load on NOT(S XOR V), Signed Greater than or equal
1100 - Reserved – Available for your use
1101 - Reserved – Available for your use
1110 - Reserved – Available for your use
1111 - Reserved – Available for your use
 Procedure
● Most of the logic for the data path is already present in the
template file in the course shell.
● You only need to implement the code for:
– The CAR
– MUX 1
– MUX 2
 Procedure

CTL
Control Control MUX1

MUX1
Address Memory MUX2
Reg. 2048 x 44 DATA
EXT_ADDR MISC
(CAR) (ROM)
UPDF

MUX2_OUT
MUX2

ASEL
DATA_I BSEL
0 1 C C Z Z S S V V DSEL
FSEL
Data
Status Bits Path

DATA_O
 Procedure
● Use the simple test bench from the course shell that instantiates
your CPU.
● The supplied test bench does nothing except to supply a clock and a
reset pulse to the module.
● It stops after a few dozen clock pulses. You can add more if you need
to.
● With the microcode ROM in place, the microcode engine will
start executing microcode.
● Your test vectors should be microcode programs that execute.
 Evaluation – Control Logic
● Basic Outcomes (55% to 70%)
● You have instantiated all the sub modules and built the blocks.
● Minimum marks for code that has a simple test bench, and CPU code
that compiles.
● Maximum marks for code that successfully executes the microcode
that is present in the example ROM file.
 Evaluation – Control Logic
● Intermediate Outcomes (70% to 80%)
● Basic outcomes fully met.
● Minimum marks for simple modifications to the microcode that try one
of the other MUX2 inputs.
● Maximum marks for modifications to the microcode that test all
conditionals on MUX2
 Evaluation – Control Logic
● Advanced Outcomes (80% - 100%)
● Basic and Intermediate outcomes fully met.
● Marks earned for:
– Implementing testing for the EXT_ADDR input
– Full testing of all condition codes (Note: the UPDF field should cause the
processor status flags to update when the respective bit is '1'. That is if the 'C'
bit is set, synchronously update 'C' with 'COUT'.)
– Creating a non-trivial piece of code that implements some kind of processing
with the microcode.