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LVDS Data Outputs For High-Speed Analog - Analog Devices - Inc
LVDS Data Outputs For High-Speed Analog - Analog Devices - Inc
APPLICATION NOTE
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Analog-to-digital converter (ADC) sample rates have Differential signaling also has the well-known common-
been increasing steadily for years to accommodate mode rejection benefit. Noise that is coupled to the
newer bandwidth-hungry applications in communication, signals tends to be common to both signal paths and
instrumentation, and consumer markets. Coupled with cancelled out by a well designed differential receiver.
the need to digitize signals early in the signal chain to LVDS outputs are current output stages requiring a 100 W
take advantage of digital signal processing techniques, terminating resistor at the receiver, differing from
this has motivated the development of high-speed ADC CMOS outputs that generally do not require termina-
cores that can digitize at greater than 100 MHz to tion. The current output results in a fixed dc load current
200 MHz clock rates with 8- to 12-bit resolution. on the output supplies—avoiding current spikes on the
supply that can couple to the sensitive analog front end.
In standalone converters, the ADC needs to be able to
drive receiving logic and accompanying PCB trace capaci-
OUT+
tance. Current switching transients due to driving the
LVDS LVDS
load can couple back to the ADC analog front end, DRIVER 100 RECEIVER
OUT–
adversely affecting performance. One approach to mini-
mize this effect has been to provide the output data at REQUIRED
one-half the clock rate by multiplexing two output ports, TERMINATION
RESISTOR
reducing required edge rates, and increasing available
settling time between switching instants. The Figure 2. LVDS Requires Far End Termination
AD9054A, AD9884, AD9410, and AD9430 are
recent examples. STANDARDS
Two standards have been written to define LVDS. One is
A new approach to providing high-speed data outputs the ANSI/TIA/EIA-644 which is titled, ”Electrical Charac-
while minimizing performance limitations in ADC applica- teristics of Low Voltage Differential Signaling (LVDS)
tions is the use of LVDS (low voltage differential Interface Circuits.” The other is IEEE Standard 1596.3
signaling). ADI is incorporating LVDS output capability which is titled, ”IEEE Standard for Low-Voltage Differen-
in a new 170 MSPS, 12-bit ADC—the AD9430—and will tial Signals (LVDS) for Scalable Coherent Interface
include LVDS in some of its future high-speed ADCs and (SCI).” A brief summary of these two standards is
DACs (digital-to-analog converters). provided below.
LVDS is, as the name says, a low voltage differential ANSI/TIA/EIA-644
signaling scheme. The operative words here are low The ANSI/TIA/EIA Standard was developed under the
voltage (~350 mV) and differential. Standards bodies Telecommunications Industry Association (TIA) Subcom-
have developed specifications that will be discussed mittee TR-30.2 and contains only generic electrical
later in this note. Lower voltage signal swings have the specifications for LVDS. Its purpose was to create a
intrinsic advantage of shorter switching times as well as general high-speed interface standard for use in point-
reduced EMI concerns (adjacent differential traces tend to-point connections between data communications
to cancel each others’ EMI). equipment. The maximum data signaling rate is 655
Mbps. The TIA Subcommittee intended other
standards bodies to reference ANSI/TIA/EIA-644 in more
~1.2V 350mV
complete interface specifications between transmitters
and receivers.
Figure 1. LVDS Output Levels
IS T
Q1 Q2 IS B
A– A+
ANSI/TIA/EIA-644 AD9430-170
Specification Min Max Typ
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AN-586
Output Current LVDS PCB DESIGN CONSIDERATIONS
Unlike CMOS, which is typically a voltage output, LVDS is a LVDS outputs for high-performance ADCs should be treated
current output technology. The AD9430 output current is differently than standard LVDS outputs used in digital
set by a resistor with a typical value of 3.7 kW. This 3.7 kW logic. While standard LVDS can drive 1 to 10 meters in
resistor sets the output current to 3.5 mA. Note that the high-speed digital applications (dependent on data rate),
nominal output current (IS) of 3.5 mA can be varied in the it is not recommended to let a high-performance ADC
AD9430, allowing some system design flexibility. See drive that distance. It is recommended to keep the output
the AD9430 data sheet for more information. trace lengths short (< 2 in.), minimizing the opportunity
for any noise coupling onto the outputs from the adja-
Differential Output Voltage and Offset Voltage
cent circuitry, which may get back to the analog inputs.
The ANSI specification defines the differential output
voltage swing to be between 247 mV and 454 mV. The differential output traces should be routed close
Assuming that the ADC outputs are set for a 3.5 mA together, maximizing common-mode rejection with the
output current and the receiver input impedance is 100 W termination resistor close to the receiver. Users
100 W, the nominal differential output voltage is 350 mV. should pay attention to PCB trace lengths to minimize
any delay skew.
The output drivers of the AD9430 were designed for a
nominal 1.2 V common mode, which is well within the A typical differential microstrip PCB trace cross section
ANSI specification. The common mode was specified in is shown in Figure 6.
the range 1.1 V to 1.375 V to account for ground shifts of
TW TS TW D TW TS TW
as much as ±1 V between the driver and receiver grounds.
For best performance, the ADC outputs should be located
very close to the receiver inputs on the same PCB, so DIFF PAIR 1 DIFF PAIR 2
Transition Time TG
REV. 0 –3–
AN-586
OTHER CONSIDERATIONS SUMMARY
LVDS also offers some benefit in reduced EMI. The EMI The advantages LVDS offers in high-speed signaling
fields generated by the opposing currents will tend to can provide performance and system benefits in
cancel each other (for matched edge rates). Trace converter applications. ADI’s portfolio of this
length, skew, and discontinuities will reduce this benefit technology within the ADC and TxDAC® products is in
and should be avoided. response to the ever increasing high-speed converter
E02796–0–5/02(0)
performance requirements.
LVDS also offers simpler timing constraints compared
to a demuxed CMOS solution at similar data rates. A
REFERENCES
demuxed databus requires a synchronization signal that
1. ANSI/TIA/EIA-644, Electrical Characteristics of Low
is not required in LVDS. In demuxed CMOS buses, a
Voltage Differential Signaling (LVDS) Interface Circuits,
clock equal to one-half the ADC sample rate is needed,
March 1996.
adding cost and complexity, that is not required in
LVDS. In general, the LVDS is more forgiving and can 2. IEEE Std 1596.3-1996, IEEE Standard for Low-Voltage
lead to a simpler, cleaner design by the customer. Differential Signals (LVDS) for Scalable Coherent
Interface (SCI), March 1996.
PRINTED IN U.S.A.
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