Assignment I

Problem Bank 01
Assignment Description:
The assignment aims to provide deeper understanding of cache by analysing it’s
behaviour using cache implementation of CPU- OS Simulator. The assignment has three
parts.
 Part I deals with Cache Memory Management with Direct Mapping
 Part II deals with Cache Memory Management with Associative Mapping
 Part III deals with Cache Memory Management with Set Associative Mapping

 Submission: You will have to submit this documentation file and the name of the file
should be GROUP-NUMBER.pdf.For Example, if your group number is 1, then the file name
should be GROUP-1.pdf.

Submit the assignment by 5thDecember 2021, through canvas only. File submitted by any
means outside CANVAS will not be accepted and marked.

Caution!!!

Assignments are designed for individual groups which may look similar and you may not
notice minor changes in the assignments. Hence, refrain from copying or sharing documents
with others. Any evidence of such practice will attract severe penalty.
Evaluation:

 The assignment carries 10 marks

 Grading will depend on
o Contribution of each student in the implementation of the assignment
o Plagiarism or copying will result in -10 marks
************************FILL IN THE DETAILS GIVEN BELOW**************
Assignment Set Number: 01
Group Name: Group 01
Contribution Table:
Contribution (This table should contain the list of all the students in the group. Clearly
mention each student’s contribution towards the assignment. Mention “No Contribution” in
cases applicable.)

Sl. Name (as appears in Canvas) ID NO Contribution

No.

1 DUGGISETTY GREESHMA 2021C104017 100%

Recorded
observations for
all test cases,
verified other
member’s values,
graph generation,
made inferences
for all the graphs.

2 AMBATI UDAYCHANDER 2021C104033 100%

Recorded
observations for
all test cases,
verified other
member’s values,
graph generation,
made inferences
for all the graphs.

3 CHAMARTHI SREEKARI 2021C104051 NIL

Resource for Part I, II and III:

 Use following link to login to “eLearn” portal.
o https://elearn.bits-pilani.ac.in
 Click on “My Virtual Lab – CSIS”
 Using your canvas credentials login in to Virtual lab
 In “BITS Pilani” Virtual lab click on “Resources”. Click on “Computer Organization
and software systems” course.
o Use resources within “LabCapsule3: Cache Memory”
Code to be used:
The following code written in STL Language, implements searching of an element
(key) in an array using linear search technique.
program LinearSearch 
   var a array(50) byte 

writeln("Array Elements: ")

  num = 10
for n = 0 to num 
     a(n) = n 
writeln(a(n))
next

key = 10
writeln("Key to be searched: ",key)

found = 0

for n = 0 to num
temp = a(n)
if temp = key then
found = 1
writeln("Key Found",temp)
break
end if
next
if found <> 1 then
writeln("Key Not Found")
end if
end
General procedure to convert the given STL program in to ALP:
 Open CPU OS Simulator. Go to advanced tab and press compiler button
 Copy the above program in Program Source window
 Open Compile tab and press compile button
 In Assembly Code, enter start addressand press Load in Memory button
 Now the assembly language program is available in CPU simulator.
 Set speed of execution to FAST.
 Open I/O console
 To run the program press RUNbutton.
General Procedure to use Cache set up in CPU-OS simulator
 After compiling and loading the assembly language code in CPU simulator, press
“Cache-Pipeline” tab and select cache type as “data cache”. Press “SHOW CACHE..”
button.
  In the newly opened cache window, choose appropriate cache Type, cache size, set
blocks, replacement algorithm and write back policy.
Part I: Direct Mapped Cache
a) Execute the above program by setting block size = 4 and cache size = 8, 16 and 32.
Record the observation in the following table for various values of “num” in the
program.

num Block Size Cache size # Hits # Misses %Hit Ratio

10 4 8 114 72 61.29%

4 16 148 38 79.56%

4 32 160 26 86.02%

15 4 8 139 87 61.50%

4 16 173 53 76.54%

4 32 198 28 87.61%

20 4 8 164 102 61.65%

4 16 208 58 78.19%

4 32 234 32 87.96%

25 4 8 189 117 61.76%

4 16 243 63 79.41%

4 32 269 37 87.90%

b) Comment on the result obtained in the above table by keeping in mind the locality of
reference.

Direct mapping maps each block of memory into only one possible cache line.
For constant Block size, as cache size increases, the number of lines increases.
As number of lines increases, there will be less chance in miss.
Hence Hit ratio increases.

From the code,

Access array elements a[n] – Spatial Locality

n, temp, key – Temporal Locality (repeatedly reference the same variables enjoy good
temporal locality)

Stride 1 reference – so good spatial locality

Here, block of executable code (i.e., Access array elements a[n] and search the element) uses
spatial locality.
In Spatial locality, if any miss occurs, the number is fetched into cache and adjacent numbers
are also fetched.
Therefore, subsequent accesses are more likely to hit because of spatial locality.
If the adjacent words in the block are not accessed later, the effort of fetching them is wasted.
However, most real programs benefit from larger block sizes.

Part II: Associative Mapped Cache

a) Execute the above program by setting block size = 4 and cache size = 8, 16 and 32.
Record the observation in the following table for various values of “num” in the
program.

LRU Replacement Algorithm

num Block Size Cache size # Hits # Misses %Hit Ratio

10 4 8 94 92 50.53%

4 16 158 28 84.94%

4 32 158 28 84.94%

15 4 8 114 112 50.44%

4 16 196 30 86.72%

4 32 196 30 86.72%

20 4 8 134 132 50.37%

4 16 232 34 87.21%

4 32 232 34 87.21%

25 4 8 154 152 50.32%

4 16 270 36 88.23%

4 32 270 36 88.23%
 b) Comment on the result obtained in the above table by keeping in mind the locality of
reference.

Associative mapped cache is used to store content and addresses of memory word. Any block
can go into any lines of the cache. This means that word id bits are used to identify which
word in the block is needed, but tag becomes all of the remaining bits.

From the code,

Access array elements a[n] – Spatial Locality

n, temp, key – Temporal Locality (repeatedly reference the same variables enjoy good
temporal locality)

Stride 1 reference – so good spatial locality

Here, block of executable code (i.e., Access array elements a[n] and search the element) uses
spatial locality.
In Spatial locality, if any miss occurs, the number is fetched into cache and adjacent numbers
are also fetched.
Therefore, subsequent accesses are more likely to hit because of spatial locality.
If the adjacent words in the block are not accessed later, the effort of fetching them is wasted.
However, most real programs benefit from larger block sizes.

c) Compare the performance of Associative mapped cache and Direct Mapped Cache

100.00%
80.00%
Hit Ratio

60.00%
40.00% Direct Mapped
20.00% Associative Mapped
0.00%
8 16 32 8 16 32 8 16 32 8 16 32
Cache Size

For Direct mapped cache mapping, each block in main memory can only go into one
block in the cache.

In Associative mapped cache mapping, each block in main memory can be placed
anywhere in the cache.

Hence, in perform analysis between Direct mapped cache and Associative mapped
cache, we can say that Associative mapped cache is more efficient than Direct
mapped cache.
 d) Fill up the following table for three different replacement algorithms and state
which replacement algorithm is better and why ?

Replacement Algorithm : Random , num = 25

Block Size Cache size Miss Hit Hit ratio(%)
2 4 143 163 53.26 %
2 8 83 223 72.87 %
2 16 73 233 76.14 %
2 32 59 247 80.71 %
2 64 54 252 82.35 %
Replacement Algorithm : FIFO, num = 25
Block Size Cache size Miss Hit Hit ratio
2 4 146 160 52.28 %
2 8 72 234 76.47 %
2 16 64 242 79.08 %
2 32 62 244 79.73 %
2 64 54 252 82.35 %
Replacement Algorithm : LRU, num = 25
Block Size Cache size Miss Hit Hit ratio
2 4 163 143 46.73 %
2 8 62 244 79.73 %
2 16 62 244 79.73 %
2 32 60 246 80.39 %
2 64 54 252 82.35 %

LRU Algorithm is probably the most effective. It Replace that block in the set that has been
in the cache longest with no reference to it. Each line includes a USE bit. When a line is
referenced, its USE bit is set to 1 and the USE bit of the other line in that set is set to 0.
Because we are assuming that more recently used memory locations are more likely to be
referenced, LRU should give the best hit ratio. LRU is also relatively easy to implement for a
fully associative cache.
 Part III: Set Associative Mapped Cache
Execute the above program by setting the following Parameters:
 Number of sets (Set Blocks ) : 2 way
 Cache Type : Set Associative
 Replacement: LRU/FIFO/Random
 num = 25

a) Fill up the following table for three different replacement algorithms and state which
replacement algorithm is better and why ?
Replacement Algorithm : Random
Block Size Cache size Miss Hit Hit ratio
4 4 N/A N/A N/A
4 8 133 173 56.53%
4 16 51 255 83.33%
4 32 38 268 87.58%
4 64 37 269 87.90%
Replacement Algorithm : FIFO
Block Size Cache size Miss Hit Hit ratio
4 4 N/A N/A N/A
4 8 124 182 59.47%
4 16 40 266 86.92%
4 32 37 269 87.90%
4 64 32 274 89.54%
Replacement Algorithm : LRU
Block Size Cache size Miss Hit Hit ratio
4 4 N/A N/A N/A
4 8 152 154 50.32%
4 16 36 270 88.23%
4 32 36 270 88.23%
4 64 32 274 89.54%

LRU Algorithm is probably the most effective. It Replace that block in the set that has been
in the cache longest with no reference to it. For two-Way set associative, this is easily
implemented. Each line includes a USE bit. When a line is referenced, its USE bit is set to 1
and the USE bit of the other line in that set is set to 0. Because we are assuming that more
recently used memory locations are more likely to be referenced, LRU should give the best
hit ratio. LRU is also relatively easy to implement for a fully associative cache.

For Block size of 4 and cache size of 4 caches lines would be 1 which is against the two-way
associative mapping where it contains 2 lines per set.

Cache Lines=(Cache Size)/(Block Size)=4/4=1 Line

1 Line ≠ 2 Lines per set (as it is two-way set associative)

b) Plot the graph of Cache Hit Ratio Vs Cache size with respect to different replacement
algorithms. Comment on the graph that is obtained
100
90
80
70
60
Replacement Algorithm :
Hit Ratio

50 Random
40 Replacement Algorithm :
FIFO
30 Replacement Algorithm :
20 LRU

10
0
8 16 32 64
Cache Size (Bytes)

From above graph we can observe that LRU replacement algorithm work better for larger
cache size. For cache size of 8Kb FIFO Replacement algorithm works better.

c) Fill in the following table and analyse the behaviour of Set Associate Cache. Which one is
better and why?
Replacement Algorithm : LRU, num=20
Block Size, Set Blocks Miss Hit Hit ratio
Cache size
2, 64 2 – Way 50 216 81.20%
2, 64 4 – Way 50 216 81.20%
2, 64 8 – Way 51 215 80.82%

Above table shows the results of simulation study of set-associative cache performance. The
difference in performance between two-way and four way associative at 64kB is much less
and negligible in this case. The complexity of cache increases in proportion to the
associativity. In this case cache size with 64kB with two-way is suitable as there is no
significant change in performance when compared to four-way and eight-way.While the
benefit of going from one-way (direct mapped) to two-way set associativeis significant, the
benefits of further associativity are smaller (e.g., 1%–10% improvement going from two-way
to four-way versus 20%–30% improvement going from one-way to two-way). There is even
less improvement in going from four-way to eight-way set associative, which, in turn, comes
very close to the miss rates of a fully associative cache