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Sitronix ST7920
Chinese Fonts built in LCD controller/driver
Main Features
l Operation Voltage Range: l Low power consumption design
Ø 2.7V to 5.5V Ø Normal mode (450uA Typ VDD=5V)
l Support 8-bit, 4-bit and serial bus MPU interface Ø Standby mode (30uA Max VDD=5V)
l 64 x 16-bit display RAM (DDRAM) l VLCD (V0 to VSS): max 7V
Ø Supports 16 words x 4 lines (Max) l Graphic and character mixed display mode
Ø LCD display range 16 words x 2 lines l Multiple instructions:
l 64 x 256-bit Graphic Display RAM (GDRAM) Ø Display Clear
l 2M-bits Character Generation ROM (CGROM): Ø Return Home
Support 8192 Chinese words (16x16 dot matrix) Ø Display ON/OFF
l 16K-bit half-width Character Generation ROM Ø Cursor ON/OFF
(HCGROM): Ø Display Character Blink
Supports 126 characters (16x8 dot matrix) Ø Cursor Shift
l 32-common x 64-segment (2 lines of character) Ø Display Shift
LCD drivers Ø Vertical Line Scroll
l Automatic power on reset (POR) Ø Reverse Display (by line)
l External reset pin (XRESET) Ø Standby Mode
l With the extension segment drivers, the display l Built-in voltage booster (2 times)
area can up to 16x2 lines VOUT: max 7V
l Built-in RC oscillator: l 1/33 Duty (with ICON)
Frequency is adjusted by an external resistor
Function Description
ST7920 LCD controller/driver IC can display alphabets, numbers, Chinese fonts and self-defined characters. It
supports 3 kinds of bus interface, namely 8-bit, 4-bit and serial. All functions, including display RAM, Character
Generation ROM, LCD display drivers and control circuits are all in a one-chip solution. With a minimum system
configuration, a Chinese character display system can be easily achieved.
ST7920 includes character ROM with 8192 16x16 dots Chinese fonts and 126 16x8 dots half-width alphanumerical
fonts. Besides, it supports 64x256 dots graphic display area for graphic display (GDRAM). Mix-mode display with
both character and graphic data is possible. ST7920 has built-in CGRAM and provide 4 sets software programmable
16x16 fonts.
ST7920 has wide operating voltage range (2.7V to 5.5V). It also has low power consumption. So ST7920 is suitable
for battery-powered portable device.
ST7920 LCD driver consists of 32-common and 64-segment. Company with the extension segment driver (ST7921)
ST7920 can support up to 32-common x 256-segment display.
Instruction
Register (IR) COM1 to
RS
MPU Display 33/49-bit Common COM32
Interface Data RAM shift Signal
RW
(DDRAM) register Driver
E 64 x 16 bits
Instruction
Decoder
SEG1 to
SEG64
64-bit 64-bit Segment
shift latch Signal
Address register circuit Driver
Counter
DB4 to
DB7
Input/ Data
DB0 to Register LCD Drive
DB3 Output
(DR) Voltage
Buffer
Selector
Busy
Flag
Parallel/Serial converter
Vss and
Attribute Circuit
VDD
XOFF
XRESET
V0 V1 V2 V3 V4
Pad Diagram
30 1
31
ST7920
136
“ST7920
(0,0)
99
68
1
69 98
Pin Description
Name No. I/O Connects to Function
XRESET 11 I ― System reset input (low active).
Interface selection:
PSB 23 I ― 0: serial mode;
1: 8/4-bit parallel bus mode.
Parallel Mode: Register select.
0: Select instruction register (write)
or busy flag, address counter (read);
1: Select data register (write/read).
Serial mode: Chip select.
RS(CS*) 17 I MPU
1: chip enabled;
0: chip disabled.
When chip is disabled, SID and SCLK
should be set as “H” or “L”. Transcient
of SID and SCLK is not allowed.
Parallel Mode: Read/Write control.
0: Write;
RW(SID*) 18 I MPU
1: Read.
Serial Mode: Sserial data input.
Parallel Mode: 1: Enable trigger.
E(SCLK*) 19 I MPU
Serial Mode: Serial clock.
Higher nibble data bus of 8-bit interface
D4 to D7 28~31 I/O MPU
and data bus for 4-bit interface
D0 to D3 24~27 I/O MPU Lower nibble data bus of 8-bit interface.
Latch signal for extension segment
CL1 12 O Extension segment drv.
drivers.
Shift clock for extension segment
CL2 13 O Extension segment drv.
drivers.
AC signal for extension segment drivers
M 15 O Extension segment drv.
voltage inversion.
Data output for extension segment
DOUT 16 O Extension segment drv.
drivers.
COM1 to
40~71 O LCD Common signals.
COM32
SEG1 to
136~73 O LCD Segment signals.
SEG64
LCD bias voltage.
V0 to V4 1~3,7,8 ― ―
V0 ~ V4 ≦ 7V.
VDD 10,14 I Power VDD : 2.7V to 5.5V.
Vss 9,20 I Power VSS: 0V.
Using internal oscillator:
5.0V R=33K;
OSC1,
21,22 I, O Resistors 2.7V R=18K.
OSC2
Using external clock:
Use OSC1 as external clock input.
LCD voltage doubler output.
VOUT 33 O Resistors
VOUT ≦ 7V.
*Note: The OSC pin must have the shortest wiring pattern of all other pins. To prevent noise from other
signal lines, it should also be enclosed by the largest GND pattern. Poor anti-noise characteristics on the
OSC line will result in malfunction, or adversely affect the clock’s duty ratio.
Note:
1. 7V>=VOUT>=V0>=V1>=V2>=V3>=V4 must be maintained
2. Two clock options: As shown below.
R Clock input
R=33K (VDD=5.0V)
R=18K (VDD=2.7V)
700 800
700
600
600
Frequency(KHz)
500
Iss (uA)
500
400
400
300
300
200 200
100 100
0 0
5 15 25 40 60 80 100 5 15 25 40 60 80 100
Resistor(K) Resistor(K)
3. When using voltage doubler (VOUT), it is recommended that the sum of those divide resistors (R1~R5) should be larger than 20K Ohm.
So that the voltage doubler can provide sufficient power.
Voltage Doubler
Voltage Doubler
Reference Voltage
Vss VD2
CAP1M
CAP1P
CAP2M
CAP2P
CAP3M
VOUT VOUT
9
Do not operate in this area.
8
7
VOUT (V)
0
5 4.8 4.6 4.4 4.2 4 3.8 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2 1.8
VD2 (V)
Voltage Doubler mode: VD2 & Vout output characteristic
Notes:
l Total resistance of the Follower deviding resistors should larger than 20K Ohm.
l Booster Capacitor uses 4.7uF
l Panel size: 80mm x 28mm (check display)
Function Description
System interface
ST7920 supports 3 kinds of bus interface to communicate with MPU: 8-bit parallel, 4-bit parallel and clock
synchronized serial interface. Parallel interface is selected by PSB=”1” and serial interface is by PSB=”0”. 8-bit / 4-bit
interface is selected by function set instruction DL bit.
Two 8-bit registers (Data Register DR and Instruction Register IR) are used in ST7920 to access DRAM or Register.
Data Register (DR) can access DDRAM, CGRAM and GDRAM through the address pointer implemented by Address
Counter (AC). Instruction Register (IR) stores the instruction sent by MPU to ST7920.
4 kinds of parallel interface access mode can be selected through RS and RW:
RS RW Description
L L MPU write instruction to instruction register (IR)
L H MPU read busy flag (BF) and address counter (AC)
H L MPU write data to data register (DR)
H H MPU read data from data register (DR)
* The serial interface access modes do not have Read operation.
Character Generation ROM (CGROM) and Half-width Character Generation ROM (HCGROM)
ST7920 is built in a Character Generation ROM (CGROM) to provide 8192 16x16 character fonts and a Half-width
Character Generation ROM to provide 126 8x16 alphanumeric characters. It is easy to support multi-language
applications such as Chinese and English. Two consecutive bytes are used to specify one 16x16 character or two
8x16 half-width characters. Character codes are written into DDRAM and the corresponding fonts are mapped from
CGROM or HCGROM to the display drivers.
ST7920 can display half-width HCGROM fonts, user-defined CGRAM fonts and full 16x16 CGROM fonts. The
character codes in 0000H~0006H will use user-defined fonts in CGRAM. The character codes in 02H~7FH will use
half-width alpha numeric fonts. The character code larger than A1H will be treated as 16x16 fonts and will be
combined with the next byte automatically. The 16x16 BIG5 fonts are stored in A140H~D75FH while the 16x16 GB
fonts are stored in A1A0H~F7FFH. In short:
1. To display HCGROM fonts:
Write 2 bytes of data into DDRAM to display two 8x16 fonts. Each byte represents 1 character.
The data is among 02H~7FH.
2. To display CGRAM fonts:
Write 2 bytes of data into DDRAM to display one 16x16 font.
Only 0000H, 0002H, 0004H and 0006H are acceptable.
3. To display CGROM fonts:
Write 2 bytes of data into DDRAM to display one 16x16 font.
A140H~D75FH are BIG5 code, A1A0H~F7FFH are GB code.
The higher byte (D15~D8) is written first and the lower byte (D7~D0) is the next.
Please refer to Table 5 for the relationship between DDRAM and the address/data of CGRAM.
CGRAM fonts and CGROM fonts can only be displayed in the start position of each address. (Refer toTable 4)
80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F
H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L H L
S i t r o n i x S T 7 9 2 0
矽 創 電 子 . . 中 文 編 碼 ( 正 確 )
矽 創 電 子 . . . 中 文 編 碼
Table 4
LCD driver
ST7920 embedded LCD driver has 33 commons and 64 segments to drive the LCD panel. Segment data from
CGRAM, CGROM and HCGROM are shifted into the 64 bits segment latche to display. Extended segment driver
(ST7921) can be used to extend the segment outputs upto 256 segments.
Note:
1. DDRAM data (character code) bit1 and bit2 are identical with CGRAM address bit4 and bit5.
2. CGRAM address bit0 to bit3 specify total 16 rows. Row-16 is for cursor display. The data in Row-16 will be logically OR to the cursor.
3. CGRAM data for each address is 16 bits.
4. To select the CGRAM font, the bit4 through bit15 of DDRAM data must be “0” while bit0 and bit3 are “don’t care”.
12
13
14
15
16
17
18
19
20
21
22
23
...........
24
25
26
27
28
29
30
31
32
33
︵ 34
35
Y
36
︶ 37
38
39
40
41
42
43
44
45
...........
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Instructions
ST7920 offers basic instruction set and extended instruction set:
Display Fill DDRAM with "20H" and set DDRAM address counter (AC)
0 0 0 0 0 0 0 0 0 1 1.6 ms
Clear to "00H".
Return Set DDRAM address counter (AC) to "00H", and put cursor
0 0 0 0 0 0 0 0 1 X 72 us
Home to origin ;the content of DDRAM are not changed
Entry Mode Set cursor position and display shift when doing write or read
0 0 0 0 0 0 0 1 I/D S 72 us
Set operation
D=1: Display ON
Display
0 0 0 0 0 0 1 D C B C=1: Cursor ON 72 us
Control
B=1: Character Blink ON
Cursor
Cursor position and display shift control; the content of
Display 0 0 0 0 0 1 S/C R/L X X 72 us
DDRAM are not changed
Control
DL=1 8-bit interface
Function 0 DL=0 4-bit interface
0 0 0 0 1 DL X X X 72 us
Set RE RE=1: extended instruction
RE=0: basic instruction
Set Set CGRAM address to address counter (AC)
CGRAM 0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 Make sure that in extended instruction SR=0 (scroll or 72 us
Address. RAM address select)
Set
0 Set DDRAM address to address counter (AC)
DDRAM 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0 72 us
AC6 AC6 is fixed to 0
Address.
Read
Read busy flag (BF) for completion of internal operation, also
Busy Flag 0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0 0 us
Read out the value of address counter (AC)
(BF) & AC.
Write data to internal RAM
Write RAM 1 0 D7 D6 D5 D4 D3 D2 D1 D0 72 us
(DDRAM/CGRAM/GDRAM)
Read data from internal RAM
Read RAM 1 1 D7 D6 D5 D4 D3 D2 D1 D0 72 us
(DDRAM/CGRAM/GDRAM)
Note:
1. Make sure that ST7920 is not in busy state by reading the busy flag before sending instruction or data. If using delay loop instead, please
make sure the delay time is enough. Please refer to the instruction execution time.
2. “RE” is the selection bit of basic and extended instruction set. After setting the RE bit, the value will be kept. So that the software doesn’t
have to set RE every time when using the same instruction set.
0 0 0 0 0 0 1 D C B
Display
Display, cursor and blink are ALL OFF
Control
0 0 0
0
0 0 0 0 1 DL X X X
FUNCTION RE
8-bit MPU interface , basic instruction set
SET
1 0
0 0 0 0 0 0 0 1 R1 R0
REVERSE Begin with normal and toggle to reverse
0 0
1
EXTENDED 0 0 0 0 1 DL X G 0
RE
FUNCTION Graphic display OFF
SET 0
Code 0 0 0 0 0 0 0 0 0 1
Code 0 0 0 0 0 0 0 0 1 X
Set address counter (AC) to "00H". Cursor moves to origin. Then content of DDRAM is not changed.
l Enry Mode Set
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code 0 0 0 0 0 0 0 1 I/D S
Set the cursor movement and display shift direction when doing write or read operation.
I/D: Address Counter Control: (Increase/Decrease)
When I/D = "1", cursor moves right, address counter (AC) is increased by 1.
When I/D = "0", cursor moves left, address counter (AC) is decreased by 1.
S: Display Shift Control: (Shift Left/Right)
S I/D DESCRIPTION
H H Entire display shift left by 1
H L Entire display shift right by 1
l Display Control
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code 0 0 0 0 0 0 1 D C B
This instruction configures the cursor moving direction or the display shifting direction. The content of DDRAM is
not changed.
S/C R/L Description AC Value
L L Cursor moves left by 1 position AC=AC-1
L H Cursor moves right by 1 position AC=AC+1
H L Display shift left by 1, cursor also follows to shift. AC=AC
H H Display shift right by 1, cursor also follows to shift. AC=AC
l Function Set
Code 0 0 0 0 1 DL X RE X X
In same instruction cannot alter DL and RE at once. Make sure that change DL first then RE.
Read busy flag (BF) can check whether the internal operation is finished or not. At the same time, the value of
address counter (AC) is also read. When BF = “1”, further instruction(s) will not be accepted until BF = “0”.
Code 1 0 D7 D6 D5 D4 D3 D2 D1 D0
Code 1 1 D7 D6 D5 D4 D3 D2 D1 D0
Read data from the internal RAM and increase/decrease the (AC) by 1
After the operation mode changed to Read (CGRAM, DDRAM and GDRAM…), a “Dummy Read” is required.
There is no need to add a “Dummy Read” for the following bytes unless a new address set instruction is issued.
Code 0 0 0 0 0 0 0 0 0 1
This Instruction will set ST7920 entering the standby mode. Any other instruction follows this instruction will
terminate the standby mode.
The content of DDRAM remains the same.
Code 0 0 0 0 0 0 0 0 1 SR
l Reverse
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Code 0 0 0 0 0 0 0 1 R1 R0
Select 1 out of 4 lines to reverse the display and to toggle the reverse condition by repeating this instruction.
R1, R0 initial vale is 00. The first time issuing this instruction, the display will be reversed while the second time
will return the display become normal.
R1 R0 Description
L L First line normal or reverse
L H Second line normal or reverse
H L Third line normal or reverse
H H Fourth line normal or reverse
Please note that only 2 lines out of 4 lines of display data can be displayed with one ST7920.
Code 0 0 0 0 1 DL X RE G X
In same instruction cannot alter DL, RE and G at once. Make sure that change DL or G first and then RE.
Set GDRAM address into address counter (AC). This is a 2-byte instruction.
The first instruction sets the vertical address while the second one sets the horizontal address (write 2
consecutive bytes to complete the vertical and horizontal address setting).
Vertical address range is AC5...AC0
Horizontal address range is AC3…AC0
The address counter (AC) of graphic RAM (GRAM) will be increased automatically after the vertical and
horizontal addresses are set. After horizontal address is increased upto 0FH, it will automatically return to 00H.
However, the vertical address will not increase as the result of the same action.
Parallel interface:
ST7920 is in parallel mode by pulling up PSB pin. ST7920 can select 8-bit or 4-bit bus interface by setting the DL
control bit in “Function Set” instruction. MPU can control RS, RW, E and DB0…DB7 pins to complete the data
transmission.
In 4-bit transfer mode, every 8-bit data or instruction is separated into 2 parts. The higher 4 bits (bit-7~bit-4) data will
be transfered first through data pins (DB7~DB4). The lower 4 bits (bit-3~bit-0) data will be transfered second through
data pins (DB7~DB4). The (DB3~DB0) data pins are not used during 4-bit transfer mode.
RS
RW
DB0-DB7
Instruction write Dummy read RAM read
RS
RW
E
Upper Lower Upper Lower Upper Lower
Serial interface:
ST7920 is in serial interface mode when pulling down PSB pin. Two pins (SCLK and SID) are used to complete the
data transfer. Only write data is available in the serial interface mode.
When chip select (CS) is low, ST7920 serial clock counter and serial data will be reset. Serial transfer counter is set
to the first bit and data register is cleared. After CS is “L”, any further change on SID or SCLK is not allowed. It is
recommended to keep SCLK at “L” and SID at the last status before set CS to “L”. For a minimal system with only
one ST7920 and one MPU, only SCLK and SID pins are necessary. CS pin should pull to high.
ST7920’s serial clock (SCLK) is asynchronous to the internal clock and is generated by MPU. When multiple
instruction/data is transferred, the instruction execution time must be considered. MPU must wait till the previous
instruction is finished and then send the next instruction. ST7920 has no internal instruction buffer area.
When starting a transmission, a start byte is required. It consists of 5 consecutive “1” (sync character). Serial transfer
counter will be reset and synchronized. Followed by 2-bit flag that indicates: read/write (RW) and register/data
selected (RS) operation. Last 4 bits are filled by “0”.
After receiving the sync character, RW and RS bits, every 8 bits instruction/data will be separated into 2 groups.
Higher 4 bits (DB7~DB4) will be placed in the first section followed by 4 “0”s. And lower 4 bits (DB3~DB0) will be
placed in the second section followed by 4 “0”s.
CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK
SID 1 1 1 1 1 RW RS 0 D7 D6 D5 D4 0 0 0 0 D3 D2 D1 D0 0 0 0 0
;-------------------------------------------------------------- ;-------------------------------------------------
; Write data from A into INSTRUCTION Register ; Write data from A into DATA Register
;-------------------------------------------------------------- ;-------------------------------------------------
WRINS: WRDATA:
SETB CS SETB CS
SETB SID ; SID = 1 SETB SID ; SID = 1
CLR SCLK CLR SCLK
SETB SCLK ; READ DATA FROM SID SETB SCLK ; READ DATA FROM SID
CLR SCLK CLR SCLK
SETB SCLK ; READ DATA FROM SID SETB SCLK ; READ DATA FROM SID
CLR SCLK CLR SCLK
SETB SCLK ; READ DATA FROM SID SETB SCLK ; READ DATA FROM SID
CLR SCLK CLR SCLK
SETB SCLK ; READ DATA FROM SID SETB SCLK ; READ DATA FROM SID
CLR SCLK CLR SCLK
SETB SCLK ; READ DATA FROM SID SETB SCLK ; READ DATA FROM SID
CLR SCLK CLR SCLK
CLR SID ; SID = 0 CLR SID ; SID = 0
SETB SCLK ; READ DATA FROM SID SETB SCLK ; READ DATA FROM SID
CLR SCLK CLR SCLK
SETB SCLK ; READ DATA FROM SID SETB SID ; SID = 1
CLR SCLK SETB SCLK ; READ DATA FROM SID
SETB SCLK ; READ DATA FROM SID CLR SCLK
CLR SCLK CLR SID ; SID = 0
MOVBIT SID, A.7 ; SID = A.7 SETB SCLK ; READ DATA FROM SID
SETB SCLK ; READ DATA FROM SID CLR SCLK
CLR SCLK MOVBIT SID, A.7 ; SID = A.7
MOVBIT SID, A.6 ; SID = A.6 SETB SCLK ; READ DATA FROM SID
SETB SCLK ; READ DATA FROM SID CLR SCLK
CLR SCLK MOVBIT SID, A.6 ; SID = A.6
MOVBIT SID, A.5 ; SID = A.5 SETB SCLK ; READ DATA FROM SID
SETB SCLK ; READ DATA FROM SID CLR SCLK
CLR SCLK MOVBIT SID, A.5 ; SID = A.5
MOVBIT SID, A.4 ; SID = A.4 SETB SCLK ; READ DATA FROM SID
SETB SCLK ; READ DATA FROM SID CLR SCLK
CLR SCLK MOVBIT SID, A.4 ; SID = A.4
CLR SID ; SID = 0 SETB SCLK ; READ DATA FROM SID
SETB SCLK ; READ DATA FROM SID CLR SCLK
CLR SCLK CLR SID ; SID = 0
SETB SCLK ; READ DATA FROM SID SETB SCLK ; READ DATA FROM SID
CLR SCLK CLR SCLK
SETB SCLK ; READ DATA FROM SID SETB SCLK ; READ DATA FROM SID
CLR SCLK CLR SCLK
SETB SCLK ; READ DATA FROM SID SETB SCLK ; READ DATA FROM SID
CLR SCLK CLR SCLK
MOVBIT SID, A.3 ; SID = A.3 SETB SCLK ; READ DATA FROM SID
SETB SCLK ; READ DATA FROM SID CLR SCLK
CLR SCLK MOVBIT SID, A.3 ; SID = A.3
MOVBIT SID, A.2 ; SID = A.2 SETB SCLK ; READ DATA FROM SID
SETB SCLK ; READ DATA FROM SID CLR SCLK
CLR SCLK MOVBIT SID, A.2 ; SID = A.2
MOVBIT SID, A.1 ; SID = A.1 SETB SCLK ; READ DATA FROM SID
SETB SCLK ; READ DATA FROM SID CLR SCLK
CLR SCLK MOVBIT SID, A.1 ; SID = A.1
MOVBIT SID, A.0 ; SID = A.0 SETB SCLK ; READ DATA FROM SID
SETB SCLK ; READ DATA FROM SID CLR SCLK
CLR SCLK MOVBIT SID, A.0 ; SID = A.0
CLR SID ; SID = 0 SETB SCLK ; READ DATA FROM SID
SETB SCLK ; READ DATA FROM SID CLR SCLK
CLR SCLK CLR SID ; SID = 0
SETB SCLK ; READ DATA FROM SID SETB SCLK ; READ DATA FROM SID
CLR SCLK CLR SCLK
SETB SCLK ; READ DATA FROM SID SETB SCLK ; READ DATA FROM SID
CLR SCLK CLR SCLK
SETB SCLK ; READ DATA FROM SID SETB SCLK ; READ DATA FROM SID
CLR SCLK CLR SCLK
CLR CS SETB SCLK ; READ DATA FROM SID
CALL DLY8 CLR SCLK
RET CLR CS
CALL DLY8
RET
1 Big5 (0A) 38 88 CC F1
2 GB (0B) 9D 81 79 29
3 0C FD 6F B5 85
ST7920 check sum circuit: Data is available when CLK is height; if CLK is low then the data is always FFH. The last
four bytes are Y0, Y1, Y2, and Y3.
1 Big5 (0A) B5 11 B5 11
2 GB (0B) B5 11 B5 11
3 0C B5 11 B5 11
1 1 -- RESET
0 1 655362 CGROM
1 0 10242 HGROM
;*******************************;
;* CHECK_ROM *;
;*******************************;
;*******************************;
;* Definition of outside Pin *;
;*******************************;
CLK REG P3.5 ;
TT1 REG P3.0 ;
TT2 REG P3.1 ;
TT3 REG P3.2 ;CHECK CGROM FLAG
TT4 REG P3.3 ;CHECK HCGROM FLAG
TT5 REG P3.4 ;ERROR FLAG
;*******************************;
;* Definition of internal RAM *;
;*******************************;
STACK EQU 6FH ;
FUNC EQU 20H ;
;*******************************;
; Interrupt set *;
;*******************************;
ORG 00H ;
AJMP RESET ;
;*******************************;
;* PROGRAM START *;
;*******************************;
RESET: MOV SP,#STACK ;
MOV P1,#FFH ;
MOV P3,#FFH ;
;*******************************;
;* CHECK_CGROM *;
;*******************************;
;*******************************;
;* Initial DDRAM *;
;*******************************;
CALL WR0x00 ;Write 0x00 to whole DDRAM
;*******************************;
;* Initial setting *;
;*******************************;
CGROM: SETB TT1 ;
SETB TT2 ;TT1,TT2 SET HIGH (RESET)
CALL DELAY_100US ;Wait Reset 100us
CLR TT1 ;TT1=LOW TT2=HIGH ( CHECK CGROM)
SETB CLK ;
CALL DELAY_100US ;
;*******************************;
;* start counter *;
;*******************************;
MOV R3,#9 ;
CN4: MOV R2,#0 ;<----
CN3: MOV R1,#0 ; |
CN2: CLR CLK ; |
SETB CLK ; |
DJNZ R1,CN2 ; |
DJNZ R2,CN3 ; |
DJNZ R3,CN4 ; |
; |
MOV R3,#0 ; |
CN5: MOV R2,#255 ; |
CN6: CLR CLK ; |
SETB CLK ; |
DJNZ R2,CN6 ; |
DJNZ R3,CN5 ; |
; |
8-bit interface:
POWER ON
Function set
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 1 1 X 0 X X
Function set
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 1 1 X 0 X X
Display clear
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 1
Initialization end
4-bit interface:
POWER ON
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 1 0 X X X X
0 0 X 0 X X X X X X
Function set
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 1 0 X X X X
0 0 X 0 X X X X X X
Display Clear
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 X X X X
0 0 0 0 0 1 X X X X
INITIALIZATION END
Vss VD2
CAP1M
Voltage Doubler
Reference Voltage
CAP1P
VD2
CAP2M
CAP2P
CAP3M
VDD
Tres
XRESET
Trw
V0
V1
V2
COM1 V3
V4
VSS
V0
V1
V2
COM2 V3
V4
VSS
V0
V1
V2
COM33 V3
V4
VSS
V0
V1
SEGx V2
off V3
V4
VSS
V0
V1
SEGx V2
on
V3
V4
VSS 1 frame
VIH1
RS VIL1
TAS TAH
R/W
TPW TAH
E
TDSW TH
TR
VIH1
RS VIL1
TAS TAH
R/W
TPW TAH
TR
E
TDDR TH
TCSS TCSH
CS
TSCYC
SCLK TSLW
TSHW
Tf
Tr
TSDS TSDH
Enable
DATA
A
D
V4.0
VCC
JP1
R5
R4
R3
R2
R1
1
LCD
4.7K
4.7K
2.2K
4.7K
4.7K
2
R10
10K
VCC
3
4
HEADER 16
5
6
J1
3
2
1
7
R6
CON3
8
33K
1
1
9
VCC
10
R7
2K
11
ST7920
12
13
14
C1
104
15
16
JK
2
CON2
1
VCC
LCD Voltage : VCC
JP2
2
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
10
9
8
7
6
5
4
3
2
1
15
14
13
12
11
HEADER 2
R8
R9
E
M
D6
D5
D4
D3
D2
D1
D0
V4
V3
V2
V1
V0
RS
TT2
TT1
CLK
RW
CL2
CL1
PSB
VSS
VSS
VXC
VXB
VDD
VDD
VXA
Application circuit 1:
OSC2
OSC1
33
33
31
DOUT
136 S1
D7 S1
XRESET
32 135 S2 C25 192 96 C24
XOFF S2 C25 C24
33 134 S3 C26 191 95 C23
VOUT S3 C26 C23
2
2
34 133 S4 C27 190 94 C22
JA
2 CAP3M S4 C27 C22
35 132 S5 C28 189 93 C21
CON2
1 CAP1P S5 C28 C21
VCC
36 131 S6 C29 188 92 C20
CAP1M S6 C29 C20
37 130 S7 C30 187 91 C19
CAP2P S7 C30 C19
38 129 S8 C31 186 90 C18
CAP2M S8 C31 C18
39 128 S9 C32 185 89 C17
VD2 S9 C32 C17
C1 40 127 S10
C1 S10
C2 41 126 S11 S160 184 88 S140
C2 S11 S160 S140
C3 42 125 S12 S159 183 87 S139
C3 S12 S159 S139
C4 43 124 S13 S158 182 86 S138
C4 S13 S158 S138
: 32-COM x 160-SEG
3
3
C30
C31
C32
C33
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S112 S92
S111 155 59 S91
S111 S91
U1 S110 154 58 S90
S110 S90
S109 153 57 S89
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
S109 S89
ST7920
46/49
S108 152 56 S88
S108 S88
S107 151 55 S87
S107 S87
S106 150 54 S86
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
C30
C31
C32
S106 S86
S105 149 53 S85
S105 S85
S104 148 52 S84
S104 S84
S103 147 51 S83
S103 S83
S102 146 50 S82
S102 S82
S101 145 49 S81
S101 S81
S80 144 48 S60
S80 S60
4
4
S74 S54
S113 S73 137 41 S53
S73 S53
S72 136 40 S52
110 S72 S52
109
108
107
106
103
102
100
99
98
97
96
95
105
104
101
S69 S49
S1
V3
V2
V0
S49
DL1
DL2
VSS
DR1
DR2
S68 S48
VDD
SHL2
SHL1
5
5
B
Size
S129 16 79 S81 S33 117 21 S13
File:
Title
Date:
S65 S17 S33 S13
S130 17 78 S82 S32 116 20 S12
S66 S18 S32 S12
S131 18 77 S83 S31 115 19 S11
S67 S19 S31 S11
S132 19 76 S84 S30 114 18 S10
S68 S20 S30 S10
S133 20 75 S85 S29 113 17 S9
S69 S21 S29 S9
S134 21 74 S86 S28 112 16 S8
S70 S22 S28 S8
S135 22 73 S87 S27 111 15 S7
Number
S71 S23 S27 S7
S136 23 72 S88 S26 110 14 S6
1-Mar-2001
S72 S24 S26 S6
S137 24 71 S89 S25 109 13 S5
S73 S25 S25 S5
S138 25 70 S90 S24 108 12 S4
S74 S26 S24 S4
S139 26 69 S91 S23 107 11 S3
S75 S27 S23 S3
S140 27 68 S92 S22 106 10 S2
S76 S28 S22 S2
S141 28 67 S93 S21 105 9 S1
D:\Buffer-2\7920V1.DDB
S77 S29 S21 S1
S142 29 66 S94
S78 S30
S143 30 65 S95 C16 104 8 C1
S79 S31 C16 C1
S144 31 64 S96 C15 103 7 C2
S80 S32 C15 C2
S145 32 63 S97 C14 102 6 C3
Sitronix
S81 S33 C14 C3
S146 33 62 S98 C13 101 5 C4
S82 S34 C13 C4
S147 34 61 S99 C12 100 4 C5
S83 S35 C12 C5
S148 35 60 S100 C11 99 3 C6
S84 S36 C11 C6
S149 36 59 S101 C10 98 2 C7
S85 S37 C10 C7
ST7920 LCM
S150 37 58 S102 C9 97 1 C8
S86 S38 C9 C8
S151 38 57 S103
6 S87 S39
6
Sheet 1 of 1
S88
S89
S90
S91
S92
S93
S94
S95
S96
S48
S47
S46
S45
S44
S43
S42
S41
S40
L1
U2
Revision
ST7921
WDG1603P
1.2
S152
S153
S154
S155
S156
S157
S158
S159
S160
S112
S111
S110
S109
S108
S107
S106
S105
S104
2008/08/18
B
C
A
D
C
A
D
V4.0
JP1
R5
R4
R3
R2
R1
1
LCD
4.7K
4.7K
2.2K
4.7K
4.7K
2
R10
10K
VCC
3
4
HEADER 16
5
6
J1
3
2
1
7
R6
CON3
8
33K
1
1
9
VCC
10
R7
2K
11
ST7920
12
13
14
C1
104
15
16
JK
2
CON2
1
VCC
JP2
2
1
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
10
9
8
7
6
5
4
3
2
1
15
14
13
12
11
HEADER 2
R8
R9
E
M
D6
D5
D4
D3
D2
D1
D0
V4
V3
V2
V1
V0
RS
TT2
TT1
CLK
RW
CL2
CL1
PSB
VSS
VSS
VXC
VXB
VDD
VDD
VXA
Application circuit 2:
OSC2
OSC1
33
33
31
DOUT
136 S1
D7 S1
XRESET
32 135 S2 C25 192 96 C24
XOFF S2 C25 C24
33 134 S3 C26 191 95 C23
VOUT S3 C26 C23
2
2
34 133 S4 C27 190 94 C22
JA
2 CAP3M S4 C27 C22
35 132 S5 C28 189 93 C21
CON2
1 CAP1P S5 C28 C21
VCC
36 131 S6 C29 188 92 C20
CAP1M S6 C29 C20
37 130 S7 C30 187 91 C19
CAP2P S7 C30 C19
38 129 S8 C31 186 90 C18
CAP2M S8 C31 C18
39 128 S9 C32 185 89 C17
VD2 S9 C32 C17
C1 40 127 S10
+ C3
C1 S10
4.7u
C2 41 126 S11 S160 184 88 S140
C2 S11 S160 S140
C3 42 125 S12 S159 183 87 S139
C3 S12 S159 S139
C4 43 124 S13 S158 182 86 S138
C4 S13 S158 S138
: 32-COM x 160-SEG
C2
C5 44 123 S14 S157 181 85 S137
+
4.7u
C5 S14 S157 S137
C6 45 122 S15 S156 180 84 S136
C6 S15 S156 S136
C7 46 121 S16 S155 179 83 S135
C7 S16 S155 S135
C8 47 120 S17 S154 178 82 S134
C8 S17 S154 S134
C9 48 119 S18 S153 177 81 S133
C9 S18 S153 S133
C10 49 118 S19 S152 176 80 S132
C10 S19 S152 S132
C11 50 117 S20 S151 175 79 S131
C11 S20 S151 S131
C12 51 116 S21 S150 174 78 S130
C12 S21 S150 S130
C13 52 115 S22 S149 173 77 S129
C13 S22 S149 S129
C14 53 114 S23 S148 172 76 S128
C14 S23 S148 S128
C15 54 113 S24 S147 171 75 S127
C15 S24 S147 S127
C16 55 112 S25 S146 170 74 S126
C16 S25 S146 S126
C17 56 111 S26 S145 169 73 S125
C17 S26 S145 S125
C18 57 110 S27 S144 168 72 S124
C18 S27 S144 S124
C19 58 109 S28 S143 167 71 S123
C19 S28 S143 S123
3
3
C30
C31
C32
C33
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S112 S92
S111 155 59 S91
S111 S91
S110 154 58 S90
U1 S110 S90
S109 153 57 S89
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
S109 S89
ST7920
47/49
S108 152 56 S88
S108 S88
S107 151 55 S87
S107 S87
S106 150 54 S86
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
C30
C31
C32
S106 S86
S105 149 53 S85
S105 S85
S104 148 52 S84
S104 S84
S103 147 51 S83
S103 S83
S102 146 50 S82
S102 S82
S101 145 49 S81
S101 S81
S80 144 48 S60
S80 S60
4
4
S74 S54
S113 S73 137 41 S53
S73 S53
S72 136 40 S52
110 S72 S52
109
108
107
106
103
102
100
99
98
97
96
95
105
104
101
S69 S49
S1
V3
V2
V0
S49
DL1
DL2
VSS
DR1
DR2
S68 S48
VDD
SHL2
SHL1
5
5
B
Size
S129 16 79 S81 S33 117 21 S13
File:
Title
Date:
S65 S17 S33 S13
S130 17 78 S82 S32 116 20 S12
S66 S18 S32 S12
S131 18 77 S83 S31 115 19 S11
S67 S19 S31 S11
S132 19 76 S84 S30 114 18 S10
S68 S20 S30 S10
S133 20 75 S85 S29 113 17 S9
S69 S21 S29 S9
S134 21 74 S86 S28 112 16 S8
S70 S22 S28 S8
S135 22 73 S87 S27 111 15 S7
Number
S71 S23 S27 S7
S136 23 72 S88 S26 110 14 S6
S72 S24 S26 S6
17-Aug-2001
S137 24 71 S89 S25 109 13 S5
S73 S25 S25 S5
S138 25 70 S90 S24 108 12 S4
S74 S26 S24 S4
S139 26 69 S91 S23 107 11 S3
S75 S27 S23 S3
S140 27 68 S92 S22 106 10 S2
S76 S28 S22 S2
S141 28 67 S93 S21 105 9 S1
S77 S29 S21 S1
S142 29 66 S94
S78 S30
S143 30 65 S95 C16 104 8 C1
S79 S31 C16 C1
S144 31 64 S96 C15 103 7 C2
S80 S32 C15 C2
S145 32 63 S97 C14 102 6 C3
Sitronix
S81 S33 C14 C3
S146 33 62 S98 C13 101 5 C4
S82 S34 C13 C4
S147 34 61 S99 C12 100 4 C5
S83 S35 C12 C5
LCD Voltage : VCC x 2 (Voltage doubler is used). *VLCD (V0), VOUT and VCAP3M should not over 7V.
Sheet 1 of 1
ST7920 LCM (Booster)
S88
S89
S90
S91
S92
S93
S94
S95
S96
S48
S47
S46
S45
S44
S43
S42
S41
S40
L1
U2
Revision
ST7921
WDG1603P
1.4
S152
S153
S154
S155
S156
S157
S158
S159
S160
S112
S111
S110
S109
S108
S107
S106
S105
S104
2008/08/18
B
C
A
D
2008/08/18
Dot Matrix LCD Panel
Com 1-32 Seg 1-64 Seg 1-96 Seg 1-96
Dout DL1 DR2 DL1 DR2
VDD DL2 VDD DL2
DR1 DR1
SHL1 ST7921 CL1 SHL1 ST7921 CL1
SHL2 CL2 SHL2 CL2
VSS M VSS M
48/49
2Line 16Chinese Word (32-COM x 256-SEG)
V0 V0
V2 V3 V2 V3
ST7920 VDD
VSS
CL2
CL1
M
V0
V1
V2
V3
V4
Application circuit 3:
DB0-DB7
Vcc(+5V/+3V) VSS
VR Regsister Regsister Regsister Regsister Regsister
To MPU
Note:Regsister=2.2K~10K ohm
ST7920
VR=1K~30Kohm
:
LCD
V4.0
ST7920
R1
R2
R2
R2