IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

High Speed and Area Efficient Single Precision

Floating Point Arithmetic Unit
Sangeeta Palekar, Nitin Narkhede

Abstract— Many fields of science, engineering, finance, The control signal procreated from control unit will decide
mathematical optimization methods, Artificial Neural Networks, whether to adopt fixed point arithmetic unit or floating point
signal and image processing algorithms requires the operations arithmetic unit. In the proposed design the parallelism is
and manipulations of real numbers. Floating-point operations assimilated in multiplier to enhance the speed of operation and
are most extensively adopted approach for exploiting real achieve thorough speed requirement [1]. meticulousness of
numbers. The speed of Floating-point arithmetic unit is very fixed point implementation. So the high performance and area
crucial performance parameter which impinges the operation of economical floating point arithmetic unit is proposed which
the system. On that account a 32 bit floating point arithmetic unit will be used in 32 bit RISC processor for high speed
is designed for different applications which insists for eminent
application to impoverish the overhead of processor and
speed. The intent of this design is to reduce the area and
combinational path delay to enhance the speed of operation
accession of performance. The control signal procreated from
which is attained by parallelism in multiplier which is used for control unit will decide whether to adopt fixed point arithmetic
mantissa multiplication. For Floating-point multiplier Booth unit or floating point arithmetic unit. In the proposed design
recoded multiplier is used where the number of partial product the parallelism is assimilated in multiplier to enhance the
are reduced which in turns boost the speed of multiplication. The speed of operation and achieve thorough speed requirement
proposed module is implemented on Spartan 6 FPGA. [1].
Performance of the floating point arithmetic unit is compared The aggrandizement in the demand of floating point
with latest research papers regarding delay and it is ascertained arithmetic unit is predominantly due to three reasons: first is
that there is 59% of optimization in critical path delay of floating due to the effective range constraints and compatibility issues
point multiplier and 50 % of optimization of floating point adder. correlated with the various fixed-point delegation. Second
The result illustrates that proposed arithmetic unit has a great because of amelioration in VLSI technology it became
impact on convalescent the speed and area of the design. reasonable to devote hardware to the vocation of floating-
point computation. Third step was embodiment of floating
Keywords— Single precision, floating point arithmetic unit, point arithmetic unit in the extant processor on which fixed
high speed multiplier, radix4 booth multiplier, normalize and floating point reckoning can run concurrently [2]. The
floating point arithmetic unit inhere of fused floating point
adder/subtractor, multiplier.
I. INTRODUCTION
Memory Devices are getting economical and compact by II. FLOATING POINT REPRESENTATION
each passing day, but due to advancement in science and In 1985 a standard was refined by Institute of Electrical
technology the calculations and operations are insisting and Electronics Engineers named as IEEE 754 standard for
amassed memory. In computers numbers can be accumulated floating point numbers. Single precision floating point number
either in fixed point or floating point but depending upon abides of 32 bit and double precision point number abides of
application and performance required user adjudicate which 64 bit. The base for scaling is ordinarily binary (2), decimal
representation to be followed. Many fields of science, (10) or hexadecimal (16) [3].
engineering, finance, mathematical optimization methods,
Artificial Neural Networks, remote sensing, digital signal TABLE I: BIT RANGE
processing algorithms requires the operations and
manipulations of real numbers. Floating point representation Sign Exponent Emax Emin Mantissa Bias
has prevalent ascendancy over fixed point numbers, it Single 1
8 [30-23] +127 -126 23 [22-0] 127
endeavors extensive range of values; it can be used to Precision [31]
epitomize too minuscule number like mass of electron or too Double 1
11[62-52] +1023 -1022 52 [51-0] 1023
Precision [63]
exorbitant number like distance between earth and sun. To
implement the applications with high speed and performance,
it is elementary to design arithmetic and logical unit that can The single precision floating point number is symbolized as
manipulate floating point numbers with embracing the follows:
meticulousness of fixed point implementation. So the high
performance and area economical floating point arithmetic X = (-1) Xs ( Xm * 2Xe) (1)
unit is proposed which will be used in 32 bit RISC processor
for high speed application to impoverish the overhead of Xm: mantissa of X
processor and accession of performance.
Xs: sign bit of X
Xe: exponent of x
Sangeeta Palekar1, Department of Electronics, RCOEM, Nagpur, India
(sangeetapalekar2411@gmail.com)
Single precision floating point number includes sign of 1
bit, exponent of 8 bit and mantissa of 23 bit. Mantissa is
Dr. Nitin Narkhede, Department of Electronics, RCOEM, Nagpur, India hoarded with one hidden bit as 1.M. On the occasion sign bit
(narkheden@rknec.edu) having value zero indicates positive number, else negative.

978-1-5090-0774-5/16/$31.00 © 2016 IEEE

1950
 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

III. PROPOSED WORK

A. Floating point Arithmetic unit

The primitive obligation of any application is to have an
area efficient and high performance design. Hence a single
precision floating point arithmetic unit which encompasses
floating point adder/ subtractor, multiplier with high speed
performance and area efficient design is proposed [3].
B. Floating Point Adder/Subtractor
This block is used for addition in conjunction with Fig.3:Mantissa adder
subtraction which involves involves following steps [4]:
2. Normalize: The result of addition or subtraction may
X Y
fall outside of specified range or may be too small,
1 8 23 1 8 23
for such cases normalization is required to bring them
Sign Exponent Mantissa Sign Exponent Mantissa
in accepted range. It takes the result of step 2 sum as
8
an input, and then gives normalized sum. The
8 23 23 standard format to store mantissa is 1.M, so shifts the
Exponent Mantissa
1 8
Swap
sum to obtain one at the most significant bit. The
Subtractor
result also indicates for the cases like zero output or
Right Shift
denormalize. If the non-zero bits are discarded then
Sign Logic Mantissa add/sub
EOP
inexact flag is set.
Exponent Normalize

update
Rounder

1 8 23

Sign Exponent Mantissa

Fig.1: Floating Point Adder / Subtractor Fig.4: Normalizer

Where EOP: effective operation ADD/SUB 3. Rounding: Rounding is done on the basis of
following table [5]:
1. Align: Prior to addition it is mandatory that both the
operands should have same exponent. This module TABLE II: ROUNDING
does the same, it takes two operands a and b, split out Round mode Abbreviations Round to
the numbers into the bigger mantissa x and the 00 RN Nearest even
smaller mantissa y. The exponents of both the inputs 01 RZ Zero
are compared, and then the smaller exponent is 10 RP Positive infinity
11 RM Negative infinity
aligned to the larger exponent by incrementing the
exponent and shifting the binary point towards right.

Fig.5:Rounder
Fig.2: Aligner
4. Special: This module sets the flag whether the result
Mantissa addition/ subtraction: The output of aligner x is infinity, not a number or signaling not a number.
and y serves as input. The effective operation to be performed
is determined be exclusive OR of operation add/sub to be
perform (op), sign of a (Sa) and b (Sb). Choose Y for addition
and ~Y for subtraction. This module also produce presticky bit
which preserve trace of discarded bit and guard bit is the next
bit after limit of normalize mantissa which sometime will be
shifted into mantissa if MSB cancels while subtraction.

1951
 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

4. Multiply and Normalize: Multiply the mantissa of

multiplier and multiplicand, in the proposed design
the radix 4 booth recoded multiplier is used for
mantissa multiplication purpose. The mantissa is of
24 bit so the output of multiplication will result to 48
bit. Truncate the output so as to obtain the allowed
number of mantissa bit i.e. 24 bit.

5. Computation of exponent: Calculate the exponent of

result by adding the exponent of X and Y and
subtracting bias (12710) form it.
Re=Xe + Ye – bias
Fig.6: Special
6. Composition of result: Sign bit, exponent bits and
mantissa bits are combined to get the final result in
5. Final: This module gives the final mantissa Mz, binary format. Check the result for underflow and
exponent Ez and sign Sz, and with the help of flags overflow and generate exception or return error. If
determines all the applicable exceptions: overflow, the sum of exponent in step 5 exceeds 127 i.e the
underflow, invalid, and inexact. largest exponent value then it will results to overflow,
C. Floating point multiplier then the exponent is set to 128 and the mantissa is set
to zero resulting the result to be positive or negative
The floating point multiplication of input X and Y is infinity. If the sum of exponent is more negative than
explained with the help of flow chart as follows: 126 then it results to underflow.
Finally check for the proper results:
X Y
TABLE III: COMPARISON TABLE
1 8 23 1 8 23 Exponent Mantissa Number represent
Sign Exponent Mantissa Sign Exponent Mantissa Zero Zero Zero
Zero Non zero Denormalized Number
23 23
1 1 8 8 1 to 254 Anything Floating point number
Booth
Subtract Multiplier
127
255 Zero Infinity
XOR
255 Non-zero Not a Number
Carry 48
Exponent Normalize
1
Adder D. Radix 4 Booth Multiplier
The speed of operation is of ample concern in numerous
1 8 23
applications. One way to boost up the multiplication is to
incorporate parallelism to impoverish the number of partial
Sign Exponent Mantissa
products. In the proposed design radix 4 booth recoded signed
multiplier is adopted for mantissa multiplication which
32
enhances the parallelism. The partial products are reduced to
Z
half by radix4 booth recoding multiplier. The approach to
Fig. 7:Floating Point Multiplier recoding is that in preference of shifting and adding for each
column of the multiplier term and multiplying by 1 or 0, take
1. Floating point number representation: The inputs are only every second column, and multiply by ±1, ±2, or 0, to
given in binary format which should be first decoded attain the equivalent outcomes. The booth recoding implies
into the IEEE 754 standard representation format. that consider the bits in block of three with overlapping such
that MSB of first group is LSB of second group. The
2. Check for zero input: Check the input values if any categorization starts from LSB. The first group is of two bits
one of the input is zero, then the result will be zero. and later groups are of three bits which is shown as follows:
3. Computation of sign: In multiplication if any one of
the input sign is negative or if the sign of both the 0 1 0 1 1 0 1 0 1 0
input is different then the sign of output will be
negative and if the sign of both the inputs are either Fig. 8:Grouping Logic
positive or negative i.e. if they are same then the sign
bit of output will be positive. This resembles to the Each encoded digits of multiplier Y performs specified
truth table of XOR hence the sign bit of result is operations on multiplicand X. At each step partial product is
calculated by XORing of sign bit of multiplier and provoked, all the partial products are added with the carry look
multiplicand. 1 indicates positive sign and 0 indicate ahead adder to get the eventual multiplication result which is
negative sign. as shown below:

1952
 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India

TABLE IV: BOOTH ENCODING TABLE VI: AREA COMPARISON OF FLOATING POINT
Block Re-coded digit Operation on X MULTIPLIER
000 0 0X Existing unit Proposed unit
FPGA
Reference 4 input 4 input
001 +1 +1X family Slices Slices
LUTs LUTs
010 +1 +1 X
Ref [7] Virtex 4 976 1091 554 1066
011 +2 +2 X
Ref [9] Spartan 3E 1269 2270 554 1066
100 -2 -2 X
Ref [9] Virtex 4 1269 2270 554 1066
101 -1 -1 X
Ref [10] Spartan 3 1208 2270 554 1066
110 -1 -1 X
111 0 0X
The graph showing optimization in the area in terms of
slices is as follows:
IV. RESULT AND ANALYSIS
The floating point arithmetic unit is coded in Verilog
HDL, synthesized and simulated on Xilinx 13.1 ISE simulator
and implemented on Spartan 6 FPGA. The maximum
combinational path delay of floating point multiplier is 20.105
ns and of radix 4 booth multiplier is 19.286 ns. The
performance comparison of implemented floating point
multiplier with referenced research paper in terms of critical
path delay is as summarized in following table:
TABLE V: DELAY COMPARISON OF FLOATING POINT
MULTIPLIER
Existing unit Proposed unit
Reference FPGA family
delay delay
Ref [7] Virtex 4 18.783 16.721 ns
Fig 10: Comparison of slices
Ref [8] Spartan 6 49.797 ns 20.105 ns
Ref [9] Spartan 3E 34.333 ns 31.578 ns
The graph showing saving in the area in terms of look up
tables (LUTs) is as follows:
Ref [10] Spartan 3 29.72 ns 22.597ns

The optimization of speed in floating point multiplier as

compared to the referenced papers is as shown below:

Fig 11: Comparison of LUTs

The maximum combinational logic delay of floating point

adder is 25.494 ns. The performance comparison in terms of
critical path delay is as shown in following table:
TABLE VII: DELAY COMPARISON OF FLOATING
POINT ADDER
Proposed unit
Reference FPGA family Existing unit delay
delay

Fig. 9: Delay Comparison of floating point multiplier Ref [11] Virtex II pro 30.67 ns 25.494 ns
Ref [12] Virtex II pro 51.54 ns 25.494 ns
The comparison of resource usage of floating point multiplier Ref [13] Virtex II pro 27.059 ns 25.494 ns
with referenced research papers is as follows:
The optimization of speed in floating point adder is as
shown in following graph:

1953
 IEEE International Conference On Recent Trends In Electronics Information Communication Technology, May 20-21, 2016, India
REFERENCES
[1] K.M. Mukund, Sudharsan Seshadri, JanarthananDevarajululand M.
Kannan'A, “ 1 GHz Pipelined Low Power Floating Point Arithmetic
Unit with Modified Scheduling for High Speed Applications” IEEE
International conference on Signal Processing, Communications and
Networking 2007.
[2] ShahabArdalan, Akbar Adibi, “Design, Simulation and Synthesis ofa 32-
bit Math-ProcessorCircuits and Systems”, IEEE 48th Midwest
Symposium 2005.
[3] Ushasree GR Dhanabal, Dr. Saratkumarsahoo, “VLSI Implementation of
a High Speed SinglePrecision Floating Point Unit Using Verilog”, IEEE
Conference on Information and Communication Technologies 2013.
[4] Sonali M. Rane, Prof. Mrs. TruptiWagh, Dr. Mrs. P. Malathi, “FPGA
Implementation of Addition/Subtraction Module for DoublePrecision
Floating Point Numbers Using Verilog”, IEEE International Conference
on Advances in Engineering & Technology Research 2014.
Fig. 12:Delay Comparison of floating point adder/subtractor [5] Weiqiang Liu, Chenghua Wang, Fabrizio Lombardi, “Design and
Analysis of Inexact Floating-Point Adders”, IEEE Transactions on
TABLE VIII: AREA COMPARISON OF FLOATING Computers, Vol. 65, No. 1, January 2016.
POINT ADDER/SUBTRACTOR [6] Rajit Ram Singh, Asish Tiwari, Vinay Kumar Singh, Geetam S Tomar,
Proposed “VHDL environment for floating point Arithmetic Logic Unit -ALU
Features Ref [13] Ref [14] Ref [15] design and simulation”, International Conference on Communication
unit
Systems and Network Technologies 2011.
Slices 541 495 464 368 [7] Arish S, R.K.Sharma, “Run-time reconfigurable multi-precision floating
4 input point multiplier design for high speed, low-power applications”, IEEE
- - 805 660 International Conference on Signal Processing and Integrated Networks
LUT’s
2015.
IOB’s - - 101 106 [8] Paldurai.K, Dr.K.Hariharan, “FPGA Implementation of Delay
Optimized Single Precision Floating point Multiplier”, IEEE
International Conference on Advanced Computing and Communication
As shown in the table VIII there is 31% of saving as Systems 2015, Coimbatore, INDIA.
compared to reference [13], 25% of saving as compared to [9] Anna Jain, Baisakhy Dash, Ajit Kumar Panda, “FPGA Design of Fast
reference [14] and 20% of saving as compared to reference 32-bit floating point multiplier unit”, IEEE International Conference on
[15] in terms of slice utilization. The comparison of resource Device , Circuit and System, 2012.
usage floating point adder with reference [15] is as follows:

Fig. 13:Comparison of resource usage

V. CONCLUSION
The proposed design with the proposed algorithms and
arithmetic units accommodate an imperforate IEEE
compatible arithmetic system which is competent of
accomplishing floating point arithmetic operations with high
speed. Performance of the proposed design is compared with
research papers in terms of critical path delay and it is
contemplated that there is upto 59% of optimization in critical
path delay of floating point multiplier and 50 % of
optimization of floating point adder/subtractor. The result
manifest that proposed design is speed optimized as well as
area efficient.

1954