Task 1

Verilog Code
module task1(KEY, LEDR);
    input [1:0]KEY;
    output [9:0]LEDR;
    assign LEDR[8]= 0;
    
    counter c_8 (.Clock(KEY[1]),.Reset(KEY[0]),.Q(LEDR[7:0]),.rollover(LEDR[9]));
        defparam c_8.n = 8;
endmodule

module counter (Clock, Reset, Q, rollover);
    parameter n = 4;
    wire [n-1:0]k = 20;
    input Clock, Reset;
    output reg [n-1:0] Q;
    output reg rollover;
    always @(posedge Clock or negedge Reset)
    begin
        if (!Reset)
            Q <= 1'd0;
        else
        begin
            if (Q == k-1)
            begin
                Q <= 0;
                rollover <= 1;
            end
            else
            begin 
                rollover <= 0;
                Q <= Q + 1'b1;
            end
        end
    end
endmodule
 Pin Assignment
Signal Pin
Clock KEY [ 1 ]
Reset KEY [ 0 ]
Count (Q) LEDR [ 7 : 0 ]
rollover LEDR [ 9 ]

Test-bench Code
module task1_tb();

    reg [1:0] KEY;                                     
    wire [9:0] LEDR;
                       
task1 t (KEY, LEDR);
// KEY[ 1 ] clock
initial
begin
    KEY[1] = 1'b0;
    KEY[1] = #30 1'b1;
    # 10;
    repeat(48)
    begin
        KEY[1] = 1'b0;
        KEY[1] = #10 1'b1;
        # 10;
    end
end 
// KEY[ 0 ] reset
initial
begin
    KEY[0] = 1'b1;
    KEY[0] = #10 1'b0;
    KEY[0] = #10 1'b1;
end 
endmodule

Symbol files
Timing Simulation

RTL viewer
 Task 2

Verilog Code
module task2(CLOCK_50 ,KEY, HEX0, HEX1, HEX2, s, Q0, Q1, Q2);
    input  KEY;
    input CLOCK_50;
    output [6:0] HEX0,HEX1,HEX2;
    output s;
    assign s = 1;
    output [3:0] Q0, Q1, Q2;
    wire r1,r2,r3;
    s_counter sec (CLOCK_50, KEY, s);
    counter a (.Clock(CLOCK_50),.Reset(KEY),.Q(Q0),.s(s), .rollover(r1));
    counter b (.Clock(CLOCK_50),.Reset(KEY),.Q(Q1),.s(s&r1),.rollover(r2));
    counter c (.Clock(CLOCK_50),.Reset(KEY),.Q(Q2),.s(s&r1&r2),.rollover(r3));
    decoder d0 (Q0, HEX0);
    decoder d1 (Q1, HEX1);
    decoder d2 (Q2, HEX2);
endmodule

module counter (Clock, Reset, Q, s, rollover);
    parameter n = 4;
    wire [n-1:0]k = 10;
    input Clock, Reset,s;
    output reg [n-1:0] Q;
    output reg rollover;
    always @(posedge Clock or negedge Reset)
    begin
        if (!Reset)
            Q <= 1'd0;
        else
        begin
            if(s)
            begin
                if (Q == k-1)
                begin
                    Q <= 0;
                    rollover <= 0;
                end
                else if (Q == k-2)
                begin
                    rollover <= 1;
                    Q <= Q + 1'b1;
                end
                else
                begin 
                    rollover <= 0;
                    Q <= Q + 1'b1;
                end
            end
        end
    end
endmodule
module s_counter (clk, reset, rollover);
    parameter n = 26;
    input clk, reset;
    reg [n-1:0] Q;
    integer i;
    output reg rollover;
    
    always@(posedge clk or negedge reset)
    begin
        if(!reset)
        begin
            Q <= 0;
            rollover <= 0;
        end
        else
        begin
            if ((Q[25]==1)&&(Q[24]==1)&&(Q[23:0]==0))
            begin
                rollover <= 1;
                Q <= 0;
            end
            else
            begin
                Q <= Q+1;
                rollover <= 0;
            end 
        end
    end
endmodule
module decoder (V, H);
        input  [3:0]V;
        output [6:0]H;
        assign H[0] = (V[2]&~V[1]&~V[0]) | (~V[3]&~V[2]&~V[1]&V[0]);
        assign H[1] = (V[2]&~V[1]&V[0]) | (V[2]&V[1]&~V[0]);
        assign H[2] = (~V[2]&V[1]&~V[0]);
        assign H[3] = (~V[2]&~V[1]&V[0]) | (V[2]&~V[1]&~V[0]) | (V[2]&V[1]&V[0]);
        assign H[4] = (V[0]) | (V[2]&~V[1]);
        assign H[5] = (~V[2]&V[1]) | (V[1]&V[0]) | (~V[3]&~V[2]&V[0]);
        assign H[6] = (V[2]&V[1]&V[0]) | (~V[3]&~V[2]&~V[1]);
endmodule

Pin Assignment
Signal Pin
Clock CLOCK_50 
Reset KEY
Count 0 HEX [ 0 ]
Count 1 HEX [ 1 ]
Count 2 HEX [ 2 ]

Test-bench Code

module task2_tb();
    reg CLOCK_50;
    reg KEY;                                                  
    wire [6:0] HEX0, HEX1, HEX2;
    wire [3:0] Q0, Q1, Q2;
    wire s;
task2 t (CLOCK_50 ,KEY, HEX0, HEX1, HEX2, s, Q0, Q1, Q2);
// CLOCK_50
    always
    begin
        CLOCK_50 = 1'b0;
        CLOCK_50 = #10000 1'b1;
        # 10000;
    end
// KEY reset
initial
begin
    KEY = 1'b0;
    KEY = #10000 1'b1;
end 
endmodule

Symbol files

Timing Simulation

RTL viewer
 Task 3

Verilog Code
module task3(CLOCK_50,KEY,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,Q0,Q1,Q2,SW);
    input [2:0] KEY;
    input CLOCK_50;
    input [7:0] SW;
    output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5;
    output [7:0] Q0, Q1, Q2;
    wire s = 1;
    wire [3:0]k1 = 10;
    wire [3:0]k2 = 6;
    wire [3:0] Qa,Qb,Qc,Qd,Qe,Qf;
    wire r1,r2,r3,r4,r5,r6;
    assign Q0 = {Qa,Qb}; assign Q1 = {Qc,Qd}; assign Q2 = {Qe,Qf};
    counter a0(CLOCK_50,KEY[2],!KEY[0]&s,Qb,r1,k1,1'b0,SW[3:0]);
    counter a1(CLOCK_50,KEY[2],!KEY[0]&s&r1,Qa,r2, k1,1'b0,SW[7:4]);
    counter b0(CLOCK_50,KEY[2],!KEY[0]&s&r1&r2,Qd,r3,k1,1'b0,SW[3:0]);
    counter b1(CLOCK_50,KEY[2],!KEY[0]&s&r1&r2&r3,Qc,r4,k2,1'b0,SW[7:4]);
    counter c0(CLOCK_50,KEY[2],!KEY[0]&s&r1&r2&r3&r4,Qf,r5,k1,KEY[1],SW[3:0]);
    counter c1(CLOCK_50,KEY[2],!KEY[0]&s&r1&r2&r3&r4&r5,Qe,r6,k2,KEY[1],SW[7:4]);
    decoder d0 (Qa, HEX1); decoder d1 (Qb, HEX0); decoder d2 (Qc, HEX3);
    decoder d3 (Qd, HEX2); decoder d4 (Qe, HEX5); decoder d5 (Qf, HEX4);
endmodule
module counter (Clock, Reset,s, Q, rollover,k,preset, In);
    parameter n = 4;
    input [n-1:0]k,In;
    input Clock, Reset,s,preset;
    output reg [n-1:0] Q;
    output reg rollover;
    always @(posedge Clock or negedge Reset)
    begin
        if (!Reset)
        begin
            Q <= 1'd0;
        end
        else
        begin
            if(preset)
            begin
                Q <= In;
            end
            if(s)
            begin
                if (Q == k-1)
                begin
                    Q <= 0;
                    rollover <= 0;
                end
                else if (Q == k-2)
                begin
                    rollover <= 1;
                    Q <= Q + 1'b1;
                end
                else
                begin 
                    rollover <= 0;
                    Q <= Q + 1'b1;
                end
            end
        end
    end
endmodule
module decoder (V, H);
        input  [3:0]V;
        output [6:0]H;
        assign H[0] = (V[2]&~V[1]&~V[0]) | (~V[3]&~V[2]&~V[1]&V[0]);
        assign H[1] = (V[2]&~V[1]&V[0]) | (V[2]&V[1]&~V[0]);
        assign H[2] = (~V[2]&V[1]&~V[0]);
        assign H[3] = (~V[2]&~V[1]&V[0]) | (V[2]&~V[1]&~V[0]) | (V[2]&V[1]&V[0]);
        assign H[4] = (V[0]) | (V[2]&~V[1]);
        assign H[5] = (~V[2]&V[1]) | (V[1]&V[0]) | (~V[3]&~V[2]&V[0]);
        assign H[6] = (V[2]&V[1]&V[0]) | (~V[3]&~V[2]&~V[1]);
endmodule

Pin Assignment
Signal Pin
Clock CLOCK_50 
Reset KEY [ 2 ]
SW preset KEY [ 1 ]
Clock Holder KEY [ 0 ]
minutes HEX [ 5 : 4 ]
seconds HEX [ 3 : 2 ]
1 HEX [ 1 : 0 ]
(second)
100
Min Input SW [ 7 : 0 ]
 Test-bench Code
module task3_tb();
    reg CLOCK_50;
    reg [2:0] KEY; 
    reg [7:0] SW;   
    wire [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
    wire [7:0] Q0, Q1, Q2;                  
    task3 t (CLOCK_50,KEY,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,Q0,Q1,Q2,SW);
    // CLOCK_50
    always
    begin
        CLOCK_50 = 1'b0;
        CLOCK_50 = #50 1'b1;
        #50;
    end 
    // KEY[ 2 ]
    initial
    begin
        KEY[2] = 1'b0;
        KEY[2] = #10 1'b1;
    end 
    // KEY[ 1 ]
    initial
    begin
        KEY[1] = 1'b0;
        KEY[1] = #1000000 1'b1;
        KEY[1] = #40000 1'b0;
    end 
    // SW[ 7 : 0 ]
    initial
    begin
        SW = 0; #900000
        SW = 5;
        SW = #400000 0;
    end 
    // KEY[ 0 ]
    initial
    begin
        KEY[0] = 1'b0;
        KEY[0] = #280000 1'b1;
        KEY[0] = #10000 1'b0;
        KEY[0] = #270000 1'b1;
        KEY[0] = #10000 1'b0;
    end 
endmodule
 Timing Simulation
Transition from 100th of a second  second

59 minutes complete  0 min

Holding clock when KEY[0] is being pressed

Presetting minute value from SW when KEY[1] is pressed

Symbol files

RTL viewer
 Task 4

Verilog Code
module part4(KEY, LEDR, SW, CLOCK_50);
    input [1:0] KEY; // KEY[1] for display and KEY[0] for reset
    input [2:0] SW;  // To input Alphabet
    input CLOCK_50;  // clock signal
    wire [1:0] Q;
    output reg LEDR; //Morse Code on LED
                                         // State Encoding
    parameter [2:0] ON=3'b000,OFF=3'b001,Rest=3'b010,Dash=3'b011,Dot=3'b100,Delay=3'b101;
                                         // Alphabet Encoding
    parameter [2:0] A=3'b000, B=3'b001, C=3'b010, D=3'b011,
                         E=3'b100, F=3'b101, G=3'b110, H=3'b111;
    reg [2:0] size, s; // size of code of current alphabet
    reg [3:0] code;           // code of current alphabet
    reg [2:0] n_state;        // next state
    reg [2:0] p_state; // present state
    reg alph_end,r;    // alph_end-> end of alphabet code | r-> counter reset
    wire dash_end, rollover;  // dash_end -> indicates end of dash
    wire dot_end, u_delay,a;  // dot_end -> indicates end of dot
    assign u_delay = dot_end; // delay between pulses is same as duartion of dot i.e. 5 secs
    assign a = code[s];       // either a dot or dash
    
    always @(negedge KEY[1])
    begin
        case (SW)
            A: size <= 3'b010;
            B: size <= 3'b100;
            C: size <= 3'b100;
            D: size <= 3'b011;  // updating size of alphabet present on input port SW
            E: size <= 3'b001;
            F: size <= 3'b100;
            G: size <= 3'b011;
            H: size <= 3'b100;
            default: size <= 3'bxxx;
        endcase
    end
    always @(negedge KEY[1])
    begin
        case (SW)
            A: code <= 4'b1110;
            B: code <= 4'b0001;
            C: code <= 4'b0101;
            D: code <= 4'b1001;
            E: code <= 4'b1110;  // updating code of alphabet present on input port SW
            F: code <= 4'b0100;
            G: code <= 4'b1011;
            H: code <= 4'b0000;
            default: code <= 4'bxxxx;
        endcase
    end
    
    always@(posedge CLOCK_50, negedge KEY[0])
    begin
        if (!KEY[0]) p_state <= Rest;
        else p_state <= n_state;  // sequential block for hopping n_state to p_state     
    end
    always@(*)
    begin
        if ((p_state == ON)|(p_state == OFF)) r = 1; // restarting counter
        else                                  r = 0;
    end
    
    always@(*)
    begin
        if ((p_state == Dash) | (p_state == Dot))
        begin
            LEDR = 1;              // Output logic block
        end
        else 
            LEDR = 0;
    end
    
    always@(*)
    begin
    case(p_state)                // Next State logic block
        ON:                    
        begin                
            if (a) n_state = Dash;
            else     n_state = Dot;
        end
        
        OFF: 
        begin
            n_state = Delay;
        end
        
        Delay: 
        begin
            if(alph_end)    n_state = Rest;
            else         
            begin
                if (u_delay) n_state = ON;
                else         n_state = Delay;
            end
        end
        
        Rest: 
        begin
            if (!KEY[1])  n_state = ON;
            else            n_state = Rest;
        end
        
        Dash: 
        begin
            if (dash_end) n_state = OFF;
            else          n_state = Dash;
        end
        
        Dot: 
        begin
            if (dot_end)  n_state = OFF;
            else          n_state = Dot;
        end
        
        default:  n_state = Rest;
    endcase
    en 
    s_counter sec (CLOCK_50, r|!KEY[0], rollover); // 0.5 sec counter
    counter c (CLOCK_50, r|!KEY[0], dot_end, dash_end, Q, rollover); 
    // ^ 2 bit counter (0,0.5,1,1.5)
    wire x = (p_state == Rest) ,y = ((p_state == Dash)|(p_state == Dot)), z = (s == size);
    always @(negedge KEY[0] or posedge CLOCK_50)
    begin
        if (!KEY[0])   // s variable for iterating the size of code
        begin
            s = 3'b000;
        end
        else
        begin
            if(x)
            begin
                s = 3'b000;
            end
            else if(y)
            begin
                s = s + 3'b001;
            end
            else
            begin
                s = s;
            end
        end
    end 
    always @(negedge KEY[0] or posedge CLOCK_50)
    begin
        if (!KEY[0])
        begin
            alph_end = 0; //alph_end variable for indicating end of alphabet code
        end
        else
        begin
            if(z)
            begin
                alph_end = 1;
            end
            else
            begin
                alph_end = 0;
            end

            if(x)
            begin
                alph_end = 0;
            end
        end
    end 
endmodule

module counter(clk, reset, dot_end, dash_end, Q, z);
    input clk,reset,z;
    output reg [1:0] Q;
    output reg dash_end, dot_end;
    always@(posedge clk or posedge reset)
    begin       // 2 bit counter for pulses in (0-3) multiples of 0.5 secs
        if(reset)
        begin
            Q<=0; dot_end <=0; dash_end<=0; 
        end
        else
        begin
            Q <= z? Q + 2'b01: Q;
            if(Q == 1)
            begin
                dot_end <= 1;
            end
            else if (Q == 3)
            begin
                dash_end <= 1;
                dot_end <= 0;
            end
            else 
            begin
                dot_end <= 0;
                dash_end <= 0;
            end
        end
    end  
endmodule
module s_counter (clk, reset, rollover);
    input clk, reset;        // counter for exact 0.5 sec period
    parameter n = 25;
    reg [n-1:0] Q;
    integer i;
    output reg rollover;
    always@(posedge clk or posedge reset)
    begin
        if(reset)
        begin
            Q <= 0;
            rollover <= 0;
        end
        else
        begin
            if ((Q[24]==1)&&(Q[23]==1)&&(Q[22:0]==0))
            begin
                rollover <= 1;
                Q <= 0;
            end
            else
            begin
                Q <= Q+25'b1;
                rollover <= 0;
            end 
        end
    end 
endmodule
 Pin Assignment
Signal Pin
Clock CLOCK_50 
Reset KEY [ 0 ]
Display ON key KEY [ 1 ]
Alphabet SW [ 2 : 0 ]
Morse code display LEDR [ 0 ]

Test-bench Code
`timescale 1 ns/ 1 ps
module part4_tb();
reg CLOCK_50;
reg [1:0] KEY;
reg [2:0] SW;
wire LEDR;
part4 t(KEY, LEDR, SW, CLOCK_50);
// CLOCK_50
always
begin
    CLOCK_50 = 1'b0;
    CLOCK_50 = #10 1'b1;
    #10;
end 
// KEY[ 1 ]
initial
begin
    KEY[1] = 1'b1;
    KEY[1] = #25 1'b0;
    KEY[1] = #10 1'b1;
    KEY[1] = #2550000001 1'b0;
    KEY[1] = #30 1'b1;
end 
// KEY[ 0 ]
initial
begin
    KEY[0] = 1'b1;
    KEY[0] = #10 1'b0;
    KEY[0] = #10 1'b1;
end 
// SW[ 2 ]
initial
begin
    SW[2] = 1'b0;
end 
// SW[ 1 ]
initial
begin
    SW[1] = 1'b0;
    SW[1] = #2550000000 1'b1; 
//   SW[1] = #60 1'b0;
end 
// SW[ 0 ]
initial
begin
    SW[0] = 1'b0;
    SW[0] = #2550000000 1'b1;
//   SW[0] = #60 1'b0;
end 
endmodule

Timing Simulation

Morse code for A Morse code for D

Symbol files
 State Machine Viewer

State Machine

State Transitions

State Encoding Description

ON 000 Turning LED on for either Dash/Dot
OFF 001 Turning LED off for either delay between pulses or at the end of
Morse code display for input alphabet
Rest 010 Idle state, nothing is done until KEY[1] is pressed
Dash 011 For displaying a 1.5 sec light pulse on LED
Dot 100 For displaying a 0.5 sec light pulse on LED
Delay 101 For delay between pulses