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    Vlsi Design

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    Shivam Chaudhary

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    ers QUANTUM Series VLSI Design Topic-wise coverage of entire syllabus : in Question-Answer form. | | » Short Questions (2 Marks) | | PUBLISHED BY: QF tym Publica ata obstn ste: w.quantumpage.cain tas Noga, Shabara, Delhi110082 Bast Rohtas Noes opt of rato ay pai weit La yang mes wt pom inary fw yam me iy derived om sources ‘eration cond in ts wom ensure arabe ae ern er re plier te eas remem orn ant bp res epi ny eer, nisin 0 Spot oe of i rman sou ‘VLSI Design (BC: Sem-7) 1 Bion : 201112 201213 2019.14 201s 2015.16 201647 201718 201819 201920 REC-702 ; VISI Desi ‘UNIT! : INTRODUCTION TO Vist csc) Introduction: A Brie History, Preview, MOS Transistor CMOS Legic,CMOS Fabrication ad Layout, Design Parioning, Lagi Design, Circuit Design, Physical Design, Design Verfcation, Fabrication, Packaging and Testing, UNIT; DELAY AND POWER (40c64c) ‘Delay lntrouction, Transient Response, RC delay model Linest Delay Model Local ifort of Pats Taming Analy elay Modes Power Ineoduction, Dynamic Power, Satie Power. UNITS : INTERCONNECT (65c-860) Energy ~ Delay Optimization, Love Power Architectures Interconnect: ntoduction, Interconnect Modeling Interconrect Impact nterconnect Engineering, Logical Effort wit Wires, UNIT : DYNAMIC LoGiC ciRcURTS (e7c—120) Dynamic logic circuits: Introduction, base principle of pase transistor crus, synchronous dynamic cicult techniques, <éymamie CMOS circuit teciriques, domino CMOS lope Semiconductor memories: Inodsction DRAM, SRAM, ROM, ashmemory. UNITS: LOW-POWER CMOSLOGICCIRCUTS (123-158) {Low ~Pomer MOS Logi Cuts: troduction Overview of Power Consumption, Low ~ Power Design tough vllape scaling, Estimation and Optimization of swching activity, Reduction of ‘Switched Capacitance and Adib Loge Cheuk: Design fr Testability: Introduction, Fault Types and Modes, Controllability and Observabilty, Ad Hoe Testable Design Techniques Techniques Scan Based and BIST Te ‘SHORT QUESTIONS (89-1760) ‘SOLVED PAPERS (2016-1770 2018-19) ace ‘Scanned wih CamScanner repr outline: Part pe Girton PART 1] 5 CONCEPT GUTLINE : PART-1 ‘When we plot log ofthe component count ava function oftine, ‘we get a traigh line, indieating that there has been an ‘exponential rowthin the complexity of hips over thee decades + The component count has roughly doubled every 18months, 8 was noted early by Gordon Moore, This reglar doubling is now ae Moors law (CMOS technology provides twotypesof transistors: sntype transistor aMf0S) ptypatransstr (pMOS) ‘Transistor operation is based on clectri elds the devices are also called Metal Oxide Semiconductor Field Eet Transistors (MOSFET cesiply FETS. Questions Anewers tere Long Answer Type and Medium Answer Type Questions gone Quoi, | Briety describe the evolution and enhancement of tegrated circ an "The cletronice industry has achieved a phenomenal growth ver the last few decades, mainly duo tothe raid advances in integration technologies 2. Typically the required computations and information processing power thes applications isthe driving freofor the fast development this Sal Era Year | Complexity Single transistor 1958 | <1 Uri loge ne gt) 1960 | 1 Multenetin ser | 2 Complex funtion see | 5 ‘Median Sal Integration (SD) 167 Lungs Seal Integration CSD) 192 Very Large Sele Integration (LS) | 1978 ‘itn Large Seale Tntepration (ULSD) | 1989 ‘Scanned wih CamScanner emene rites ea he met ne ee : Ahetnceasig ee ¥O coats A Mist ra en cea demain eerie “a Toei ie ee sm 1k Leper cons 2 pan teingreate SL ge rein. her, ren ted ‘nim entre si oe 41 itso the evn fhe nina of transistors ie tern a fe edo a Fe te lng nvr se eset erent TE, ete mtg er a Er Cen i eaoeacc octyl ase eer urge numberof fonction 09 singe ntaataytem evel pdr improvedonchipinteronnre, tegration wil contin in foresceaby Reel 200 1978 19801885 80 1995 gt09 2005 2011 Pett. RETR] sate Moore's Law. VLSIDesign 180-7 C aawer 1 ThelCwasinvented in February 1959 by Jack Kilby of Tens Instrument. ‘Theplanar version ofthe C war developed by Robert Noye at Piri induly 1950 2 Since then the evolution of this technology has bren exicemely fst pier, One ay ogg the procs he ld ia tolok atthe complexity of 12 ana function of ime, When wept log ofthe component count aa function of time, we get ‘etrnight ine, indicating tht thee has been am exponetial growth in th complet of ehipn aver three dee 4 The component count has roughly doubled every 18 maths, a8 was rtrd arity Gordon Moore This teguae doubling known a Moore's law |The min factor that has enbled this increase of eomplesty i the bly toahrink or scale dees. 6 Clesty, on can pack a Icger numbse of corspooents with greater Tanctionalityon 0 10 they are smaller, ale being advantageous in terms of fster Is hich conse less owe 1. Pig. 12.1 shows the level ointegeationvervua time for memory chips, 108 in roost Number or oa ‘yerchip 1 10K 10K 1975 1680 VeSs ovo 1005 2000 2010 2911 8 Iteante ctaered that interma cf transistor count, logic chipa contain greatly ower transistors any given ears mainly det large Consumption ofehip area for complex intereanneets- 2. Memory circuits are highly regula and thus more cll can be integrate wrth much lees area for nereonnect ‘Scanned wih CamScanner - 2408 14 abe peroneal 30, Td i on lable Prenat let etry 1 ro echoes fri to several hundred of Ui op 12 Bipolar and gailium ase = coo so ay rman 1 es aces Feria nt nd wrk of rita, =. FE cammsin: 1 i femmes - I ieicaedaenin 2 Tra raglan ofthe ain, the ifsion of impute in rea ittieyecaticn cag Shee eranraraaeron ea source Gate Drain cd Pepsin 80), ey paki abate si ‘s @ 4 Crosections and symbol of aMOS transistor and pMOS transistor re shown in Fig 13 The oe and pe repons indicate heavily doped Srorpapeciicn. ach rans cos of stackof the conducting gat, an insulating lef elon id andthe icon wate caldera, x bl. The gates typical formed fom polyerystaline acon obi, 7 5 AnnMOS ansistor ist witha ptype bd and has regions of ype ‘semiconductor act othe gate called the source end drain, A pOS ons of pipe source and drain region with an hype ‘ransitor VLSIDenien eacne = ——_____saone ‘Working of MOB Feanantores ojala oy flea cet these aa rin Kee, ener 08 tranisarTh ly igneraly rounded whe junctions ofthe wre and drain oblate even ane {fhe gat in he prounde,n caret ws tug the teen baad een str OFF Eth ae wage ied trenton om let Gelato Ara re clon thn S80, ere, 2h og iri enh he decom utero an "thin rein under thee hare sive ostanan ‘ome romiconuctr Hane acd pao cron carne {ome fom woarce ta dain andeurentcan low. Way the anaitor BON ora pMOS transistor, the dy isheld a high potential, When the steals at high potential tbe souree and drain junctions are reverse Biased and no current Rows tothe tannitor i OFF. ‘When the gat voltage lowered, postive chargon are attested the “underside the S80, interac: Atl gate volage avert the channel and a ondactng path of psitv carriers informed fom source rain ao the tanaster is ON, summary, when the gate ofan MOS transstoris'the transsor {ON and there ea eanducting path fom ware to drain ‘pS rns he ppt eg ON whe te esr {00 Oren he ng Tc whe ote ia dinette toca: 0 ot 7 a ox 3 F : ma Tat eels an inte det, ‘Scanned wih CamScanner Introdoctionto Vigy swwone sagot CMOS inverter. win] rey deere be ness of Tamer quo iaverter or NOT ete sing 8 DATOS 1 ig Ll) shows 2 MOS ster eee OST geri OFF sd theo 2 Monte nmi" Me pal wf ea iti 3105 OFF, ad the Ys pug When Ashe inthe rth tale andthe sro en dre: ox ® ig A Ivete ia ans Ted OY = ‘TaeTR | sketch 2inpat CMOS NAND gate and also discuss it works 1 Pig 181 stovsa input CMOS WAND gata. itconsistsoftwo series mostra betwenY nd GND and parallel MOS ransisors either nyu or Bis 0a easton ofthe nMOS transistors wil at east one ofthe MOS transistors will be (OFF reakingthe path fom Ft GND, Buta least one ofthe pMOS Ltanistrswilbe ON retng ptf Fe SaiaawilbeON crating path fom Yo Vg, Hence, the outpet ce Mee eC ie ‘ A sD 3. beth inputs are‘ bath ofthe nMOS transistors willbe ON and both ofthe pMOS transistors wile OFF. Hone, the output willbe. 44 Thetruth table ie given below andthe eymbalisshownin Fig. 15.10) [AND gate truth table A [_B | paihaows network | pallup network [ ¥ |e OFF oN 1 ot on on 1 ij o on ox 1 1a on ojo ‘GEETR | Write a short note on combinational logic. eave 1L The inverter and NAND gates are examples of comaplomentary CMOS. logic gtes als called statie CMOS gates. In general fully complementary CMOS gatohas nMOS pulldown network ta connect the output to’ (GND) snd pMOS pull-up network to-onneet the ootpt oT (Vy) as shown in Fig. 164. The networks tre arranged such that one if ON and the other OFF for any inpat tern, 4. ‘TheNANDyate used aseresplldown network and parallel pull-up aetwork, 4. Twooriore transistors inserieareON nl ifallo the saris raise {AIeON. Toor more transistors parall are ON ifany ofthe parallel {ranisorsare ON. hi i lusteated nig, 6:2.0r MOS and pMOS transistor pair. By using combinations of these constructions, CMOS combiastionn! sates canbe constructed. ‘Scanned wih CamScanner Introductionto Vigy | pee en at ae ee eine ‘The crowbarredX level exists when © multaneculy turned ON," DP ad pull-down are eee 9 Pc air tp ed tac albup OFF | pullapON pll-dows OFF Z 1 pall-down ON ° wowtarred Go _ ‘GET, ] Sketch a 2input CMOS NOR gate and also discuss its working. eG a pad dS 1 -Adinpat NOR gateisshown in Fig 17.1, The nMOS trensietoreare in parallel to pull the output low when either input ie high, 2, The pMOS transistors are in series to pll the oitput high when both {inputs are low, asindieated bythe truth table o ‘4 Aawith the NAND gate there is never a eat in which the output ie crowbarredorlef floating [NOR gate truth table = : i ao Let? os ° » sg 1:13: NOR gt elo ab O)Y AT) ‘Scanned wih CamScanner Inmdotinnto gy Sn cate (07 foRctigg gionsfsris and para BRT aout genie aCe NERS sss * nt esata ites srebshae tee ents a selena a ¥ Sheen prs 2 renters Teeter (CDinw bi Seco dnerer == 7 cl o ind ene ae IK a b> gaat: 4. ThepMOSpalep netork iste conduction complement. Therefore, insist appear increas the pul-down network must appear ‘nywalelotbe lap ntwerktod wanitr: that appear in parallel {ne pulldown eerork ust apearinseriesin the pull-up network, [BESTA] suse «complementary CMOS gate computing 160OD. = 13s hn OR AND-IVER1 (OAD e 2 Rea\spldromtwptetatlortDin nde i inthe prema MisIDesn wEcne &_ The pS pullup networks the conduction rs {pale with he eres combination of, Band. ‘GueTIOl] Explin the concept of strong V and weak in pass Tarver 1. AnsMOStrasestor ean almest thon we aay pases a strong V. However the MOS transistor i imperfect at passing 2". The high iag eels somevbat less than Vy We sayit pases doraded or weak. 13. ApMOS transistor agin as the oposite behavior, posing song's iniogratd Ve The trandsor symbols and bhaviosare eunmarard perfect evteh when passing a Wand inFig 1102, ' «0 Input gy Outpat wos Enero soe sresg0 et sat sosed app deered 1 @ o © ' a0 Inpst gag Output pos Seed eo degraded 0 et s-0 sted 1ope-seoog 1 @ a - a cst tr ind Barat Oka, ig 107: “4. When an nMOS or pMOS is used alone in an imperfect switch, we cometines alt pas transistor. ‘Scanned wih CamScanner p08 tanto 10 pay aon HOS 28 Tacoma said jena in an pe Sth tor aa Fone ari ry eo ta gent ready hg soli ot se ce se Nee Tae by trstate buffer ? Also explain what doyou understand! ‘the operation of CMOS tristte inverter “ai shews ember treat butler When the enable input 1B a tang A jt einen ornay bate eg lee Disa 2 Whentheensileis 9, isle inate: vist ae ___nwene ‘Truth table for trntato ¥ 24 ae or ENvo ver yak oo a « ig. 112.2. Tritt nverte 8. Fig. 112.110) shows a tristat inverter. The output i actively driven fom Vag or GND, vi restoring loi gate. When EN is‘ Fig. 112.10, both enable transistors are OFF leaving theontpt Noting When EN ie'l Fig 1121, both enable transistors are ON. They are Coneeptvaliy removed fom the circuit, leaving a simple inverter. Fig, 112d chow embol forthe state inverter. ‘GeeLAS] What is multiplexer? Briefly discuss sbout twoinput transmission gate multiplexer and inverting multiplexer. “Answer “Amultipleser choses the output tobe one of several inputs hased ona select signal ‘Atwovinpat or 24 multiplexer, ehooces input D0 when the selec i” ‘and inpot D1 when the selec ‘The truthtable igen in Tale thelogefunctons Y= 5-D0+S- Dt snasion gates can be ted together to form compact input rahe in Fig. 1.13.00) The select and ita complement transmission patna any given fine he ‘Twotrans ‘Scanned wih CamScanner ‘VUSIDerign ering male snssion gates produce 6 ver out of gates in seyer® Agi, theansison FE ltl vera see rae - ssbornia 11326) Any ae ig One compen ran swnn F113.) Pfr =n : DO 5 ¥ stp o Tt o » : i. arene yt ca ttc Unoaal ice. Agsn, ifthe complementary select ig ro ee i Sorc SS bo: p-S or df mv 8 pm set & y Yo. SSH 5 pv pt © o ® RRR Tee SaaS ‘WRETAG] Raplain th operation of CMOS positiveevel-sensitive Daten. oR Describe the working of atch. al ‘AD ach ning Dap mei aves Fg Lidia) Iensnrafadatlape Dyadeck oper Leas ‘and complementary outpute Q and @. 2 When cua Renuie, Wee ied Ona td hard Ulavrerpurroasln Pgh ichaloiniancasen are Ginna ‘het tones sia Te malian ‘ostream parfait as een ax "the latch is transparent. @ = D and Q = B ® ® @ a Ter a cuke1 .} eukaa @ @ ux. aK > : pipe © o igs LAAL/OMOS psi oat stiveD teh 15 ‘The D-atchisalso knowns aleve sensitive latch because the state of the ouipt is dependent on the fovel of Ube clack signal, a shown in Fig. 114.1) The lateh show is postivelevel-snstive late, represented by the symbolin Fg. 114.10), ‘Scanned wih CamScanner 1 Introdvetionto Vig, iresmstve and Taw | sete ered nh Showy see wel i anes emer ang ‘ue first atch Beate se. see twrelsensitvelatchoutpt Qj) ex enn en ahha Sarees ‘hen the clecktrmsiBO ET Tg thetime ofthe clock transition, ne using ate nse ave QD th ele eereer aN legen che th des mrig e A ax ap VistDesign (BOC D-ove Ro yo a cuK=0 + @ Doe ae cuxet Lovo] L @ cu > @ © cu {Fs a ae |g: LARATOMOs pativeaige gga D io9 {6 Tasummary, this lipo copies D t Qo the ising ee ofthe clock, ts shown in Fig. 1.15.1, Ths, this device i called poitve-edes {vigered Hipp also called aD pop, D register or mater eave Aipfap Fig. .15. shows the ict symbol fo the ip op. ‘oe TI6 | How hotd-time problems are avoided in flip ops ? on, Explain the role of two-phase non-overlapping élocks in CMOS, fip-0p, Taawer Flip-flops may experience old time failure ifthe syatom hastoo much lock skow, fone Mp lop teagers early and another triggers late ‘ecauseof variations in clock arrival tine. ‘When desigatimeis more important bod time-problems canbe voided altogether by distributing atwo-phase nonoverlapping clock. ‘Scanned wih CamScanner tn oping path ro ip don eM ean with WRK tt Ed etn Pret enable signals to eset il Ney a Cae ae T % eon ty in ets woe NED ey ag ssc. sion nd Ls, Dein Portining Lage Dey os abi ea Dein, Design Verification, a) rt Den Packaging and Testing. ae Fee ele a dee rari Di0setnnbnn ‘sStin etaitenetoe ceeeemaacec Naan ya mtandih sie sea alyeraetnee ra Beceem tartan eerie mance Seen ocean Sipe Oso thus allow Enea, proportional ealing ++ Digital VLSI design is often partitioned five levels of See ered a ate ISI Deen —— —— — Ta Aniwee Typo nd Mdm Aner Qooktt | Discuss Aaa Si QuoatioasrAnswore low. Show mupporting figure for ench fabrication step. 1. 1. 2 ‘The uation procs involved agetof ptterned layers of doped ico, pliant ond insulting silicon dioxide Initially icon substrate have tobe taken as shown n Fig..17.10) “The soquence starts with the thermal oxidation ofthe sian surface, {estan gronth of about 1 mam thickness of SiO, layer as ehown ia Fig. L170, “Theentir ayer ecoated withthe aubxtance called photoresist, whichis Slight sensitiv, ei-resist organi polymer ax shown in Fig 147.10, ‘When photoresist material is exposed to UV light the exposed portion ‘eeome sft othe solvents can easily etch hat portion, ‘To select the specified position for exposure we we mas pseage af UV light fom ts transparent portion ashown a Fig. LI. ‘Thetypeof photoresist intl hardin nature but when exposed ta ight becomessoft ar called ms postive photoresist, Following the UV exposure ste, the soft portion is etched of sing Solvent IF acd) a shown in Fig. L171). [Now the Si0, region which snot covered eam be etched away by using chemical solvents showin Fig. L170). ‘Woobtsin an oxide window tat reaches down athe silicon surface, the ‘esting poloreist ean now be stripped rom ret of SiO, surface by {sing another solvents as shown in Fig. L171). “The sequence of fbrizston step artuall ia single pattern transfer on tothe iO, surface. "The fabrication of semiconductor devies requires several uch pattern transfer tobe porformed on S10, polysilicon and metal. ‘Scanned wih CamScanner sa] R818 Drow the proce flow fr the fabrication of an PE = MOS ras on péype silicon substrate. i | i wont | sens Sati a ssobstalt | = = reer TT ge 80, (0a) | nytt piety xt stow ini 3380, ——s 2 The proces sat with heel ecidatone Sessa a shewa = Fig. 118.10). 4. Using ma and etch open th desired portion rom the mata as a van ® otainiie 116i00 andi Lissa 50, (sie lye) | simarte oe = ote Lime oe) ‘Si-substrate |+—— Mask 1 rs Opa peston | Tyna . Transparent postion | + eee BI Insabe photoresist | Crags pin Se 810, Oxide layer) TTS ont Siadaste faye salable ctor | a) eeneas TTB | : eescconre E J4— Si0, layer ard potresist. al Siebarte RE Fo, Orden | St 4 Th sures anny covered wth tin vd per whch forms the ete eof MOS ana " = 5. The complete surface is again covered using polysilicon as shown in E ard ptr Fa lini ie oan 6. ebatenin sd at gate dred ad friars medio. Sete 1 Ate epson the pli yer pated and teed form Ghotnnrouncetsand tbe MOS want gee 8 8. The thin gate oxide not covered by polysilicon is also etched a way, to FRE E50, onde oer | ‘rye te portion on wich te sores and rin jncins are tobe Sind ea dwn a LARA aN -Polysiticon layer. a BE nine a Oye Sma | e ‘Siaubstrate | ‘Scanned wih CamScanner eypeinpuct 0 taopamabbeeh nian ate LIB fasion fn AP ich patterned before doping, actully creg 10. ‘mime chamnelepon tnd oe theloeaton of tig sours dthe rnin SEO ed process, Once the source and 1, Sait mal nr wh ants Le eer te prove contact Window forte = “ Metal eantat Torlting oxide Thin de = FAK 50, nye o ‘Siaubstrate, ene 12. The mu iscovered with evaporated aluminum whi en porated aluminum which wil form the 18, Finly, the retal ayer is patterned P fs and etched completing the arimwctoa ofthe MOS transistors onthe surfaces shown 1, However, sand (er mise sg thd ayer of metalicinterconnect can alo be SETI] writes short note VUSTDesign aEC-DC Tomver 1. Layout design rules descite how smal features canbe and how closely ‘they ea be packed in particular manufuctring process. 2 Lambdacased design rales based on a single parameter 3, which characteries the rasation af the process, 5. generally half ofthe minim drawn transistor channel length. ‘Thislongthisthe distance betncen the source anddrainof a transistor andissetty the miamum width of poysion wie This dimension is ‘ypialy speed a micros fr dimensions above 038 ym = 180 nn sin nanometers belo. 44. MOStS has develped a set of sabe lambde-based design ues that Cover a wide ange of manufotaring processes 5. A setof design rules for layouts with two metal layers in an n-well process is follows ‘Meta and iffuson have minimum width and spacing’. Contacts are 2. 2h and must be surrounded by onthe layers above and below. + Payaltion uses with of 24, Palpiconoverop ison by where atranssorisdesrdandhas a spacing of away where ne transistor i desired + Pobycon and eontats have a spocng of fom other plyiicon or + Novell surrounds AOS transistors by 6. and avoids mMOS transistors bya Fig. 1194 show the basic MOSIS desig rales fora proess with wo tealiayers Transistor dimensions are often specified by thelr Widen (W rata, ‘Fig 1104. Sinpliod bosed dese rls. ‘Scanned wih CamScanner rao % peters iy thn erat detvertne same cure tt tick gram ora c0s 21apu NAND gle Faaaenrm tn aisha bie “peg inp nan atin 2 There arefour vertical wie tracks, uli track to give Tarorore frock, multiplied by Bt por track tog Tore are ve horizontal tracks giving a cellhght of 4% (ie. 8h x5). RETF] sketch a otick diagram for » CMOS gate computing Y= (AVBSOVD and eatimate the cell width and height. 1 Pe 12 teers res etinated el st aO bo gaa a verti pitches BOC SOO \ Gratis = 10h ‘ig. 131.1. CM0S compound gat Gao Tae] Why ¥echart is cose design flow ? Explain the three do function ¥ in implementation of VLSI ins of VLSI design flow. Rnewer 1. The chart was fiat introduced by D. Gaje. Y-Chart illustrates & ‘Tmplifed design flow for most loge chips, using design acivitos on ferent dmg which resemble the letter Y. ‘Yeh eat : Geonetiallaget dona Fig Lat: ‘Scanned wih CamScanner InrattionteVay ee eae ca nas esis Ma dae cet a ls, ne * Dashatian irene otc ccm os cmt aint ee, al hh Re ements et ete 2 Reierpetint optn be ered eal, ar A rrp STEAL] Draw and discuss in brief about top-level MIPS block, aiagram. LL The chip is partite into two toplevel units: the controller and Anpath as ehown abl diagram nig. 124.1. Saceal contre ih VAT rt he remainder icleconetdde 5. Avriterscedume er other cement. ANE fp op addr, multiplexer, ‘ofthe chip. Itcan be viewed ‘stein mene © ‘Avera the tga an be ved aight wove fal. ‘ach ital one a a eh cpus sang rte brant ‘ea comecing he its topther 1 Duling tapas sng wordnice i urlyeser tense can ‘roche, such athe sore detection dct inte ALU, are ot ented neat, 1 Thecontoller has much ese strustre is tedious tranaat FS Into ates by hand, and in anew design, the contol the moe holy portion tohave bug and lest minute change, 9, Therefor, we wil pec thoeonizllar mor sbtrsty witha hardware ‘eacriptionanguoge and astomatcally generate wsngeyathess and place and rout ols a programmable gi array PLAY. ‘Fig 125.1 shows par ofthe design hierarchy fr the MIPS procettor. "The controller contains the controle. pla. and alee, which intra is bull from # brary of standard cells such as NANDs, NOR, and vere 3 The datapath i composed of Bit wordlces, each of which slo tylelly bul fom standard elle such s adders, register ile tits, ‘ltiplesers, and flip lope. Same of hace ols are reused in multiple laces. 4. ‘The design hierarchy does nat necesunily hav tobe identical in the loge, rei, and physical designs : Fig: EEL MIPS BERET, ‘Scanned wih CamScanner ~ TESTE wre a sor note on hardinare derision languages Introductionto Vigy Sone ee ae ered - - ae sally intendeg 1 ire eee ye {eae deer Pan, bt are Dw wed 0 STMECSE® Rate, Laren et Dt se ar Nt Sn patnorc mereypencitsee t HDL epecfis what wcll dos 4 Alogi simulatorsimalstes HDL code. Tt can report whether results si malion an ean dnplay waveforms t0 help debug Sccrepace. ‘Apert! sina to compiler or hardmare that ape 8 Aste atbary oftscaled standard cell to minimize area le eeting soe ining cotrlats. 1h Vere, each el is called mode. The inputs end outputs are ‘ero nach sina progr ad it width are piven fr buses, 1 Tnrnaleignale ws als be declared in away analogous to Incl rae {8 Theprocssrs deere biracial wxingstrcturalVerilogat the {oper vels ad behavioral Vergo tele el 8 Thdataathisopeiedstrctrallyin tert of wordslices, which are Intaradeatedbeharaly. ‘ee 127] Explain the concept of circuit design. a hie ag mien ‘Particular logic function in given circuit design, we limate the sepiconmstecrmerten ser Deere aes Seceemeeccea aterm tte rales iets secre {YUSLDesien ig 1: Ct a ad perinatal | ot towing cocci reat daring switiog 6) tai eakage reat Jel geet eran 4 ‘fanaverage currents applied the tine 'o eviteh between 0408 Vig 7a) ¢ Tt Hence, the delay iene wih the lon apace and dereses sith driv tren. One fhe gsi f cet dasign nt chose ‘Tani ida omest dle reqacrene. 5. Bncrgy isroquiredto charge and discharge the lod expacitance. This is called dynam power beeauseiteconsumed when the iets actively bitching. 6. The dynamic power consumed when a capacitor is charged and discharged ut frequency fis Pana Vf A213) ‘Bren when the gate isnot evitching, it draws some state power. Because ‘anOFF transistors eaky, mall amount ofcurrent ows between ‘power and ground, resulting ina static power dissipation of Prac Fae 90 a2 "FE, ] What do you understand by floor planning in physical Aesign? ‘Scanned wih CamScanner Inietctonto gy | a as sa organ The Doorplsn estimates yy, 1 ei tin in eis irene, | Peter ered > Fiat chp ares bigetadandtocstinae nag Peery as on a8 he logic is 4A npn sade prea some #8 BO cay Seether erent oorrlan will often suggest change ie (ang | 4 TeSoariectro wich crn changes te oorpan, sunigisestimaing the sie ofeach usiwithons | Seog cups detalles of ech shoe the ci organ fr the MIPS processor Snclaing Tunargitetnte mies ta 10 pte ti pet 3dr oe ihe mela | L_siticemindiemteepas | ‘wiring channlis act Toten ei bee the to VistDesign & secne partitioned into wordslices, The pad frame which are wired tothe pair on the chip package. sed for signals; the remainders are Vand GND. "The datapath i farther Includes 4000 pads ‘There are 29 pas ‘QHETHO,] enain tho standard cellbase design approsch forthe {implementation of VLSI circuits. ae] 2 3 ‘The standard cell bsed design one ofthe most prevalent fll custom sesimn styles which require development ofa full custom mask se, Different ogc ells are developed, characteriaed and stored ina standard call ibrary ‘A cpical library may contain afew honde ells including inverters, AND gates, NOR gates, complex AOT, OAL gates, latches, and fp. ‘The different gates can have standard size, double sue an quadruple sie so that designer can choose the proper sie a achieve high creat speed and layout density. Bach cells cheracterizedaccordngto several diferent characterization categories including, ‘Delay time versus load capacitance, (Cell data for place and route, Fault simulation model ‘Timing sirolation model Mask dat Circuit simulation model b a “ ‘To enable automated placement ofthe cells and routing of inter-cell ‘connections each ell layout is designed with a fined height, thet 8 ‘number of cells ean be abuited ide by side to form rows, ‘Thepower and ground rails typically rum parallel tothe upper and lower ‘boundaries ofthe cel thus, neighboring cells share a common power bus and a commen ground bus. ‘The input and outpot pin arelaeated on the upper and lower boundaries ofthe el. Fig. 1.29.1 shows a Noor plan forthe standard call bated design. Inside ‘the VO frame whichis reserved for VO celle, the chip area contains rows foreshumns of standard cells 7 10, Between cell rows are channels for dedicated inter cell routing, ‘Scanned wih CamScanner Intention to Vs oes ensure 1 Menten ced cena an tester = ert Sranucrtdee > eal a dingo nape wr’ eee tiara een SE aa (eo boar oO OE O oodotoo i900 pd an of ard te sign 12, Aftarehiplpe designis done sing standard calls from the liber, the se cheng tak eo place tho fia cls into rows ond {Srwonmect ten inayat net dein palin cc peed, chip ‘ro, and pore consumption 14, Many advance CAD tos for place and routs have nen developed ad sd tachi such goa ‘GEETAT] Write a short noteon fabrication, packaging and testing oFVESE chip, “Anewor 1 Once chip designs complete, tis taped ou for manufacturing. 2. Tapeout gest from the ld practice of writing aspecificatim of masks to magnetic tape; today, the descriptions ave te iptions are usually sent to the 3 Twocomman format descriptions ar the (Ci? ato Szeins re the Caltech fterchange Format (Ge (an ena ath Colina GDS Stream Format sear Sonat ‘pattern of chrome on a glass with an ‘vustDesian maene {5 Mali chips ro mnatitaed simultane ona igi alr, {gpially 160900 mm" = 12") im darter, Parcation eure any ‘poston, maskingand implant sep, ocased wafers are alice inte de chipm and package. “L._ The wirotonded package utes thin gold wien to connect the pad on the dete the lead fame in the cenlar cavity athe package. ‘8 Chips ae tered before being sld. Testers capable of handing high speed chips cont millions of dla oo eanyehips se bultin wtst ‘Matares to reduce the tstr tine Felted, ooo ‘Scanned wih CamScanner A. Canept Oatline Part 1B fone nd Medium Anawsr Type Questions Delay and Power, —_ ——___4 agence CONCEPT OUTLINE | PART ‘oa ie ine wins the apt ain V7 ‘he toltn af te erential panna te mina racemase oa ae he nok fecponse + Theat tha changes or discharges anode called te river tnd the gates and wires ning den ae called the lend ‘timing analyzer competes he areal men the atet {me at which esch nod na Mack o age wil wiih + Tho“dlck iste atforence between the required and arial Limes. Positive slark mane thet the cvuit meets tog [Negative slack means thatthe ciate enough, i _ uertionrAnewers “Long Answer Type and Medion Answer Type Questions B. Long and Medium Answer Type Questions. 560. ‘Quel. | Define the following: ween y Prepeeter degen SSS, i mene thane 5 Bae, Rnawer ‘We bina few dfinitions illustrated in Fig. 2.1.1. 1 Propagation delay time, «Maximum time from the input crossing [50% tothe output erossing 30. 2 Contamination delay time, ¢, = Minimum time from the input ‘rosting 50% tothe output eroating 50%. 3. Rise times ¢, = Time for a waveform trite from 209% ta 80% ofits steady-state Value 4 Fall time, ¢, = Time fora waveform to fll from 80% to 20 % of its steady state'valuc. 5. Bdge rate,ty=(¢,+ (2 ‘Scanned wih CamScanner i bear geen, erarae changes tho cut ts new valve {8 at moge 4! {When aniaput chang Py take thy me ie poset dl | Ye 10 1. Rise times ee alao sometimes called slope or edge rate. | 8 Propagation and contamination delay times are aleo called max-time | anid min-time respectively. | WaeRE, | Compute the step response (or transient response) of inverter X, driving another inverter X, at the | 2 Smt fom otis tn Aa eh iam the popu ly naught thls Sas ott epi rae Pepa te ay Teepe ae shown ng 22:10) ig 2216) sate orl check dagam nial ooo ese irae 4 ten cep h vltgs sep is opp A = 0 is OFF, P, is ON, and a ‘toward 0, mi 2 | 1% 08 ot a OF a | | i ‘VEStDesign s@one the rtetig vag Yann lpn csi Docitatae Soeseetaoet CaS, tay 1 Sanath ney height Tare Ste carseat pon ee nat Vp tho coureo iat, andthe drains at Vy- Thus, V,= Vag Abd Vj, Vy Initially, V,= Vig > W,,~ Vp, 00 iain saturation. 8 As pfallsbelow Vjq VN entors the linear region. Th diffe ‘equation governing V, i given by, 5 eM (222) Fe Meean-¥ 0. ivingantiatin he cores conan ¥ poe ot Peiaatee Vas oY, Thereafter, the diferental equation becomes eet rere canbe sop amare. sn sing Vo Yo the ramp reponse rept Ascuming Ve AY han ean write the eifferetil equations fur V, ineach phase Phase 1 Va" Veo . BM Foot “Hann 1223) ee eae mh 2 Mag tet Phase 3 a ‘Scanned wih CamScanner joiner | mute the nonlinear transistor LV and. re ay ae cin caactance Over ty ey an vr esl paitanee overt) ‘prteing range the B86 | ecveResitinety - ‘ a ets rani ab ich ri ith 1 Te Rea el btn atrae ar eehngntervafinteres, 7 1 aaa rasiteria defined tohave oe resistance R 8 Act invent ih sree Ise ‘Milivers tines as much current, 4 Aunipl0Strassarbas greater resistance, generally inthe range H2RCaR, becuse ofits lower moby. ‘According thelong chante mode, current dereases linearly with ‘Beelingth and hence esistancois proportional to L. 4 Moreover, he resistance oft transistors in series isthe sum o restances ofeach transistor. 7 1. However, if transistor is fllyvlosity-saturated, current and __ Rina inne fen ‘Tperesistanceof transistors in sei at Thesis ersinseriesis somewhat ower than the sum fee bea ors ranstrs have smaller Vand velocty-sturated “ | mateo ee poare r08 wants a ‘nate yun rears startin Gate and Diffusion Capacitance : 4 paves rata pas mn capacitance. | sitonetvdhiwemcete, | Diffusion capacitance depends ‘i a cf cere aera toma | 4 Inceasing {Eiyatingcanel nth increases gate capacitance proportionally oe ee TaaaT ora equates RC iat mel for OS a MOS ‘Resistors. Alv draw tho equivalent creat foram inverter, Fig. 24.1 shows equivalent RC creuit models for nMOS ‘and pMOS Fig. 2.4.1 ste with contacied effsion on both source and drain. 4, ‘The pMOS transistor has approximately tree the resstanss of Taide transitar because holes have lower mobility than electrons 4 The pM0S capacitors are shown with Vo as ther second termine Fane pe reels aually ted high, Fig 2.4.2shows the enyalent eet fara fanou-o-1 inverter with negligible wire capacitance ‘The unit inverters of Fig, 24.20) are composed from an 00K Tae rer af unt size anda pMOS transistor of tice unit width fe fachieve equal rise and fll resistance. 5 Fig. 2420) gives an equivalent circuit, showing the first invertor (driving the second inverter’s gate. 4. Ifthe ingot A rises, the nMOS transistor will be ON and the pMOS at ie 2.4) ustates his eave with the switehes removed 4, Tecopaitrs shorted between two constant suplice ae sles removed rosa they are not charged or discharged. The total capacitance on ‘the output Vis 6. Wissen iii aaa ‘Scanned wih CamScanner wut NAND gate with transistor width chosen to achieve effective rise and fall esistance equal to that ot ‘unit inverter (R). Annotate the gate with its gate and diffuaioe ‘capacitances, Assume al diffusion nodes are contacted, then sketeh ‘equivalent cireuits for the falling output transition and for tie ‘Worst-cate rising output transition. 1. Pig 2510) shows such gat, The thre AMOS transistors are a see 2 Beem punstene map th st can von

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