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CSE 181303

Roll No. of candidate

2019 ABtAD
B.Tech. 3rd Semester End-Term Examination
DIGITAL SYSTEMS

New Regulation (w.e.f 2017 2018)-

&
New Syllabus (w.e.f 2018 19)
Full Marks - 70
Time -Three hours

The figures in the margin indicate full marks

for the questions.
Answer questionm No. 1 and any four from the rest.
1 Answer any ten of the following questions
(10x 1 10)
aa Convert binary 1001 to Gray code.
o ASCII code is a 22=n3bit code.
(c) What do you mean by active-LOW input gate?
(d) The interconnection of gates to perform a
variety of logical operations is called
A®R
(e) De Morgans theorem states that (Choose thec
right alternative)
) A+B A.B and AB = A+B
Gi) A+B =A+B and AB =A.B
(ii) A+B A+B and AB= A.B
(iv) A+B= A.B and AB =A.B

[Turn over
 The simplified fornm of Boolean expression (k) How many states 6 bit
a ripple counter can
(X+Y+XY)X+Z) s (Choose the right alternative)

TME/S
have? (Cho0se the right alternative)
) X+Y+Z i) 6
i) XY+ YZ (ii) 12 AD

ii) X+YZ

(iv) XZ+Y
PACS (i) 32
iv) 64
() The number of cells in a 6 variable K map is
(Choose the right alternative) Convert 2598.67510 to hex.
i)
i)
6
12
M L 2. (a) State and prove De Morgan's theorems, Reduce
the expression: (3+3-6)
n ) 36 f [B+C.(AB +AC)
iv) 64 b) Expand A+B to minterms and
(h) Compare a decoder with a demultiplexer. maxterms.

G) A combinational logic circuit which is used to Ci Minimize the following expression using K.
send data coming from a single source to two or Map
more separate destination is called (Choose the
right alternative) F(A, B,C.D) = Em(1,4,7,10,13) +Zd(5,14,15)
H
() a decoder
i ) Prove that: AB + AC+ ABCAB + C) = 1.*
(i) an encoder
3. (a) What is combinational circuit? Design a full
ii) a multiplexer adder using half adders. What is a ripple carry
iv) a demultiplexer adder? (2+3+1-6)
The transparent latch is (Choose the right (b) Implement the following logic function using
alternative) 8x 1 MUX: (5)
() an SR flip flop 2
F(A,B,C, D) = Zm(1,3,4,11,12,13,14,15)
(ii) a D flip flop k () Design a full adder using a decoder. (4)
(ii) a Tflip flop
Or
(iv) a JK flip flop
i ) Design a 2-bit magnitude comparator. (4)

CSE 181303 2 CSE 181303 3 Turn over

=10
 What are sequential circuits? Differentiatee
) between synchronous sequential circuits and
asynchronous sequential circuits. (2+3-5)

8)
L (i) Draw the circuit diagram of a positive
edge triggered JK flip flop and explain its
operation with the help of a truth
How is race around condition
table..
eliminated? (6+2)
Or
i ) Convert an SR flip flop to JK flip flop. (8)
(c) Discuss the applications of flip flops. (2)
5. (a) With the help of a neat diagram, explain the
working of a R-2R ladder network type A
DAC.
6- bit DAC has a step size of 50 mV. Determine
the full scale output voltage and percentage
resolution. (5+3-8)
Design a Mod-6 Asynchronous Counter using T
flip flop. (7)
6. Write short notes on: (any three) (3x5 15)
(a) Synchronous counters.
(b) Parallel-in, Serial-out shift registers.

(c) Programmable Array Logic (PAL).

(d) Ring Counters.

(e) Priority Encoders.

( Latches

CSE 181303 4