PSDC ENGINEERING DIPLOMA ASSESSMENT: TUTORIAL 2

1. Implement a 2:4 decoder with AND and NOT gates

2. Implement the function as below using

i. 8:1 multiplexer
ii. 4:1 multiplexer and no other gates
iii. 2:1 multiplexer, two AND gate, and inverter

3. Implement a full adder with carry output, C using

i. 4:1 multiplexer
ii. 8:1 multiplexer

4. Design a 3-to-8 decoder. Assume inputs A2, A1, A0 are active high and outputs
O7, O6…,O0 are active low.

5. Design 1-to-4 de-multiplexer using a 2-to-4 decoder with an enable.

Hint: When using a decoder as a de-multiplexer, use the enable input as the data input
and use the decoder inputs as select lines.

6. Use four 8 to 1 MUX and THREE 2 to 1 MUX to implement a 32 to 1 MUX.

7. a). Alyssa P. Hacker needs to implement the function Y = AB’+B’ C’ + A’BC to finish
her senior project, but when she looks in her lab kit, the only part she has left is an 8:1
multiplexer. How does she implement the function?

b). Alyssa turns on her circuit one more time before the final presentation and blows up
the 8:1 multiplexer. (She accidently powered it with 20 V instead of 5 V after not
sleeping all night.) She begs her friends for spare parts and they give her a 4:1
multiplexer and an inverter. Can she build her circuit with only these parts?