Chapter Digital Meters 2.1 INTRODUCTION Analog meters use an electromechanical movement of a pointer over a calibrated scale to display the value of the quantity (voltage, current, resistance, etc.) being measured by the meter. Digital meters, on the other hand, use an alphanumeric or numeric LED (Light Emitting Diode) display or LCD (Liquid Crystal Display) for showing the reading of the measured quantity. Further, the internal circuitry used in digital meters is different from that of analog meters. Digital meters normally use analog-to-digital (A/D) converters (or ADC) and other digital processing circuits. Figure 2.1 shows the block diagram of a digital multimeter. Digital Digital processing [*] display Ac, t ee mine : up Se rons atemtor | ool converter 2p, ohm ohm © aS) Amp = Inps converter ac |] ac Precision Low) o—| Figure 2.1. Block diagram of a digital multimeter ssTTT inion) ‘The basic input blocks are same as used in an electronic analog multimeter. The attenuators are used for lowering (attenuating) the input voltage. Annexure A gives more details on attenuators. DC input voltage is first attenuated, if required, and then interfaced with an A/D converter which converts it into digital form. This digital signal is then processed and displayed, AC input voltage is also first attenuated, if required, and then fed to an AC converter which rectifies it. The rectified output is then interfaced with an A/D converter which converts it into digital form. This digital signal is then displayed after processing, The current is converted to a voltage by passing it through precision shunt resistors. The voltage is then processed and displayed in the units of current For ohms measurement, an ohms converter is used. As explained for the electronic analog ohmmeter, the converter includes a constant current source which is made to flow through the unknown resistor. The voltage so developed is then measured and displayed in the units of resistance. We observe that the A/D converter plays an important role in the digital meters. These converters also constitute the core of other instruments like oscilloscopes, signal analyzers, etc. Many modern meters and other digital instruments use microprocessors for processing. digital signals and providing other additional features. In this chapter we will study basics of AID converters and then describe some commonly used architectures. Some of the A/D converters use built-in digital-to-analog (D/A) converters. for converting digital signals analog signals, Therefore, first let us leam about the different types of converters. 2.2 DIGITAL-TO-ANALOG CONVERTER Figure 2.2 illustrates the basic function of a D/A converter. Reference voltage, V, + =] wa Binary input, By aes Analog output, Va, Figure 2.2. Basie funetion of a D/A converter. Bay is defined to be an N-bit digital word such that Buy = BD + D2? +. + DY” where b, is a binary digit and equals a | or a 0. We also define b, to be the most significant bit (MSB) and by the least significant bit (LSB). The analog output signal, Voy is related to the digital signal, Bi., through an analog voltage reference, V,. The relationship between these three signals is given byTien Tatraments el Fsiramenaton TciooTogy Veee = Vz (O2! + 52? +... + BD) We can define Vi sq 0 be the voltage change when one LSB changes, or mathematically, y, Vise Example 2.1 An 8-bit D/A converter has V, = 5 V. What is the output voltage when Bj, = 10110100? Find alsa View Solution Using the previous equations, we get Big = 21 4 23 4 244 2% = 0.703125 Vout = Ve Biq = 5 X 0.703125 = 3.516 V Bama Visu #35 = 55 = 19.5 mv We see that precision depends upon the number of bits N. 2.2.1 Transfer Characteristics Figure 2.3 shows the transfer characteristics of an ideal 3-bit D/A converter, 10 0.87 0.750 0.825 ‘Analog output voltage, Vous 0.000 000 0b) O10 oly 4004) 10 a Digital input word Figure 2.3. Transfer characteristics of an ideal 3-bit D/A converter.TTT inne) Note that the maximum value of Vjq is not V, but rather ¥; (I~ 2-%), of equivalently Ve Visw: In practical circuits, the transfer characteristics are not linear and not monotonic. These are explained in the section on performance parameters of D/A converters. 2.2.2 D/A Conversion Techniques Various architectures are used to realize a D/A converter, The most commonly used techniques are discussed in the following sections. Weighted-resistor D/A converter Figure 2.4 illustrates a 4-bit weighted resistor D/A converter which has a reference voltage source, a set of binary-weighted resistors, an opamp and a set of switches. Each switch has its own binary bit of the digital input word which controls it. The switch is closed when the binary bit is a 1 and open when the binary bit is a 0. The switches are realized using transistors. % Pe i) Tw Lww fa n> Summing a WW ~~ terminal “ 168, wa When the binary bit (b) is a 1, the current flows through the resistor in series into the summing terminal. When the currents from the network of resistors are summed in the amplifier, the total current, J; is given by Lah+th+ht+h=h The same current flows through the feedback resistor R,. The output voltage is given by the following equation: naw (et Be Be) Vou = Rel 2 * aR * BR * T6R R, aM (b,27 + by? +o. + by2™)Dict Tareas sd Trarmerntion Teco We sce that the output voltage is proportional to the sum of the binary weights. Further, the values of the input resistors are inversely proportional to the input binary weights. The lowest value resistor (R) corresponds to the MSB and the highest-value (8R) to the LSB. ‘The disadvantage of the weighted-resistor D/A converter is the large number of resistor values that it has. For instance, if we take an 8-bit converter, the 8 resistors will range from R to 128R in binary weighted steps. Also, this type of D/A converter is very difficult to mass produce due to the range of resistors required, where the tolerance is less than 0.5%, 10 accurately convert the input. Further, the lowest value resistor R affects the MSB and must hhave the highest precision. Also, it draws maximum current from the reference voltage source. R-2R ladder D/A converter Unlike the weighted-resistor D/A converter, the R-2R ladder D/A converter uses only two resistor values. Figure 2.5 shows the basic circuit of 4-bit R-2R ladder D/A converter. i> Figure 2.5. A 4-bit R-2R ladder D/A converter. Each switch has its own binary bit of the digital input word which controls it. The switch is connected to V, when the binary bit is a 1 and connected to ground when the binary bit is a 0. ‘To understand how the circuit operates, consider the first bit (LSB) of the R-2R network. Depending on the state of the switch, this bit forms a voltage divider developing 0 x V, or 1/2 x V,. In either case, the Thevenin resistance is the same, i. R. The Thevenin equivalent to the left of point A is shown in the Figure 2.6(b). Similarly, if we find the Thevenin equivalent to the left of point B, we find that the Thevenin equivalent is as shown in Figure 2.7(b).. We therefore see that the Thevenin equivalent of the circuit to the left of point D would be as shown in Figure 2.8 From the circuit of Figure 2.5, the current J; is given by LBV, + DV, )12 + (bY, 14 + O4Y_ 182 Raie) A AV) avi) @ ) Figure 2.6 Thevenin equivalent to the lft of point A of Figure 2. ey stv) Ly, + v.22 Figure 2.7 Thevenin equivalent to the left of point B of Figure 25. aN, + DaV2) + OsVIS) + AVR) Figure 2.8 Thevenin equivalent to the left of point D of Figure 25.Dini Taare snd Trsramerntion Tecinology Therefore, the output voltage is by be You = By = RV (ae aie Ry ieee -) = Fey, 24 + 622 + + by? Fe Ve 2! + bye by) Thus, the K-2K ladder can be used to obtain binary weighted voltages or currents while using only a single-sized resistor. (The resistors of size 2K are made of two resistors of size R, to improve matching properties.) As a result, this R-2R approach usually gives both smaller size and better accuracy than the binary-weighted resistor approach. Further, the resistors can be lower in value giving high speed operation. Inverted R-2R ladder D/A converter In this configuration, the positions of R and 2K resistors are interchanged. The ladder currents are independent of the switch position. This is a popular configuration for CMOS technology. Switched-capacitor D/A converter Instead of using resistors in binary weighted-tesistor and R-2K ladder networks, capacitors are used, ie. R is replaced by C. Therefore these networks become binary weighted capacitor and C-2C ladder networks. These converters have low-power dissipation with CMOS technology. CMOS opamps and capacitors are fabricated on the same chip. However, these converters suffer from more dynamic switching losses. Internal structure of commercial D/A converters In addition to the resistor network, commercial D/A converters include additional digital and analog circuitry for temporarily storing the digital input and for shifting the voltage levels to get the desired output voltage (see Figure 2.9). J] Dieta input. 2s Input gates T N-bit register TDW ies Level amplifiers IL tines Resistor notwork ¥ Analog ouput, Vou Figure 29 Block dagram of commercial D/A converter.@ 2.2.3 Digital Input Modes of Operation There are different modes (configurations) that can be configured to operate a D/A converter, eg. Unipolar Straight Binary (USB), Bipolar Offset Binary (BOB), or Binary Two's Complement (BTC). Table 2.1 shows the meaning of each mode of operation. Depending on the design specifications, one of these three modes may be more useful than the others. ‘Table 2.1 Modes of operation Digital input ‘Analog ouput MSB LSB Unipolar straight Bipolar offset Binary wo's inary (USB) binary BOB) complement (BTC) TUT “Pull sale + Full scale = 1 LSB 1090000000000, + 17 Fall sale Zero = Full sale ont (+ 17 Fall scale ~ LSB) = 1 LSB + Full sale 1000000000000 Zero = Fal scale Zero 2.2.4 Performance Characteristics of D/A Converters Resolution It refers to the smallest subdivision (step-size) of the full-scale output that is possible, given the number of bits in the input word. This is equivalent to the weight of one LSB which is defined as v, Vise where V, is the reference (full scale voltage) and NV is the number of bits in the input word. Resolution can also be defined as the number of bits that are converted. Accuracy Accuracy tells us how close is the output to the ideal converted output. That is, it gives the error in the analog output from the theoretical value for a given digital input. It is generally specified as a percentage of the full scale output. Ideally, the accuracy should be no worse than + (1/2) LSB. It also includes the offset and gain errors (see Figure 2.10). Offset error The offset error is the AV from OV that results when a digital code is entered that is supposed to produce 0 V. Related to the offset error is the offset error temperature coefficient, which is the change in offset over temperature. This is usually specified in ppm/°C. Offset error is critical in de applications. For this reason, a buffer op-amp that does not contribute to the problem must be selected. The opamp's own offset voltage should be much less than that of the converter. In ac applications, the offset error is not important and can be ignored.MD itn Tras cd Traramernnion Tecogy Gain error 0875 0.750 0.625 0.500 0.305 Z4nalog output voltage, Vax 0.250 0.125 Offset error 00 00) 010 Oly 100 4D) 1101 Digital input word Figure 2.10 Gain and offset errors Gain error The gain of the D/A converter may be greater than or less than the gain needed to produce the desired full-scale analog voltage. The gain error is the difference in slope between the ideal D/A output gain and the actual gain. Related to the gain error is the gain error temperature coefficient, which is the change in gain over temperature. The gain error can be critical in both ac and de applications. Example 2.2 Given a 3-bit DAC with a 1 V full scale voltage and accuracy + 0.2%, find its resolution and accuracy in terms of voltage. Solution Resolution = +. = 0,125 V 3 Accuracy = (+ 0.2%) (1 V) = +2 mV These parameters can be graphically represented as in Figure 2.11 The offset and gain errors depicted in Figure 2.10 still keep the transfer characteristics linear. In practice, the characteristics, however, may not be linear and may not always increase (be monotonic) with the increase in the input (see Figure 2.12).oo v= 10V ‘Accuracy (Error) = $2mV Analog ouput voltage, Vou 3 000 por atn oly a) tT 10 att Digital input word Figure 2.11 Graphical representation of accuracy and resolution. eal Lov 0875 0.750 0.4625 0.500 037s 0.250 oust 0.000 ke » 000 901 010 O11 100 101 110 AT Digital input word oy Analog ourput vollage, Vays 0.875 0.750 0625 0.500 0375 0.250 0.128 0,000 Le > 000-001 O10 O11 100 101 110 111 Digital input word © Figure 2.12 Transfer characteristics: (a) Nonlinearity and (b) non-monotonocty Analog output voltage, VacDini Taare snd Trsramerntion Tecinology Besides nonlinearity and non-monotonocity, the following types of error values are also given by the manufacture Differential nonlinearity (DNL) error The differential nonlinearity error shown in Figure 2.13 (sometimes seen as simply differential linearity) is the difference between an actual stop height and the ideal value of | LSB. Therefore if the step height is exactly | LSB, then the differential nonlinearity error is zero. If 0.875 0.750 0.625 DNL LSB) 0.00 0375 Analog outpat voltage, Vag 0.250 0.125 0.000 000 01 alo Olt 100 HOY KOHL Digital input word He DNL(1/4 LSB) Figure 243 Differential nonlinearity err the DNL exceeds | LSB, there is a possibility that the converter would become non- ‘monotonic. This means that the magnitude of the output gets smaller for an increase in the magnitude of the input. We can define DNL error as follows: DNL error = [Vou (1+ 1) ~ Vout ~ Vise Integral nonlinearity (INL) error The integral nonlinearity error shown in Figure 2.14 (sometimes seen as simply lincarity error) is the deviation of the values on the actual transfer function from a straight line. This straight Tine can be either a best straight line which is drawn so as to minimize these deviations or it can be a line drawn between the end points of the transfer function once the gain and offset errors have been nullified. The second method is called end-point linearity and hhas the usual definition adopted since it can be verified more directly. ‘The deviations arc measured at each step. The name integral nonlinearity derives from the fact that the summation of the differential nonlinearities from the bottom up to a particular step, determines the value of the integral nonlinearity at that step. Thus, INL error = E [Voy (+ 1) ~ Vou (D1 for 0 up to the given inputDistal Nes) ED + Weal End-point Ce Tineaity oe 08: } Ar step 100 (+1/2 LSB) Analog ouput veltage, V, 0.125 F< Acstep 001 G14 LSB) 0.000 0001 O10 O11 100101110 TD Digital input word Figure 2.14 Integral nonlinearity error. Both the INL and DNL errors affect ac applications in the forms of distortion and spectral harmonics (spurs). In de applications, they result m an error in the de output voltage. Settling time This is the time it takes a D/A converter to settle within an error band around its final value when a change occurs in the digital input. Dynamic range This is defined as the number of usable values. For example, a 4-bit D/A converter has a aynamic range of 10 values of 20 logig!6 = 24 dis, Sometimes It 1s expressed as © x number of bits of digital input. Power supply rejection ratio The power supply rejection ratio is sometimes called the power supply sensitivity. It 1s the ability of the converter to reject ripple and noise present on its power inputs. DC applications may not be adversely affected. Poor power supply rejection can cause spurs and harmonic distortion in ac applications, as external frequency components leak into the output and modulate with it ‘The power supply rejection ratio is defined as the ratio of a per cent of full-scale reading change in the output to a per cent of change in either positive, negative or digital supply voltage about the nominal power supply voltages.o Drift Many converter parameters like gain and various types of errors change with temperature. This phenomenon is called drift and is specified as ppm of FSR/°C with reference to 25°C temperature. 2.3 ANALOG-TO-DIGITAL CONVERTER Figure 2.15 represents the basic function of an A/D converter. Reference voltage Vy + Analog input, Vi | A/D converter Binary output, By Figure 2.15 Basie function of an A/D converter, The binary output, Bou is the N-bit digital output word while Vi, and V, are the analog input and reference signals, respectively. For an A/D converter the following equation relates these signals: Ve (B21 + 6:27 +... + BIN) = Vig t Vy where 6; is a binary digit and equals @ | or a 0. We also define 6 t0 be the most significant bit (MSB) and by the least significant bit (LSB). Also, V, is given by the following expression (4) Vise $Y (3) Vise 2.3.1 Transfer Characteristics The process of converting analog to digital signal is called quantization. Note that there is now a range of input values that produce the same digital output word. Some information is lost and some distortion is introduced into the signal during the conversion process. This signal ambiguity produces what is known as quantization erroriquantization noise. See Figure 2.16. In the case of a D/A converter this effect is not present since the output signals are well-defined. For the ideal staircase transfer function of an A/D converter [Figure 2.16(a)], the error between the actual input and its digital form has a uniform probability density function if the input signal is assumed to be random, It can vary in the range +1/2 LSB or +q/2 where q is the width of one step. where Vise = V2".aie) m1 10; 101 100) 2 ou o10 001 lam +12 LSB 009 Lt po 0.000 0.125 0.250 0.375 0.500 0.625 0.350 0.875, Analog output voltage, Vi, @ ‘Quantization error 412 LSB Inherent quantization Jecror £1/2 LSB or 29 Figure 2.16 Transfer charactristies of an ideal 3-bit A/D converter. The yuaniced sigual yLe] car be seprescuted by a linear function xf] wid an enor en}, that is, yln] = Gxln] + etn] The gain G is the slope of the straight line passing through the center of the quantization, characteris To simplify the analysis of noise from quantizer, the following assumptions about the noise process and its statistics are traditionally made: The error sequence ¢{n] is a sample sequence of a stationary random process. 2. The error sequence is uncorrelated with the sequence x[n] 3. The random variables of the error process are uncorrelated, ie. the error is a white- noise process. 4, The probability distribution of the error process is uniform over the range of quantization error.RD itn Tatras cd Traramernnion Tecogy For a zero mean e[n}, its variance G2 or eng (mean square quantization error) is, When a quantized signal is sampled at frequency f, all ofits power folds into the frequency band 0 < f< fi Then, ifthe quantization noise is white, the spectral density of the sampled noise is given by E The noise power is flat and the level of the noise power spectral density is given by the equation ED= VG ia Consider a sine wave input F(#) of amplitude A so that FQ) = A sin or which has a mean square value of F2(), where vt 2g = Lf atsin? FO = am! onde and which is the signal power Therefore, the signal to noise ratio, SNR, is given by SNR (4B) = vow (£2) 12 But 2A__A isp = 24 4 amie Substituting for q gives A so an) = 10 el Aa x2" (6.02n + 1,76) dB This gives the ideal value for an n-bit converter and shows that each extra | bit of resolution provides approximately 6 dB improvement in the SNR. In practice, the errors introduce nonlinearities that lead to a reduction of this value. The limit of a 1/2 LSB differential linearity error is a missing code condition which is equivalent to a reduction of | bit of resolution and hence a reduction of 6 dB in the SNR. This then gives a worst case value of SNR for an n-bit converter with 1/2 LSB linearity error asaie) SNR (worst case) = 6.02n + 1,76 ~ 6 = (6.02n ~ 4.24) 4B This establishes the boundary conditions for the choice of the resolution of the converter based upon a desired level of SNR. 2.3.2 A/D Conversion Techniques Many architectures are available to realize an A/D converter. Some of these techniques are discussed below. Single slope (ramp) A/D converter Figure 2.17 shows the block diagram of this type of converter. It uses a comparison method in which the input is compared with the voltage generated by the ramp generator. The ramp gencrator is realized using opamp based integrator (see Figure 2.19). The counter counts the pulses and the latches store temporarily the output bits of the counter. Clock Analog input PS ie — Z i= Counter j + Comparator eal Ramp Reset generator Control logic Enabl Latches Figure 2.17 Block diagram of a single slope (ramp) A/D converter. At the beginning of a conversion cycle, the counter is reset and the ramp generator output is 0 V. At this point, the analog input is greater than the reference voltage and so the output of the comparator goes HIGH. This enables the clock to the counter and starts the ramp generator. Once the ramp voltage reaches the analog input, the ramp is reset and the binary count is stored in the latches by the control logic. ‘Single slope A/D converters are appropriate for very high accuracy of high-resolution (24-bit) measurements whete the input signal bandwidth is relatively low. Besides the accuracy, these types of converters offer a low-cost alternative to others such as the successive-approximation approach. Typical applications of these converters are digital voltmeters, weighing scales, and process control. They are also found in battery-powered instrumentation due to their very low power consumption.Diaconis Treas Frstrmenaon Tecnology ‘The accuracy of this converter depends on the precision of the ramp generator. In turn, the procision of the ramp generator depends on the RC time constant of its integrator which varies with time and temperature. Any noise present at the comparator input while the ramp is near the threshold crossing can cause errors. So, this type of converter is more susceptible to noise. Digital ramp A/D converter As shown in Figure 2.18, this converter uses a binary counter as the register. A START pulse resets the counter and disables the AND gate. With all Qs at its input, the D/A converter’s output is Va, = 0 volts. Since V,, < Vis the opamp output is HIGH. When the START pulse Analog input PX cock Vva——_+ Lt PL Coenpasetot sat ova convener Counter ' Vox Clock Digital ouput Figure 2.18 Block diagram of a digital ramp A/D converter. returns LOW, the AND gate is enabled. As the counter advances, the D/A converter output, Vas increases one step at a time. This continues until V,, reaches a step that just exceeds Vin by about Vp. The opamp output is then LOW disabling the AND gate. The A/D conversion is now complete and the contents of the counter are the digital representation of Vjq, The digital data 1s lost at the next START pulse. Example 2.3 Given the following values for a digital ramp A/D converter '* Clock frequency = 100 kHz © Vp= 100 pv ‘© The D/A converter’s Vig = 10.24 V and has a 10-bit input determine (a) the digital equivalent representation for Vi, = 3.728 V, (b) the resolution of the AID converter, and (c) the conversion time requited by this digital ramp A/D converter. Solution (a) The D/A converter has a 10-bit input and a 10,24 full-scale voltage output. So the possible steps are 2'° = 1024 and the step size is 10.24 V/1024 = 10 mV. Thus, Vq, increases in stepsaie) of 10 mV as the counter counts up from 0, Since Vj, = 3.728 V and Vy = 0.1 mV, Ve, must reach 3.7281 V or more before the comparator switches LOW. This requires 3.7281V/10 mV which equals 372.81 or 373 steps. At the end of the conversion, then the counter holds the binary equivalent of 373, which is 0101110101. This is the desired digital equivalent of Viq = 3.728 V as produced by this A/D converter. (b) The resolution of this A/D converter is equal to the step size of the D/A converter which is 10 mV. In per cent, it is (1/1024) x 100% = 0.1% (©) 373 steps are required to complete the conversion. Thus 373 clock pulses occurred at the rate of 1 per 10 us giving a total conversion time of 3730 ts or 3.730 ms. Dual slope A/D converter The dual slope A/D converter operates on the principle of integrating the unknown input and then comparing the integration times with a reference cycle. The basic way is to use wo (dual) slopes. Figure 2.19 shows the block diagram of this converter. Switch contol Comparator >| control logic fe Clock Me L + ; Clock Overfiow Integrator Counter win TTTTTT © Digital ouput vs Yo Slope = Vad RC o alee Figure 2.19 (a) Block diagram of dual slope A/D converter and (b) integrator outputBD iit Tatras cd Traramernnion Tecogy The counter is set to zero, and the analog input, —Vig, is connected to the integrator. The counter begins to increment and the output voltage from the integrator is given by Att, the counter overflows, then the Overflow signal to the logic goes HIGH. At this point the integrator output is dt (at. a rate of (VRC) V/s) Vy= (assuming Vig = 0 at r= 0) RC The integrator is then connected to the reference voltage, Vig, and the counter is reset. At f,, the counter begins counting and the integrator output, ‘given by vox] Yebdr tate of CUg/ RO) Vip Atty + & the integrator output has changed by Veet ta We Re At this time, the integrator voltage is zero, the comparator output changes and the counter stops. Since the integrator output voltage is 0 V, we can equate the two values to give Maat RC RC We Qn) Since the counter overtiows in the time f, we know that the counter counts to its maximum, value 2" and n= 2 tax where fcxx is the time period of the clock. Ta @ dhe counter will count t a value 1, thee ty = Mer Hence from Eq. (2.1) Veer Meu _ Via 2¥ teu. RC RC and V2” V, Thus 1 is proportional to the input voltage (rather the ratio of input and reference voltages) and the maximum count NV but is independent of R and C. Hence, the range of counter and reading the counter at 1, + #2 gives the desired digital output. The comparator determines when the integrator signal would reach zero. The control logic performs the necessary operations to control the switch depending upon the counteraie) status and the comparator output. When the comparator switches, the counter is reset for the next integrate eyele and conversion. Since this type of converter actually performs integration on the input signal, it nulifies the effects of noise (the integration process averages out the noise), provided the noise frequencies, figies are such that 1 where 1, is the integration period. Thus the choice of r, determines what signals can be rejected, for example, the interference from the power supply mains. Conversion time is determined by teow = ON + mytcux + fo where tp is the time to zero the integrator. ‘The main benefits of this converter are the increased range, the increased accuracy and resolution, and the increased speed. Successive approximation A/D converter The conversion technique based on a Successive Approximation Register (SAR), also known, as bit-weighting conversion, employs a comparator to weigh the applied input voltage against the output of an N-bit D/A converter (see Figure 2.20). Using the D/A converter output as a reference, this process approaches the final result as a sum of N weighting steps, in which each step is a single-bit conversion, Conversion time is directly proportional to conversion accuracy. This converter is faster than the dual slope A/D converter. Analog input, Vis ‘Control Togie J anit (CLU) Comparator 7 roc START Reset MsB DIA converter approximation Digital oupal_weiser SAR) Figure 2.20 Successive approximation A/D converter. The operation of the circuit is as follows: A START pulse clears all the bits, disables the Control Logic Unit (CLU) and sets End Of Conversion (EOC) output to 0. A/D conversion begins with the MSB = 1(1/2 of full-scale). The digital output of the register is converted to analog signal, V,,, and compared with the analog input. If V,, > Vig. then the last set bit is cleared back to 0 and the next lower significant bit to set to aL. This process is repeated till all the bits have been checked. After all the bits have been checked. the EOC output isTnsiramenis andl Tustramenta © Cikam made a 1. The A/D conversion is now complete and the contents of the register are the digital representation of Viy, The digital data is lost at the next START pulse unless stored in some sort of memory device or location. The conversion is complete when all N bits have been compared. Thus, the conversion time is given by Nifeyx. where ferx is the clock frequency. Figure 2.21 shows the bit testing sequence for a 3-bit converter. mn Technology XXX 060 = abr oo ou 100 Tor 110 th Figure 2.21 Bit testing sequence for a 3-bit converter. In the above discussion we assumed that the analog input remains constant. If the input , during conversion time, the result will be wrong. Figure 2.22 shows the response of a 4-bit converter for a variable analog input. The final code depends upon the value of the input at the start of the conversion when the input is sampled. Therefore, we need a sample and hold circuit to meet this requirement. oir ool 0101 iio 11011101 1101101 Figure 2.22 d-hit snecessive approximation A/D converter sponse for s variable analog inpa ie 0D) Successive approximation converters are more often used at lower speeds in higher- resolution applications. These converters are also well-suited for applications that have non- periodic inputs, since conversions can be started at will. This feature makes the architecture ideal for converting a series of time-independent signals. Aliasing The rate at which the samples of the input are taken is called sampling rate or sampling frequency. If the converter is being used to measure slow-changing signals, it could probably have a very slow sample frequency and still perform adequately. Conversely, if it is being used at high frequencies, the converter needs to be considerably faster. Consider Figure 2.23 where analog input aud digital ouaput ate plowed versus sanupting time for a successive approximation A/D converter. Since the signal is now varying slowly the sample rate is more than adequate to capture the general trend of the signal. Now consider the signal shown in Figure 2.24, where the input changes fast, but is being sampled at the same time intervals as in Figure 2.23. Sampling instants YN Anal input Spree t+- Time Digital output CHA fe Figure 2.23 Analog input and digi Sampling instants a Analog input LS Time—> Digital ouput | 4 Time —> Figure 2.24 Sampling of fast varying signalBD ict Trane cd Traramerntion Teco Note also how in the latter portions of the analog signal, the digital output fails to reproduce the true shape. Even in the first section of the analog waveform, the digital reproduction deviates substantially from the true shape of the wave. This is because when the sample period is too long, substantial details of the analog signal are missed out. Therefore, the sample interval should be small enough to capture essential changes in the analog waveform, The sampling frequency is related to Nyquist frequency according to which it must be equal to twice the maximum frequency of the input signal. For example, if an A/D converter circuit has a sample frequency of 5 kHz, the highestrequency waveform it can successfully resolve is the Nyquist frequency of 2.5 kHz, If an A/D converter is subjected to an analog input signal whose frequency exceeds the Nyquist frequency for that A/D converter, the converter will output a digitized signal of falsely low frequency. This phenomenon is known as aliasing (see Figure 2.25), \™ Lb HH TH = Period Digital outpat — L{ Le fk Je— Period —of co) effect on the output wave shape Figure 2.25. Aliasing and i We notice from Figure 2.25(b) that the period of the output waveform is much longer (Slower) than that of the input wave form, and how the two wave shapes are not at all similar. It should be understood that the Nyquist frequency is an absolute maximum frequency limit for an A/D converter, and does not represent the highest practical frequency measurable. To be safe, we should not expect an A/D converter to successfully resolve any frequency greater than one-fifth to one-tenth of its sample frequency.a ie 0D) A practical means of preventing aliasing is to place a low-pass filter (anti-alias filter) before the input of the A/D converter, to block any signal frequencies higher than the practical limit. This way, the A/D converter circuitry is prevented from getting any higher frequencies and thus will not try to digitize them. It is generally considered better that such frequencies go unconverted than to have them be aliased and appear in the output as false signals. ‘The commonly used filters are Butterworth filter, Chebyshev filter, Inverse Chebyshev filter, Cauer filter and Bessol-Thomson filter. Each filter has its own advantages and disadvantages. We will not discuss the details of these filters here. Undersampling FFor high frequency input, we noad a high sampling frequency. But many A/D converters may not be able to operate at this high frequency. Undersampling is a powerful tool that can be used effectively in selected applications, It allows an A/D converter to behave like a mixer in that it can take a high-frequency signal and create an image that is lower in frequency. This method effectively uses the A/D converter as a downconverter by shifting higher bandwidth signals into the A/D converter's desired band of interest. Another key advantage is that it allows us to use an A/D converter with a sample rate that is lower than Nyquist causing aliasing, which usually has significant cost advantages. With proper filtering of the input signal and proper frequency selection, the aliased components at lower frequency are selected and converted. ‘One drawback of undersampling is that unwanted signals can appear in the desired band of interest and we cannot differentiate them from the desired signal, Also, when uundersampling, the frequency range at the A/D converter input is often very wide. Sample and hold circuits In most A/D converters, it is difficult to ascertain when the digital output matched the analog input signal, unless it was static. If the conversion is required at a specific instance in time, then a sample and hold circuit is used to capture the signal value and hold it whilst the conversion takes place. If the analog input signal changes, then it will not affect the result, ‘The basic cample and hold cirouit comprises a owiteh, §, and a capacitor, C, a Figure 2.26. Feelin Contol signal Figure 2.26 Basie structure of a sample and hold circuit. When the switch is closed, the voltage across the capacitor, Vc, follows ot tracks the applied voltage, Vj,. When the switch is opened, the capacitor retains the analog voltage applied at that instant of time.BD in Trans cd Trarmerntion Teciogy Practically, the signal is buffered, as illustrated in Figure 2.27, to minimize the effects of loading. Also, a field effect transistor (FET) is used as the switeh sinee it operates like an ideal switch, with an ‘on’ resistance <100 @ and an ‘off” resistance > 10° Q with zero offset voltage. Control signal Figure 2.27 A practical sample and hold circuit ‘The “hold” time depends upon the characteristics of the capacitor, since its charge leaks over time. As a result the voltage across the capacitor, Vc, decays or droops. Now, we move on to the response parameters of sample and hold circuits (see Figure 2.28). Acquisition time Tracking Tracking Input signal Aperture time Sample Hold Sample Figure 2.28 Response parameters of sample and hold circuits Response parameters Aperture time. Time required for the switch to open. This is also called aperture uuncertainity. Acquisition time. Time it takes the output of the sample and hold circuit to ‘track’ the input signal within a specified accuracy. It depends upon the maximum charging current that the input amplifier can supply to the capacitor plus the switch operation time.Droop rate. The rate of change of the output voltage when the circuit is in the “hold” mode, and is a function of the leakage or droop current, ig, and the capacitance, C. Wo _ iy ac Example 2.4 ‘The maximum charging current of the input opamp in a sample and hold circuit is 50 mA and the droop current is 100 pA. What is the expected droop rate if the acquisition time for a 3 V step is 6 1s? Soluston The value of C is given by 50(mA) x 64s) 30) 0.1 BF The droop rate is 10009) <1 avis 0.1(MF) Tavis Considerations for choosing C '* C should be large enough to minimize the ‘droop’ caused by leakage currents in Q and IC2 ‘© C should be small enough to track fast signals since it forms a low-pass filter with the ON resistance of Q. Parallel or flash A/D converter In the flash A/D converter the analog input is compared with many reference voltages simultaneously. For an 1-bit converter, 2" ~ 1 analog comparators are used. Various reference voltages are generated by a resistive divider of 2" resistors connected between two voltage sources (or a single voltage source) representing the lower and upper limits of the desired conversion range. The basic structure for a 3-bit converter is shown in Figure 2.29. ‘The comparators generate 2" — 1 bits of information in which all of the comparators helow the inpnt voltage produce Is, and all af the comparators above the input voltage produce 0s. A priority encoder is used to convert the comparators output to the proper binary output. Table 2.2 gives the truth table of the priority encoder. The biggest advantage of this converter is its high speed and it usually operates in the 100-MHz to several-GHz range, providing between 6 and 10 bits of resolution. The major di perfectly matched components, these are available mostly in the single chip form. For each additional bit of resolution, the number of comparators double, which drives up both chip area and power consumption. wdvantage is the circuit complexity. Because of the complexity and the heavy reliance onMD itn Tareas snd Trarmernnion Tecilogy Analog input vole. Va Prirty encoder Reference — J voltage V; tp ee 0.875 ¥, oh R +f 0730, |, R 0.625 Vi, Digital output ot, R = 0500, i oben ® Pp oxy, nr R Pp 02s0y, 17) R S Figure 229A Sit fash AID converter Table 22. Truth tbl of pristy encoder Ta Ouapar hh bh bh kh kb bo oh 0, 0, O% To ¢ 6 6 6 OO 0 0 Oo x 10 0 0 0 00 0 0 1 x x 1 0 0 0 00 0 1 0 x x x 1 0 0 0.0 o 14 xox x x 1000 1 0 0 eee OR 10 4 KX eK KR x TO 1 10 xox x x xX Xx KL 14 Sigma delta A/D converter Conventional converters, as illustrated in Figure 2.30, are often difficult to implement in fine line VLSI technology with reasonably low power consumption, These difficulties arise because conventional methods need analog components that are precise and highly immune t0XD tn Tareas nd Trarmerntion Teciogy nine steps of 0.001 Q and a series resistance of calibrated manganin bar of 0.0011 Q with a sliding contact for balancing. The total resistance of R, is therefore 0.0101 @. When the switch position is changed to select a suitable value of the standard resistor, the resistor of Ry farm changes thereby changing the ratio of Rs and Rj. But the total resistance seen by the battery does not change. The contact resistance comes in series with a high resistance of ratio arms, and so has negligible effect. The accuracy of measurement of R, increases by selecting the ratio Ry/R; so that a large part of the standard resistor is used in the measuring circuit. This circuit is used for the measurement of winding resistances of machines and transformers, contact and earth conductor resistances with an accuracy of about #0.2%. 5.3 ALTERNATING CURRENT BRIDGES The ac bridges are usually employed to measure impedance, inductance, capacitance, quality factor and dissipation factor conveniently and accurately. They are also used for phase shifting, providing feedback paths for oscillators and amplifiers, filtering out undesirable signals and measuring frequency. Like a de bridge, an ac bridge in its basic form consists of four arms (each an impedance), a source of excitation (ac source) and a balance detector sensitive to small alternating potential differences like head phone, vibration galvanometer or tuneable amplifier detector. Before we discuss the bridge, let us familiarize ourselves with the impedance and other related terms used in these bridges. Impedance is the basic clectrical parameter used to characterize electronic circuits, components, and materials. It is defined as the ratio of the voltage applied to the device and the resulting current through it. That is, impedance is the total opposition a circuit offers to the flow of an alternating current (ac) at a given frequency, and is generally represented as a complex quantity, Z. Resistance (R), inductance (L) and capacitance (C) form an impedance. Impedance, Z= = = R+jX where X is defined as the reactance. In real world, electronic components are not pure resistors, inductors or capacitors, but a combination of all three or two as shown in Figure 5.18. The figure also shows the phasor diagrams of each of the combinations. Today's generation of LCR bridges are capable of displaying these parameters and can easily calculate and display many other parameters such as Z, YX, G, B, D, etc. which are defined in Table 5.1 Here f= frequency in hertz, @ = 2nf, R and X are equivalent series quantities unless otherwise defined, G and B are equivalent parallel quantities unless otherwise defined. Subscript ‘p’ stands for parallel and subscript ‘s’ stands for series. We define @ as being positive if itis inductive, negative if it 18 capacitive. We define D as positive it capacitive. The abbreviation ESR stands for Equivalent Series Resistance. A low value of D or a high value of @ means capacitor or inductor is quite pure while a high D or low Q means resistor is nearly pure. Note that D or Q of an impedance is independent of the configuration of the equivalent circuit used to represent it.Bridge ironenes) ED Ou M-0 POR Impedance Capacitive Inductive Figure 5.18 Phasor diagrams of series and parallel representation of components Table 5.1 Impedance and associated terms Parameter ‘Quantity Unit, symbol Formula Zz Impedance ohm, Q Z= Ry+iX,= : [zl e# IzI Magnitude of Z ohm, @ Izl= (ax? i Ry or ESR Resistance, ohm, Q real part of Z x Reaetance, imaginary part of Z y Admitance siemens, § Il Magnitude of Y siemens, $ 6, Real part of Z siemens, S By Susceptance siemens, § (ContdXD tn Tareas nd Trarmerntion Teciogy ‘Table S.1 Impedance and associated terms (Contd.) Parameter Quantity Unit, symbol ey Series farad, F capacitance op Parallel farad, F capacitance L Series henry, H inductance Ly Parallel henry, H inductance Ry Parallel ohm, & resistance 2 Quality factor None D, DF, an 6 Dissipation factor None 6 Phase angle of Z degree or radian @= 9 8 o Phase angle of Y degree or radian Figure 5.19 shows the basic ac bridge circuit. All impedances are complex quantities. Let us denote complex quantities by overbar letters. The voltage across the detector under the balance condition should be zero. Therefore, Splitting this equation in magnitude and phase angle, we get the following two equations to be simultaneously satisfied for the balance condition:_——— rte) ac source, Vs é igure 5.19 Basic ac bridge circuit. 12,124 1=12s 1251 and 0; + Oy = 0+ Os Similarly, for the case of admittances, we have Ir [= 16 IL and D+ = Ot Os The product of the magnitudes of the impedances/admittances of the opposite arms must be equal and the sum of the phase angles of the opposite arms must be equal. Example 5.8 An ac bridge is driven by a 500 Hz sinusoidal source. Is the bridge balanced if at this frequency the bridge arms have the following impedances? (@) Z,=44)4, +i, Bad, Z, (b) Z, = 4+ j4, “il, Ba4, Z, Solution (a) Since 12, 11Z.1= 12) IZ, |, we get ai=4i This equation is satisfied Also 0+ = +0Dict Taare cd Traramerntion Teciogy or 45° 40° = 45° + 0° This equation is also satisfied. Hence the bridge is balanced, (b) Since |Z, |Z, |=1Z; [12s |, we get Ve +4 VP +0? =P +1 Va +0? Ay2 =4V2 Thi equation is satisfied. Also 0, + 0 = 0) + 0 or 45° + 0° = -45° + 0° This equation is not satisfied. Hence the bridge is not balanced. Example 5.9 An ac bridge is driven by a 2 kHz sinusoidal source. Given Z,=10kQ, Z,=50kQ, Z, = seties combination of a resistor of value 100 k& and a capacitor of value 100 HF, Z, =series combination of an unknown resistor and an unknown reactive element. Find the value of the unknown resistor and the type and the value of the unknown reactive element. Solution Let the unknown resistance be denoted by R, and the unknown reactive element be an inductor of value Z,. The balance equation of the bridge is RAR, + X19) = RolRs ~ iXes) Equating real and imaginary parts, we get RyR, = Rey (independent of signal frequency and voltage) and IR Xi. = IRaXea This is only possible if the unknown element is also a capacitor. Therefore, we assume the unknown reactive element to be a capacitor of value C,. This equation yields R\Cy = R:C, (independent of signal frequency and voltage)_——— rte) Therefore the unknown component values are R, R R 2 Ry = 500k and C,= Sic, = 20 pF ra re Bess 20H 5.3.1 Maxwell Bridge This bridge is used to determine the value of an inductor and its quality factor in terms of known capacitance at power and audio frequencies. Figure 5.20 shows the circuit. AC source R Figure 5.20, Maxwell bridge. The balance equation is From the bridge, we have Ry Z.=R.+ iol, 1 at oe Substituting in the balance equation and equating real and imaginary parts, we have =k, and = RRC Both the equations are independent of the frequency and voltage of the signal ‘The bridge is balanced first by varying Ry for inductive balance and then Ry for resistive balance. Quality factor of the inductor is equal to X,_ ol, 2 @RC, R, R, This can be measured in terms of the known values of signal frequency, the value of Ry and CC; of from the measured values of L, and RyXD tn Tareas nd Trarmerntion Teciogy From the balance equation of phase angles 0, + 0, = 8 + 8 we observe that since Z, and Z; are resistors, the right-hand side of this equation is zero (@; and 8; are 0°). For balance, the left-hand side should also be zero. Note that 8; is negative (capacitive) and 6, is positive (inductive). For large value of Q, R, should be minimum, i.e. 8, is closer to +90°, Therefore, 64 should also be closer to -90°, ic. R should be very large. There may be a practical problem to get variable resistors of very large values. Maxwell bridge is, therefore, used to measure medium Q coils (inductors) say between 1 and 10. The bridge ie aloo not ouitable for measurement of very low @ values (Q < 1) because of balance of convergence problem. For low value of Q, R, is large and L, is small, e.g. inductive resistors or RF coils at low frequency. Since in the equations of R, and Ls, Rs appears in both the equations, if for inductive balance, Ry is decreased, it changes balance also for R,, This is called sliding balance. To balance for R, again, Ry has to be changed. This iteration may take very long time giving rise w balance of convergence problem. For medium values of Q, resistive effect is not large and the balance is achieved after a few iterations. As seen from the balance equations, we may use variable C, instead of variable Ry for Inductive balance to avoid balance of convergence problem. But it is di variable standard capacitors. Hay's bridge is used to measure inductance of high Q values. Example 5.10 Find the series inductance, resistance and Q of an inductive clement using Maxwell bridge. Given Z, = parallel combination of a resistor of value 470 Q and a capacitor of value 0.22 wh, 'Z, =Z,=1 kQ. The bridge is driven by a 2 kHz sinusoidal source. Solution R= Beg = 1 1090 = 2.13 Ko R470 L,= RaRyC = 1000 x 1000 x 0.22 x 10°6 = 0.22 H 2mfRiCy Q = arc 2.x 3.143 x 2000 x 470 x 0.22 x 10% 3 5.3.2 Hay’s Bridge Hay's bridge is similar to Maxwell bridge except now Ry is in series with C). This is used to ‘measure inductances of high Q value. Figure 5.21 shows the circuit.ater) AC source igure 5.21 Hay's onidge. From the bridge, we have Z= Ry Zs=Ry Z,=R,+ jo, RoRsC, Tog: Md = ape 140°C R 1+@'GR Both the equations are dependent on the frequency of the signal. Quality factor of the inductor is equal to Kh RR GR 2 Thie can bo meacured in terme of known valuce of signal frequency, the value of Ry and C, or from the measured values of L, and Ry. We can write expressions for R, and L, in terms of Q as follows: RRs R= "O41 For large Q, We see that for high Q, the value of L, is independent of the signal frequency and has the same relation as of Maxwell bridge. Further, the value of R, is small compared to the relation of Maxwell bridge because of high Q.@ 5.3.3. Schering Bridge This bridge is the most popular bridge and is used to measure capacitance and its insulating properties. Figure 5.22 shows the bridge circuit. AC source Figure 5.22 Schering bridge. Cis a high quality standard capacitor, This is usually a mica capacitor, which has very low losses for general measurements, and ait capacitor for insulation measurement. Air capacitor can be designed (0 have stable capacitance value of small electric field so that the insulating material is kept out of strong fields. From the bridge, we have Both the equations are independent of the frequency and voltage of the signal Dissipation factor of the capacitor is equal 10 eax This can be measured in terms of the known values of signal frequency, the value of Ry and CC; or from the measured values of C, and R,, For nearly pure capacitor, D should be very low, ic. the value of R, should be very less which implies that the phase angle, should be nearly equal to -90°. From the balance equation of phase angles 1k RC, = ORC, 0+ = 040aie ries) We observe that since Z) is a resistor and Z, is a capacitor, the right-hand side of this equation is very close to 90°, For balance, the left hand side should also be 90°, Note that 4 is also close to -90° for low values of D. To match the angles, Z; is made capacitive and is varied. In fact, at a given frequency, keeping R, fixed, we can directly calibrate variation of C; in terms of D. Example 5.11 ‘The Schering bridge balances under the following conditions: Ry = 10 kQ, Rz = 1 kQ, C1 = 100 pF, and C = 400 pF. The bridge is driven by a 1 kHz sinusoidal source. (a) Find the values of Ry, C, and D. (b) If the series combination of R, and C, is to be replaced by a parallel combination Ry and Cy, find their values. Solution @ GAR _ 100 10° 10" _ 45 400 x10 4001077 10210” _ gay pe 10 D = @R,C, = 2#fR,C, = 2 x 3.143 x 1000 x 10 x 10° x 100 x 10" = 0.006286 (b) From Table 5.1, &, RA + Q?) and C, Now Therefore, Ry = 250(1 + 159.08") = 6.33 MQ. and 4000 pF So we can replace arm 4 with an equivalent circuit having these values. Example 5.12 The Schering bridge is used to measure the permittivity of an insulator sample, The arm 4 consists of two electrodes in which sample is inserted. First the bridge is balanced without sample between the electrodes with the following conditions: Ry = Ry 100 pF and C3 = 200 pF. Then the sample is inserted between the electrodes, and balance is achievedMD ici Trtoneras nd Trsrmerntion Tecnology with the following conditions: R, = Ry = 10 k®, C, = 800 pF and Cy = 1200 pF. The bridge is driven by a 1 kHz sinusoidal source in each case, Find the relative permittivity of the specimen. Solution Let the value of the unknown capacitance without the sample be denoted by C, and that with the sample by Cas Then c= 4 ond c= S04 d a where €, is the permittivity of the specimen, & is the permittivity of the air, A is the area of the clectwako, and fis the opaving Detween die elecwwles. Diving diese twu eyoatinss we et Relative permittivity of the specimen, €, From the balance equation of the bridge, we have 200 x10"? x10 x10° TR 10 x10° and y= RL 200X102 10210909 9p 10x10 1200 ‘Therefore, relative permittivity of the specimen, € = ~ "200 5.3.4 Wien Bridge This bridge is used in many applications like notch filter, oscillators, ete. Here we shall study it as a frequency determining bridge. Figure 5.23 shows the circuit of the bridge. From the bridge, we have i Loc. BR. a= Rn Y= tiOCs. Zy= Ry BaR ae GR ag tics. Zi= Re Substituting in the balance equation and equating real and imaginary parts, we have BLK Re Rs and 1 1 f gg pet __ RROG IIR ROGates) 9 AC source igure 5.23 Wien bridge circuit In most of the bridges, components are selected so that Ry = Ry = R and C, = C these two equations reduce to = C. Then RB i Baz wt S-apR Keeping R; = 2R, and fixing C; = Cy = C, we can calibrate R, = Ry = R in terms of frequency. In fact, R, and Ry can be ganged together so that variation in both the resistors is same. Since the balancing of the bridge depends upon the frequency, it may be difficult t0 balance if the signal contains harmonics. 5.3.5 Wagner Ground Connection The basic ac bridge citcuit as shown in Figure $.19 assumes that all the impedances are lumped and do not interact with each other. In practice, stray capacitances exist between bridge elements and the ground and across each bridge arm. These stray capacitances. shunt the arms and cause error in measurements especially at high frequencies when the impedances of these capacitors become small. One way to control stray capacitances is to use shielded ‘wives with sliclds commcuied W givund, This dues nut remove die effect of eapacitances but makes them constant in value and thereby compensates their effect. Wagner ground connection can be used especially to eliminate the stray capacitance effect. Figure 5.24 shows the connections. Let C), C>, C3 and Cy be the stray capacitances between point a, d, b and c and ground respectively. Zs and Z, are impedances of the Wagner earth branch and consist of variable resistor and (or) variable capacitor. These are chosen in such a way that they can form a balance with Z, and Z and Z and Zs The following procedure is adopted to balance the two bridges: Keep switch at position 1 and try to balance the bridge by varying Z, and (or) Zs. The presence of stray capacitances will prevent a true balance but a point of minimum detector reading can be achieved. Change the position of the switch to 2 to balance the bridge by varying Zs and (or) Z to a point of minimum detector reading. Again, change the position of the switch to position 1 and rebalance the bridge by varying Z, and (or) Z3. Repeat the process tll the detector reads zero both for positions 1 and 2 of the switch. Under this condition, points ¢ and d are at ground