International Journal of Computer Science and Electronics Engineering (IJCSEE) Volume 1, Issue 5 (2013) ISSN 2320-401X; EISSN 2320-4028
Ternary Function Minimization by
Map Method
Vikram R. Ghiye, Dr. A.P. Dhande, and Sharan H. Bonde
Abstract— This paper presents the algorithm for the function
minimization of multivalued i.e. radix >2 digital system. The ternary
digital system which radix=3 is considered here for the
demonstration of proposed algorithm and computer program is
developed based on algorithm in the form of ternary map.
As the radix of system increases, the difficulties in the
minimization or reduction of logic function is get increases. It
becomes difficult to for higher radix to reduce the function design
equation. The proposed program is developed for the ternary system
function minimization. It incorporates all designed rules for ternary
logic system design and gives the output in the form of Sum-of-
Product (SOP) terms.
There are different rules for the minimization of ternary logic
based digital system that are different from the conventional binary
digital system. Output equation of ternary digital system is in the
form of F = F2 + 1. (F1) Where, F2 = 2’s minterms and F1 = 1’s
minterms. The results are verified for ternary full adder and
subtractor are tested on program and compared with truth table for
ternary full adder and subtractor and obtained results are found to be
accurate.
Keywords— Multivalued; Radix; Sum-of-Product (SOP);
Ternary; Unary function.
I. INTRODUCTION
A LEXANDER gave a wonderful explanation for the
implementation of any switching circuits natural base is
very efficient radix i.e. e = 2.71828 [1]. So it is seen that radix
3 is more efficient technique for implementation of digital
system than that of 2. In ternary logic system there have been
3 valued switching. It is possible to implement sequential as
well as combinational circuit implementation by using ternary
logic system and it is realized as well [2, 3]. Ternary logic
digital system can offers some of important advantages over
the binary logic digital systems. This advantages are
requirements of interconnection is get reduced, so indirectly
the chip area is also get reduced, by using ternary logic
systems number of functions available is also increases [4].
Vikram R. Ghiye is with Pune Institute of Computer Technology, Pune,
Maharashtra, India (Phone +919730464825, e-mail- vikramghiye
@hotmail.com).
Dr. A.P. Dhande is with the Department of Electronics and
Telecommunication, Pune Institute of Computer Technology, Pune, India
(Phone- +919822406967, e-mail: ashwpict@yahoo.com).
Sharan H. Bonde is with Pune Institute of Computer Technology, Pune,
Maharashtra, India (Phone- +918097326103, e-mail:
sharanbonde@hotmail.com).
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Ternary logic system is a subject of research from many
years, but in practical or a real-life VLSI application
implementing an additional logic level is not to be designed
yet.
Though various ternary logic models are available in the
literature, but all of them suffer from some of the drawbacks.
Either there may be high power consumption or depend on
customized technological processes, or implement
multithreshold devices [5-7]. Many of the proposed ternary
logic circuits use dynamic logic and consume static power [8].
The paper presented here is focuses merely on
minimization of ternary logic. The ternary circuits or system
can be implemented based on BJT, MOSFETs etc. It is
referred as T-gates as well [9, 10]. In binary switching theory
which is for binary circuits where uses relays or switches who
has two positions. In this paper the minimization of function
of output of circuit is explained. The voltage switching in
ternary digital circuits is based on or familiar with binary
circuit design as well as simplification techniques. The
research is aimed towards producing the lower cost ternary
function which has most reduced output terms. The multiple-
valued logic algebra development has proceeded since the
pioneering papers of Lukasiewicz and Post. Since then, there
have been many multiple-valued logic algebra developed
[11]. There are several multivalued algebras available to
choose among for a given digital system. One major criterion
for selecting the appropriate algebra in which to implement
the system should be the ease of fault detection and location
in that algebra. These considerations provide a strong
motivation for the study of fault detection and location
techniques in multivalued digital circuits [12]. This paper is
related with the minimization of ternary logic function by
using k-map method. Here the given ternary equation is
minimized and then it can be used for representation of digital
circuit output.
II. TERNARY ALGEBRA
In binary logic system logic level is represented as 𝑍 = {0,
1}, where 1 = true and 0 = false, similarly values in ternary
would be the 𝑍 = {0, 1, 2}. In ternary voltage switching
circuits the three voltage levels are presented by 0, 1 and 2.
Here 0 represents the low, 1 represents intermediate, and 2
represents high potential. Let consider a system 𝑍 whose
elements called propositions or statements are valued in the
set {0, 1, and 2}. In 𝑍 the operations of addition (+) and
multiplication (.) are defined [13].
 International Journal of Computer Science and Electronics Engineering (IJCSEE) Volume 1, Issue 5 (2013) ISSN 2320-401X; EISSN 2320-4028

𝑥 + 𝑦 = max(𝑥, 𝑦) (1) metrics. The remaining reduced functional sets are evaluated
𝑥 ∙ 𝑦 = min(𝑥, 𝑦) (2) based on the degree of approximation to the absolute minimal
functional set. There degrees reflect the order and number of
There is relationship which is inter related in the ternary metric matches relative to the absolute functional set on a per
logic system is [14]. function basis. Functions associated with higher degrees shall
have satisfied the requirements for any lower degrees. The
Commutative: coarse or lowest degree is connected to product term
𝑥+𝑦=𝑦+𝑥 (3) equivalence, succeeded by MIN-literal matching, and finally
𝑥∙𝑦 =𝑦∙𝑥 (4) equal fundamental gate quantity having the highest degree.
Associative: The biggest or finest degree refers to expressions which are
(𝑥 + 𝑦) + 𝑧 = 𝑥 + (𝑦 + 𝑧) (5) reduced to their absolute smallest form. However general
𝑥 ∙ (𝑦 ∙ 𝑧) = (𝑥 ∙ 𝑦) ∙ 𝑧 (6) observations are as assisted by such information for a
Distributive: comprehensive assessment of the algorithms and methods
𝑥 + 𝑦𝑧 = (𝑥 + 𝑦) ∙ (𝑥 + 𝑧) (7) [15].
𝑥 ∙ (𝑦 + 𝑧) = 𝑥 ∙ 𝑦 + 𝑥 ∙ 𝑧 (8) Expressions consisting of equivalent quantity of product
Absorption: terms are further distinguished by the overall combined size
𝑥+𝑥∙𝑦 =𝑥 (9) of their product terms. In such instances, expressions
𝑥 ∙ (𝑥 + 𝑦) = 𝑥 (10) associated with the lowest value produce superior reductions.
Idempotent: The size of a product term consists of its fan-in requirements
𝑥+𝑥 =𝑥 (11) and is equal to the sum of MIN-literal for each vertex plus one
𝑥∙𝑥 =𝑥 (12) for the term’s constant coefficient. When a MIN-literal spans
all p logical values, then the product term is said to be
There are some law which are used to minimize the independent of the associated vertex and its MIN-literal is
ternary logic system [14] this are removed from the product term. Product terms with constant
coefficients equivalent to the highest logical value p-1,
��� x1 + ���
x 0 + ��� x 2 = x���2 (13) dispense with mining the constant coefficient along with the
���� x ∙ x = x���0
x ∙ ���
0 1 ���
2 (14)
MIN-literals [15]. There are various method has been
��� proposed for reduction of ternary equation such as Map
x1 = x���2
x 0 + ��� (15)
reduction technique, Quine-McCluskey method, Scheinman's
x ∙ x1 = x���0
���
0 ��� (16) Binary method. The scope of this paper is restricted to
x•0= 0 (17) reduction of ternary equation or simplification of ternary
x•2= x (18) equation by using MAP method.
x+0= x (19) There is set of some rules or protocol for joining the
x+2= 2 (20) adjacent cells for minimization of the ternary function [13] i.e.
1) The group of arrays of 3 × 1, 3 × 2, 3 × 3 cells can be
There exist 33 = 27 different unary functions on 𝑍 to 𝑍. formed to provide the output values coincide with the values
We single out them and denote [13] as shown in Table I. of one of the inputs.
2) It is permitted to join (properly) adjacent cells with equal
TABLE I
UNARY FUNCTIONS
output values.
x 𝑥0 𝑥1 𝑥2 𝑥 01 𝑥 12 𝑥𝑥 𝑥∆
3) Multiple uses of cells for different arrays are permitted.
4) Cells with the output value 2 can be considered as "don't
0 2 0 0 2 0 0 2 care" for the formation of arrays with the output value 1.
1 0 2 0 2 2 1 2 Output equation of ternary digital system is in the form of
2 0 0 2 0 2 2 2 F1 and F 2 terms i.e.
F = F 2 + 1• (F 1 ) (25)
Table I of unary function shows that
x0 + x1 + x2 = x∆ (21) Where,
F 2 = 2’s minterms and
Also we can represent
F 1 = 1’s minterms.
x01 = x 0 + x1 (22)
x12 = x1 + x 2 (23)
A. Two-Variable Maps
x1 = x 01 • x12 (24)
Two variable map can be represent as shown below in fig.1
where fif.2 represents the corresponding output values for its
III. FUNCTION MINIMIZATION related input.
An output functional set which has been reduced to its
absolute minimal form is according to the priority cost

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 International Journal of Computer Science and Electronics Engineering (IJCSEE) Volume 1, Issue 5 (2013) ISSN 2320-401X; EISSN 2320-4028

TABLE II
TERNARY TWO VARIABLES MAPS REPRESENTATION
0 1 2
0 x1 x2 x3
1 x4 x5 x6
2 x7 x8 x9

Values x 1 , x 2 …. x 9 in Fig. 1 represents the output of the
digital system. These values may be 0, 1and 2. It may be
possible that it is don’t care as well, here don’t care is
represented by “×”. All the rules of map reduction can be
applicable for two variable reduction techniques. Following
are some example for two variable map reductions.
Fig. 3 Map for Two Ternary Variables
Consider the map given in fig.3, first consider the 2’s term
so we grouping can be done as shown in fig.4. Here 2’s term
in A2 column is common so take common term as A2,
similarly second group is formed by row of B2 therefore the
output for the given group is equal to B2 equation 28
represents the output for the map in figure 4.

Fig. 1 Ternary Two Variable Maps

Example 1:- Let’s take half adder, which have the input to
be “A”, “B" and output SUM is “Z” and CARRY is “C”. The
Fig. 4 Map for Grouping Of 2’s Term
Truth table for half adder is shown in table III.

TABLE III Output for 2’s term is

TRUTH TABLE FOR HALF ADDER
INPUT OUTPUT f 2 = A 2 + B2 (28)
SUM CARRY
A B
Z C
Similarly for grouping of 1’s term consider 2 as don’t care
0 0 0 0
0 1 1 0
so we can group the map as shown in fig 5. Knowing that for
0 2 2 0 grouping of 1’s term, 2’s terms are don’t care so we can make
1 0 1 0 them “×”, Here “×” represents don’t care and the grouping is
1 1 2 0 formed as shown in below fig.5.
1 2 0 1 From the map shown in fig.5, reduction can be done as
2 0 2 0
A0+A1+A2 or B0+B1+B2. Therefore from the table of unary
2 1 0 1 ∆
2 2 1 1 function, x0+x0+x0 = x = 2 can be said. then the
output for 1’s term is
The map for the table III is given in figure 2.
f1 = 2 (29)

Fig. 2 Map for SUM And Map For CARRY

Fig. 5 Map for Grouping Of 1’s Term
In fig. 2 There is not any group can form. So directly we
can write equation for SUM and CARRY as, The output equation for ternary system is represented by
terms of 2’s and 1’s, so it can be writing as in the form of
SUM = A2B0 +A1B1 +A0B2 +1 ( A1B0 +A0B1+A2B2) (26) F = f 1 +f 2
CARRY =0+ 1 (A2B1+A1B2+A2B2) (27)
Output = 2+1• A 2+B2 (30)
Example 2:-Let consider following map

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Example 3:- Let consider following map two variables. Fig.5. shows grouping of consequent six 2’s
and three 1’s combination for three variable map.

Fig. 6 Map for Two Ternary Variables

In the map given in fig. 6 first consider the 2’s term so

grouping is possible as shown in fig.7. Here A1 column has
common terms of 2, and other two terms are separated then Fig. 9 Map Three Dimensional Three Variable Maps [13]
final equation can be formed as given in equation 31.

Output for 2’s term is

f 2 = A 1 + A2B0 + A2B2 (31)

Fig.10 Two Dimensional Three Variable Map [13].

In fig.10 values x 1 , x 2…. x 9 represents the output of the

digital system. These values may be 0, 1and 2. It may be
possible that it is don’t care as well.
Example 1:- Let’s take full adder, which have the input to
Fig. 7 Map for Grouping Of 2’s Term
be “A”, “B" and output SUM is “Z” and CARRY is “C”. The
Truth table for full adder is given in table IV.
Similarly for 1’s term grouping consider 2 as don’t care so
we can group the map as shown in fig.8. TABLE IV
TRUTH TABLE FOR FULL ADDER
Output for 1’s term is INPUT OUTPUT
A B C SUM CARRY
0 0 2 Z C
f 1 = A + B +B (32)
0 0 0 0 0
0 0 1 1 0
The output equation for ternary system is represented by 0 0 2 2 0
terms of 2’s and 1’s, so it can be writing as in the form of 0 1 0 1 0
F = f 1 +f 2 0 1 1 2 0
0 1 2 0 1
0 2 0 2 0
Output = A 1 + A2B0 + A2B2 +1• A0 + B0 +B2 (33)
0 2 1 0 1
0 2 2 1 1
1 0 0 1 0
1 0 1 2 0
1 0 2 0 1
1 1 0 2 0
1 1 1 0 1
1 1 2 1 1
1 2 0 0 1
1 2 1 1 1
1 2 2 2 1
Fig.8. Map for Grouping Of 1’s Term 2 0 0 2 0
2 0 1 0 1
2 0 2 1 1
B Three variable maps 2 1 0 0 1
For three-variable functions can be draw as three- 2 1 1 1 1
dimensional map as shown in Fig. 9. But it is very difficult to 2 1 2 2 1
use this map for the performing operations so it is more 2 2 0 1 1
convenient to use the two-dimensional map shown in Fig. 10. 2 2 1 2 1
2 2 2 2 2
In this method of using two-dimensional map is similar to the

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 International Journal of Computer Science and Electronics Engineering (IJCSEE) Volume 1, Issue 5 (2013) ISSN 2320-401X; EISSN 2320-4028

The map for sum is representing as shown in fig. 11.

From fig. 11 we see that there is not any possibility for
grouping the element so directly we can write the equation for
sum.

Fig. 14 Map for Three Variable.

In map given in fig.14 first consider the 2’s term so

grouping can be done as the shown in fig.15. Here four
groups of 2’s terms are present, and final equation can be
Fig. 11 Map for Full Adder SUM formed as given in equation 36.

SUM = “A2B0C0 +A1B0C 1+A0B0C2+ A1B1C0+

A0B1C1+A2B1C2 +A0B2C0 +A2B2C1+
A1B2C2 +1 (A1B0C0+A0B0C1+A20B0C2 +
A0B1C0 +A2B1C1 + A1BC2+A2B2C0
A1B2C1+0B2C2)” (34)

Similarly fig. 12 shows the map for the carry here is only
one 2’s term and other are 1’s term so we directly write
equation for 2’s term and form group of 1’s term and find the
Fig .15 Map for Thee Variable Grouping for 2’s Term.
output equation. Equation 35 represents output equation for
carry in full adder fig.13. represents the grouping map for F 2 = C0 + C1 + C2 + B1 (36)
carry terms.
Similarly for 1’s term grouping considers 2 as don’t care so
we can group the map as shown fig.16.

.
Fig.12 Map for Full Adder CARRY.

From figure 13, wwe can obtain the solution as,

CARRY =A2B2C2 +1 (A0B2C1+A0B1C2+ A0B2C2 +
A1B0C2 + A2B0C1+A2B0C2+ A2B1C0
+A1B1C1+ A1B2C0 +A2B2C0) (35)
Fig. 16 Map for Thee Variable Grouping for 1’s Term.

F 1 = C1 + C2 (37)
The equation can be written in the form of

F=F 1 +F 2
F = C0 + C1 + C2 + B1+ C0 + C1 + C2 + B1 (38)

Fig .13 Map For Full Adder CARRY With Grouping. Example 3:- Let consider given example for finding ternary
output equation for it,
Example 2:- Let consider given map of three variable and
find out output equation for it,

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 International Journal of Computer Science and Electronics Engineering (IJCSEE) Volume 1, Issue 5 (2013) ISSN 2320-401X; EISSN 2320-4028
Fig .17 Map for Three Variable.
Map given in fig.17 first consider the 2’s term so we can
group as the shown in fig.18, then final equation can be
formed as given in equation 39.
Fig. 18 Map for Grouping Of 2’s Terms.
F 1 = B0 +B2 + C1 + A2
Similarly for 1’s term grouping considers 2 as don’t care so
we can group the map as shown fig.18. The output equation
for 1’s term is to be F 1 .
Fig .19 Map for Full Adder CARRY With Grouping.
0 2
F1 = B + B
Final output equation is given as
0 2 1 2 0 2
F = B +B + C + A + B + B
IV. APPLICATION
Plenty of applications over MVL system have been
developed earlier [16, 17]. A set of simultaneous equations in
Boolean algebra are required for obtaining the minimization
technique. Variety of applications can be developed easily
using these minimization techniques to reduce the solution.
Boolean equations used in this operations research are
referred to in [17]. Reducing the complexity of the circuit is
the major objective behind this research. Development of
calculus for the multivalued logic algebra system is one such
example.
IV. CONCLUSION
A ternary function minimization by a map method is gives
simplified solution. This paper dicsribe how to write equation
for the ternary k-MAP. The computer based programming
software tool can be implemented for mapping the equation.
The computer based programming software tool can be
extended to ‘N’ variables.
ACKNOWLEDGEMENT
With a deep sense of gratitude authors wishes to express
her sincere thanks to Miss. Roshani S. Nage for suggesting
the implementation method and helping in tool development
of proposed work. Further for her affectionate and undoubted
execution of her work. Author is fortunate to have her long
intricate and would like to remember lifetime.
REFERENCES
[1] D.I.porat, "Three valued digital system", Proc. IEE Vol. 116 , No. 6,
pp.947-955, June 1969.
[2] H.T.Mouhtaf, I.B.Jordan, “Study on the implementation
[3] of three valued logic", Proc.ISMVL, pp.359-372 May 1975.
[4] Seiichi M., "Micropower CMOS implementation of three valued logic
function", Proc.ISMVL, pp.61-63, May 1983.
[5] K.C.Smith, "The Prospects of Multivalued Logic Technology and
Application View", IEEE Transaction on Computer, Vol.-C-30, pp-619-
(39) 627, September 1981.
[6] H.M. Aytac, “Ternary Logic Based on a Novel MOS Building Block
Circuit”, Proc. IEEE Int. Symp. Multiple-Valued Logic (ISMVL), pp.
20–25, May 1983.
[7] P. Balla, A. Antoniou, “Low Power Dissipation MOS Ternary Logic
Family,” IEEE J. Solid-State Circuits, vol. 19, pp. 739–749, Oct.1984.
[8] X.Wu, F. Prosser, “CMOS Ternary Logic Circuits”, Proc. Inst. Elect.
Eng., vol.137, Feb.1990, pp. 21–27.
[9] J.S. Wang, et al., “Low Power Dynamic Ternary Logic,” Proc. Inst.
Elect. Eng., vol.135, no.6, pp. 221–230, Dec. 1988.
[10] Chung-Yu-Wu, "Design & Application Of Pipelined Dynamic CMOS
Ternary Logic & Simple Ternary Differential Logic", IEEE Journal On
Solid State Circuits, Vol.28, No-8, August 1993.
[11] T.H Iguchi, et. al., "Synthesis of optimal T-gate networks In multiple
valued logic" Proc. ISMVL, P.190-195, May 1979.
[12] Fath, A.A., et. al., “A CO-evolutionary Algorithm for Multi-Criterion
Optimization”, Proc. of (ISAS/SCI’99) 3rd World Multiconference on
Systemic, Cybernetics and Informatics & 5th Int. Conf. on Inf. Sys.
Analysis and Synthesis, USA 1999.
[13] Richard J., et al., “Detection of Single, Stuck-Type Failures in
Multivalued Combinational Networks”, IEEE Transactions on
(40) Computers, Vol. C-26, No. 12, pp.1242-1251, Dec. 1977.
[14] M. Yoeli, et al., “Logical Design of Ternary Switching Circuits”, IEEE
Transactions on Electronic Computers 1965.
[15] H.T.Moufftah, “Study on Implementation of Three Valued Logic”,
Proc.ISMVL, pp.359-372, May 1995.
(41) [16] Alexander E. et al., “Comparative Analysis of Algorithms For The
Minimization Of Multivalued Logic Functions” CH2766 - 4/89/0000 –
0559 IEEE, pp.559-564, 1989.
[17] A.P. Dhande, V.T. Ingole, “Design and Implementation of Two Bit
Ternary ALU Slice”, Science of Electronic, Technologies of
Information and Telecommunication, March 2005, Tunisia.
[18] T.N. Rajashekhara, I-Shi Eric Chen, “Fast Adder Design Using
Redundant Sign Digit Number”, International Journal of Electronics,
1990.
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 International Journal of Computer Science and Electronics Engineering (IJCSEE) Volume 1, Issue 5 (2013) ISSN 2320-401X; EISSN 2320-4028

Vikram R. Ghiye, Amravati, 15 September 1989, Perusing

Masters in Electronics and telecommunication
(Microwave)Engineering from Pune Institute Of Computer
Technology Pune, Maharashtra, India. Completed Bachelor
degree in Electronics and telecommunication Engineering
from Pune Vidyarhi Gruha’s College of Engineering And Technology ,Pune
in 2011, Maharashtra, India.
He completed Diploma in Electronics and telecommunication Engineering
from Autonomous institute of Maharashtra Amravati in 2008, Maharashtra,
India.
Currently working with Pune Vidyarhi Gruha’s College of Engineering
And Technology, Pune Maharashtra, India . Published Paper on Novel
Algorithm on Ternary Logic System on multiple valued conference 2012 at
Japan. Email: vikramghiye@hotmail.com

Sharan H. Bonde, Born in 1990 in Kopargaon, India, currently

pursuing M.E. in Microwave engineering from Pune Institute of
Computer Technology, Pune University, Pune, Maharashtra,
India. He received B.E. in Electronics and Telecommunication
Engineering from Don Bosco Institute of Technology, Mumbai
University, Mumbai, Maharashtra, India in 2011. Email:
sharanbonde@hotmail.com

Dr. A.P. Dhande, Received his B.E., M.E. and Ph.D. in

1991, 1999 and 2007 respectively from Amravati University,
Maharashtra, India. Currently he is working as Professor in
Electronic Engineering department, Pune Institute of
Computer technology, an Engineering college at Pune,
Maharashtra, India. He carried out his Doctoral study in Multi Valued Logic.
His interest is in Digital Electronics and in Astronomy. Email:
ashwpict@yahoo.com

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