FSQ0565R, FSQ0765R Green-Mode Fairchild Power Switch (FPS™) For Quasi-Resonant Operation

FSQ0565R, FSQ0765R — Green-Mode Farichild Power Switch (FPS™) for Quasi-Resonant Operation
June 2008
FSQ0565R, FSQ0765R
Green-Mode Fairchild Power Switch (FPS™) for
Quasi-Resonant Operation - Low EMI and High Efficiency
Features Description
Optimized for Quasi-Resonant Converter (QRC) A Quasi-Resonant Converter (QRC) generally shows
Low EMI through Variable Frequency Control and AVS lower EMI and higher power conversion efficiency than a
(Alternating Valley Switching) conventional hard-switched converter with a fixed
High-Efficiency through Minimum Voltage Switching switching frequency. The FSQ-series is an integrated
Narrow Frequency Variation Range over Wide Load Pulse-Width Modulation (PWM) controller and
and Input Voltage Variation SenseFET specifically designed for quasi-resonant
Advanced Burst-Mode Operation for Low Standby operation and Alternating Valley Switching (AVS). The
Power Consumption PWM controller includes an integrated fixed-frequency
Simple Scheme for Sync Voltage Detection oscillator, Under-Voltage Lockout (UVLO), Leading-
Pulse-by-Pulse Current Limit Edge Blanking (LEB), optimized gate driver, internal soft-
Various Protection functions: Overload Protection start, temperature-compensated precise current sources
(OLP), Over-Voltage Protection (OVP), Abnormal for a loop compensation, and self-protection circuitry.
Over-Current Protection (AOCP), Internal Thermal Compared with a discrete MOSFET and PWM controller
Shutdown (TSD) with Hysteresis, Output Short solution, the FSQ-series can reduce total cost,
Protection (OSP) component count, size, and weight; while simultaneously
Under-Voltage Lockout (UVLO) with Hysteresis increasing efficiency, productivity, and system reliability.
Internal Start-up Circuit This device provides a basic platform for cost-effective
Internal High-Voltage Sense FET (650V) designs of quasi-resonant switching flyback converters.
Built-in Soft-Start (17.5ms)
Applications
Power Supply for LCD TV and Monitor, VCR, SVR,
STB, and DVD & DVD Recorder
Adapter
Related Resourses
Visit: http://www.fairchildsemi.com/apnotes/ for:
AN-4134: Design Guidelines for Offline Forward
Converters Using Fairchild Power Switch (FPS™)
AN-4137: Design Guidelines for Offline Flyback
Converters Using Fairchild Power Switch (FPS™)
AN-4140: Transformer Design Consideration for
Offline Flyback Converters Using Fairchild Power
Switch (FPS™)
AN-4141: Troubleshooting and Design Tips for
Fairchild Power Switch (FPS™) Flyback Applications
AN-4145: Electromagnetic Compatibility for Power
Converters
AN-4147: Design Guidelines for RCD Snubber of
Flyback
AN-4148: Audible Noise Reduction Techniques for
Fairchild Power Switch Fairchild Power Switch(FPS™)
Applications
AN-4150: Design Guidelines for Flyback Converters
Using FSQ-Series Fairchild Power Switch (FPS™)
© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

FSQ0565R, FSQ0765R Rev. 1.0.1
Free Datasheet http://www.datasheet4u.com/

Ordering Information
Maximum Output Power(1)
Product Operating Current RDS(ON) 230VAC±15%(2) 85-265VAC Replaces
PKG.(5)
Number Temp. Limit Max. Open Open Devices
Adapter(3) Adapter(3)
Frame(4) Frame(4)
FSCM0565R
FSQ0565R TO-220F-6L -40 to +85°C 3.0A 2.2Ω 70W 80W 41W 60W
FSDM0565RB
FSCM0765R
FSQ0765R TO-220F-6L -40 to +85°C 3.5A 1.6Ω 80W 90W 48W 70W
FSDM0765RB
Notes:
1. The junction temperature can limit the maximum output power.
2. 230VAC or 100/115VAC with doubler.
3. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient temperature.
4. Maximum practical continuous power in an open-frame design at 50°C ambient.
5. These parts are RoHS compliant.

FSQ0565R, FSQ0765R Rev. 1.0.1 2

Application Diagram
VO
AC
IN
Vstr
Drain
PWM
Sync GND
FB VCC
FSQ0765R Rev.00
Figure 1. Typical Flyback Application
Internal Block Diagram
Sync Vstr VCC Drain

5 6 3 1
AVS OSC
Vref
0.35/0.55
VCC good
VCC Vref VBurst
8V/12V
Idelay IFB
FB 3R PWM
S Q
4
Gate
Soft- LEB
R R Q driver
Start 250ns
tON < tOSP
after SS
VOSP LPF
AOCP
2
VSD TSD S Q VOCP
GND
(1.1V)
LPF R Q
VOVP
VCC good
FSQ0765R Rev.00
Figure 2. Internal Block Diagram

FSQ0565R, FSQ0765R Rev. 1.0.1 3

Pin Configuration
6. Vstr
5. Sync
4. FB
3. VCC
2. GND
1. Drain
FSQ0765R Rev.00
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin # Name Description
1 Drain SenseFET drain. High-voltage power SenseFET drain connection.
2 GND Ground. This pin is the control ground and the SenseFET source.
Power Supply. This pin is the positive supply input. This pin provides internal operating cur-
3 VCC
rent for both start-up and steady-state operation.
Feedback. This pin is internally connected to the inverting input of the PWM comparator. The
collector of an opto-coupler is typically tied to this pin. For stable operation, a capacitor should
4 FB
be placed between this pin and GND. If the voltage of this pin reaches 6V, the overload pro-
tection triggers, which shuts down the FPS.
Sync. This pin is internally connected to the sync-detect comparator for quasi-resonant switch-
5 Sync
ing. In normal quasi-resonant operation, the threshold of the sync comparator is 1.2V/1.0V.
Start-up. This pin is connected directly, or through a resistor, to the high-voltage DC link. At
start-up, the internal high-voltage current source supplies internal bias and charges the exter-
6 Vstr
nal capacitor connected to the VCC pin. Once VCC reaches 12V, the internal current source is
disabled. It is not recommended to connect Vstr and Drain together.

FSQ0565R, FSQ0765R Rev. 1.0.1 4

Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-
ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-
tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA = 25°C, unless otherwise specified.
Symbol Parameter Min. Max. Unit

Vstr Vstr Pin Voltage 500 V
VDS Drain Pin Voltage 650 V
VCC Supply Voltage 20 V
VFB Feedback Voltage Range -0.3 13 V
VSync Sync Pin Voltage -0.3 13 V
FSQ0565R 11 A
IDM Drain Current Pulsed
FSQ0765R 14.4 A
TC = 25°C 2.8
FSQ0565R A
TC = 100°C 1.7
ID Continuous Drain Current(6)
TC = 25°C 3.6
FSQ0765R A
TC = 100°C 2.28
Single Pulsed Avalanche FSQ0565R 190 mJ
EAS
Energy(7) FSQ0765R 570 mJ
PD Total Power Dissipation(Tc=25oC) 45 W
Internally
TJ Operating Junction Temperature -40 °C
limited
TA Operating Ambient Temperature -40 +85 °C
TSTG Storage Temperature -55 +150 °C
Electrostatic Discharge Capability, Human Body Model 2.0 kV
ESD
Electrostatic Discharge Capability, Charged Device Model 2.0 kV
Notes:
6. Repetitive rating: Pulse width limited by maximum junction temperature.
7. L=14mH, starting TJ=25°C.
Thermal Impedance
TA = 25°C unless otherwise specified.
Symbol Parameter Package Value Unit

θJA Junction-to-Ambient Thermal Resistance (8)
50 °
C/W
TO-220F-6L
θJC Junction-to-Case Thermal Resistance (9)
2.8 °
C/W
Notes:
8. Free standing with no heat-sink under natural convection.
9. Infinite cooling condition - refer to the SEMI G30-88.

FSQ0565R, FSQ0765R Rev. 1.0.1 5

Electrical Characteristics
Symbol Parameter Condition Min. Typ. Max. Unit

SENSEFET SECTION
BVDSS Drain Source Breakdown Voltage VCC = 0V, ID = 100µA 650 V
IDSS Zero-Gate-Voltage Drain Current VDS = 560V 300 µA
Drain-Source On-State FSQ0565R TJ = 25°C, ID = 0.5A 1.76 2.20
RDS(ON) Ω
Resistance FSQ0765R TJ = 25°C, ID = 0.5A 1.3 1.6
FSQ0565R 78
COSS Output Capacitance VGS = 0V, VDS = 25V, f = 1MHz pF
FSQ0765R 125
FSQ0565R 22
td(on) Turn-On Delay Time VDD = 350V, ID = 25mA ns
FSQ0765R 22
FSQ0565R 52
tr Rise Time VDD = 350V, ID = 25mA ns
FSQ0765R 70
FSQ0565R 95
td(off) Turn-Off Delay Time VDD = 350V, ID = 25mA ns
FSQ0765R 105
FSQ0565R 50
tf Fall Time VDD = 350V, ID = 25mA ns
FSQ0765R 65
CONTROL SECTION
tON.MAX Maximum On Time TJ = 25°C 8.8 10.0 11.2 µs
tB Blanking Time TJ = 25°C, Vsync = 5V 13.5 15.0 16.5 µs
tW Detection Time Window TJ = 25°C, Vsync = 0V 6.0 µs
fS Initial Switching Frequency 59.6 66.7 75.8 kHz
ΔfS Switching Frequency Variation(11) -25°C < TJ < 85°C ±5 ±10 %
tAVS On Time at VIN = 240VDC, Lm = 360μH 4.0 µs
AVS Triggering
Feedback (AVS triggered when VAVS>spec
VAVS Threshold(9) 1.2 V
Voltage & tAVS<spec.)
Sync = 500kHz sine input
tSW Switching Time Variance by AVS(11) 13.5 20.5 µs
VFB = 1.2V, tON = 4.0µs
IFB Feedback Source Current VFB = 0V 700 900 1100 µA
DMIN Minimum Duty Cycle VFB = 0V 0 %
VSTART 11 12 13 V
UVLO Threshold Voltage
VSTOP After turn-on 7 8 9 V
tS/S Internal Soft-Start Time With free-running frequency 17.5 ms
BURST-MODE SECTION
VBURH TJ = 25°C, tPD = 200ns(10) 0.45 0.55 0.65 V
VBURL Burst-Mode Voltages 0.25 0.35 0.45 V
Hysteresis 200 mV
Continued on the following page...

FSQ0565R, FSQ0765R Rev. 1.0.1 6

Electrical Characteristics (Continued)
Symbol Parameter Condition Min. Typ. Max. Unit

PROTECTION SECTION
Peak Current FSQ0565R TJ = 25°C, di/dt = 370mA/µs 2.64 3.00 3.36
ILIMIT A
Limit FSQ0765R TJ = 25°C, di/dt = 460mA/µs 3.08 3.50 3.92
VSD Shutdown Feedback Voltage VCC = 15V 5.5 6.0 6.5 V
IDELAY Shutdown Delay Current VFB = 5V 4 5 6 µA
(11)
tLEB Leading-Edge Blanking Time 250 ns
tOSP Threshold Time TJ = 25°C 1.2 1.4 µs
Output Short Threshold Feedback OSP triggered when tON<tOSP ,
VOSP 1.8 2.0 V
Protection(9) Voltage VFB>VOSP & lasts longer than
tOSP_FB Feedback Blanking Time tOSP_FB 2 2.5 3.0 µs
TSD Thermal Shutdown Temperature 125 140 155
°C
Hys Shutdown(9) Hysteresis 60
SYNC SECTION
VSH1 1.0 1.2 1.4
Sync Threshold Voltage 1 VCC = 15V, VFB = 2V V
VSL1 0.8 1.0 1.2
tsync Sync Delay Time(11)(12) 230 ns
VSH2 4.3 4.7 5.1
Sync Threshold Voltage 2 VCC = 15V, VFB = 2V V
VSL2 4.0 4.4 4.8
ISYNC_MAX = 800µA
VCLAMP Low Clamp Voltage 0.0 0.4 0.8 V
ISYNC_MIN = 50µA
VOVP Over-Voltage Threshold Voltage VCC = 15V, VFB = 2V 7.4 8 9.6 V
tOVP Protection Blanking Time(11) 1.0 1.7 2.4 µs
TOTAL DEVICE SECTION
Operating Supply Current
IOP VCC = 13V 1 3 5 mA
(Control Part Only)
VCC = 10V
ISTART Start Current 350 450 550 µA
(before VCC reaches VSTART)
Start-up Charging Current VCC = 0V, VSTR = mininmum
ICH 0.65 0.85 1.00 mA
50V
VSTR Minimum VSTR Supply Voltage 26 V
Notes:
10. Propagation delay in the control IC.
11. Guaranteed by design, but not tested in production.
12. Includes gate turn-on time.

FSQ0565R, FSQ0765R Rev. 1.0.1 7

Comparison Between FSDM0x65RNB and FSQ-Series
Function FSDM0x65RE FSQ-Series FSQ-Series Advantages

Improved efficiency by valley switching
Constant Quasi-Resonant
Operation Method Reduced EMI noise
Frequency PWM Operation
Reduced components to detect valley point
Valley Switching
Frequency
EMI Reduction Reduce EMI Noise Inherent Frequency Modulation
Modulation
Alternate Valley Switching
CCM or AVS
Hybrid Control Based on Load Improves efficiency by introducing hybrid control
and Input Condition
Advanced
Burst-Mode Burst-Mode
Burst-Mode Improved standby power by AVS in burst-mode
Operation Operation
Operation
OLP, OVP, Improved reliability through precise AOCP
Strong Protections OLP, OVP
AOCP, OSP Improved reliability through precise OSP
145°C without 140°C with 60°C Stable and reliable TSD operation
TSD
Hysteresis Hysteresis Converter temperature range

FSQ0565R, FSQ0765R Rev. 1.0.1 8

Typical Performance Characteristics
These characteristic graphs are normalized at TA= 25°C.
1.2 1.2
Normalized
Normalized
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Temperature [°C] Temperature [°C]
Figure 4. Operating Supply Current (IOP) vs. TA Figure 5. UVLO Start Threshold Voltage
(VSTART) vs. TA
1.2 1.2
Normalized
Normalized
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Figure 6. UVLO Stop Threshold Voltage Figure 7. Start-up Charging Current (ICH) vs. TA
(VSTOP) vs. TA
1.2 1.2
Normalized
Normalized
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Figure 8. Initial Switching Frequency (fS) vs. TA Figure 9. Maximum On Time (tON.MAX) vs. TA

FSQ0565R, FSQ0765R Rev. 1.0.1 9

Typical Performance Characteristics (Continued)
1.2 1.2
Normalized
Normalized
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Figure 10. Blanking Time (tB) vs. TA Figure 11. Feedback Source Current (IFB) vs. TA
1.2 1.2
Normalized
Normalized
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Figure 12. Shutdown Delay Current (IDELAY) vs. TA Figure 13. Burst-Mode High Threshold Voltage
(Vburh) vs. TA
1.2 1.2
Normalized
Normalized
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Figure 14. Burst-Mode Low Threshold Voltage Figure 15. Peak Current Limit (ILIM) vs. TA
(Vburl) vs. TA

FSQ0565R, FSQ0765R Rev. 1.0.1 10

Typical Performance Characteristics (Continued)
1.2 1.2
Normalized
Normalized
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Figure 16. Sync High Threshold Voltage 1 Figure 17. Sync Low Threshold Voltage 1
(VSH1) vs. TA (VSL1) vs. TA
1.2 1.2
Normalized
Normalized
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Figure 18. Shutdown Feedback Voltage (VSD) vs. TA Figure 19. Over-Voltage Protection (VOV) vs. TA
1.2 1.2
Normalized
Normalized
1.0 1.0
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
0.0 0.0
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120
Figure 20. Sync High Threshold Voltage 2 Figure 21. Sync Low Threshold Voltage 2
(VSH2) vs. TA (VSL2) vs. TA

FSQ0565R, FSQ0765R Rev. 1.0.1 11

Functional Description 2.2 Leading-Edge Blanking (LEB): At the instant the
internal SenseFET is turned on, a high-current spike
1. Start-up: At start-up, an internal high-voltage current
usually occurs through the SenseFET, caused by
source supplies the internal bias and charges the
primary-side capacitance and secondary-side rectifier
external capacitor (Ca) connected to the VCC pin, as
reverse recovery. Excessive voltage across the Rsense
illustrated in Figure 22. When VCC reaches 12V, the
resistor would lead to incorrect feedback operation in the
FPS™ begins switching and the internal high-voltage current-mode PWM control. To counter this effect, the
current source is disabled. The FPS continues its normal FPS employs a leading-edge blanking (LEB) circuit. This
switching operation and the power is supplied from the circuit inhibits the PWM comparator for a short time
auxiliary transformer winding unless VCC goes below the (tLEB) after the SenseFET is turned on.
stop voltage of 8V.
VCC Vref
VDC Idelay IFB
VO VFB SenseFET
4 OSC
FOD817A
D1 D2
Ca CB 3R
+ Gate
VFB* R driver
VCC Vstr KA431 -
3 6
OLP Rsense
ICH VSD
FSQ0765R Rev. 00
Vref
8V/12V VCC good
Figure 23. Pulse-Width-Modulation (PWM) Circuit
Internal
Bias 3. Synchronization: The FSQ-series employs a quasi-
FSQ0765R Rev.00
resonant switching technique to minimize the switching
Figure 22. Start-up Circuit noise and loss. The basic waveforms of the quasi-
resonant converter are shown in Figure 24. To minimize
the MOSFET's switching loss, the MOSFET should be
2. Feedback Control: FPS employs current-mode turned on when the drain voltage reaches its minimum
control, as shown in Figure 23. An opto-coupler (such as value, which is indirectly detected by monitoring the VCC
the FOD817A) and shunt regulator (such as the KA431) winding voltage, as shown in Figure 24.
are typically used to implement the feedback network.
Vds
Comparing the feedback voltage with the voltage across
the Rsense resistor makes it possible to control the
VRO
switching duty cycle. When the reference pin voltage of
the shunt regulator exceeds the internal reference
VRO
voltage of 2.5V, the opto-coupler LED current increases, VDC
pulling down the feedback voltage and reducing the duty

cycle. This typically happens when the input voltage is
Vsync tF
increased or the output load is decreased.
Vovp (8V)
2.1 Pulse-by-Pulse Current Limit: Because current-

mode control is employed, the peak current through the 1.2V
SenseFET is limited by the inverting input of PWM 1.0V
comparator (VFB*), as shown in Figure 23. Assuming

230ns Delay
that the 0.9mA current source flows only through the
MOSFET Gate
internal resistor (3R + R = 2.8k), the cathode voltage of
diode D2 is about 2.5V. Since D1 is blocked when the
feedback voltage (VFB) exceeds 2.5V, the maximum ON ON
voltage of the cathode of D2 is clamped at this voltage,
clamping VFB*. Therefore, the peak value of the current FSQ0765R Rev.00
through the SenseFET is limited.
Figure 24. Quasi-Resonant Switching Waveforms

FSQ0565R, FSQ0765R Rev. 1.0.1 12

The switching frequency is the combination of blank time
tB=15μs tX
(tB) and detection time window (tW). In case of a heavy
load, the sync voltage remains flat after tB and waits for
valley detection during tW. This leads to a low switching
frequency not suitable for heavy loads. To correct this IDS IDS
drawback, additional timing is used. The timing
conditions are described in Figures 25, 26, and 27. When
the Vsync remains flat higher than 4.4V at the end of tB VDS
that is tX, the next switching cycle starts after internal
delay time from tX. In the second case, the next switching
ingnore
occurs on the valley when the Vsync goes below 4.4V
4.4V
within tB. Once Vsync detects the first valley within tB, the
Vsync
other switching cycle follows classical QRC operation. 1.2V
1.0V
internal delay
tB=15μs tX FSQ0765R Rev. 00
Figure 27. After Vsync Finds First Valley
IDS IDS 4. Protection Circuits: The FSQ-series has several

self-protective functions, such as Overload Protection
(OLP), Abnormal Over-Current Protection (AOCP),
VDS Over-Voltage Protection (OVP), and Thermal Shutdown
(TSD). All the protections are implemented as auto-
restart mode. Once the fault condition is detected,
switching is terminated and the SenseFET remains off.
4.4V This causes VCC to fall. When VCC falls down to the
Vsync Under-Voltage Lockout (UVLO) stop voltage of 8V, the
1.2V
1.0V protection is reset and the start-up circuit charges the
VCC capacitor. When the VCC reaches the start voltage
internal delay FSQ0765R Rev. 00 of 12V, normal operation resumes. If the fault condition is
not removed, the SenseFET remains off and VCC drops
Figure 25. Vsync > 4.4V at tX to stop voltage again. In this manner, the auto-restart can
alternately enable and disable the switching of the power
tX SenseFET until the fault condition is eliminated.
tB=15μs Because these protection circuits are fully integrated into
the IC without external components, the reliability is
improved without increasing cost.
Fault Fault
VDS Power
IDS IDS occurs removed
on
VDS
VCC
4.4V
12V
Vsync
1.2V
1.0V
8V
internal delay FSQ0765R Rev. 00 t

Normal Fault Normal
FSQ0765R Rev. 00 operation situation operation
Figure 26. Vsync < 4.4V at tX
Figure 28. Auto Restart Protection Waveforms

FSQ0565R, FSQ0765R Rev. 1.0.1 13

4.1 Overload Protection (OLP): Overload is defined as
the load current exceeding its normal level due to an
unexpected abnormal event. In this situation, the 3R
OSC
protection circuit should trigger to protect the SMPS. PWM S Q
Gate
However, even when the SMPS is in the normal LEB
R Q driver
250ns
operation, the overload protection circuit can be R
triggered during the load transition. To avoid this
undesired operation, the overload protection circuit is Rsense
designed to trigger only after a specified time to
+
2
AOCP GND
determine whether it is a transient situation or a true -
VOCP
FSQ0765R Rev.00
overload situation. Because of the pulse-by-pulse
current limit capability, the maximum peak current
through the SenseFET is limited, and therefore the Figure 30. Abnormal Over-Current Protection
maximum input power is restricted with a given input
voltage. If the output consumes more than this maximum
4.3 Output-Short Protection (OSP): If the output is
power, the output voltage (VO) decreases below the set
shorted, steep current with extremely high di/dt can flow
voltage. This reduces the current through the opto- through the SenseFET during the LEB time. Such a
coupler LED, which also reduces the opto-coupler steep current brings high voltage stress on drain of
transistor current, thus increasing the feedback voltage SenseFET when turned off. To protect the device from
(VFB). If VFB exceeds 2.5V, D1 is blocked and the 5µA such an abnormal condition, OSP is included in the FSQ-
current source starts to charge CB slowly up to VCC. In series. It is comprised of detecting VFB and SenseFET
this condition, VFB continues increasing until it reaches turn-on time. When the VFB is higher than 2V and the
6V, when the switching operation is terminated, as SenseFET turn-on time is lower than 1.2µs, the FPS
shown in Figure 29. The delay time for shutdown is the recognizes this condition as an abnormal error and shuts
time required to charge CFB from 2.5V to 6V with 5µA. A down PWM switching until VCC reaches Vstart again. An
20 ~ 50ms delay time is typical for most applications. abnormal condition output short is shown in Figure 31.
Turn-off delay
VFB FSQ0765R Rev.00 MOSFET
Drain
Rectifier
Diode Current
Current
Overload protection ILIM
6.0V VFB
0
Minimum turn-on time
2.5V D
Vo 1.2us
t12= CFB*(6.0-2.5)/Idelay output short occurs

0
t1 t2 t Io
FSQ0765R Rev. 00
Figure 29. Overload Protection 0
Figure 31. Output Short Waveforms

4.2 Abnormal Over-Current Protection (AOCP): When
the secondary rectifier diodes or the transformer pins are
shorted, a steep current with extremely high di/dt can 4.4 Over-Voltage Protection (OVP): If the secondary-
flow through the SenseFET during the LEB time. Even side feedback circuit malfunctions or a solder defect
though the FSQ-series has overload protection, it is not causes an opening in the feedback path, the current
enough to protect the FSQ-series in that abnormal case, through the opto-coupler transistor becomes almost
since severe current stress is imposed on the SenseFET zero. Then, VFB climbs up in a similar manner to the
until OLP triggers. The FSQ-series has an internal overload situation, forcing the preset maximum current
AOCP circuit shown in Figure 30. When the gate turn-on to be supplied to the SMPS until the overload protection
signal is applied to the power SenseFET, the AOCP triggers. Because more energy than required is provided
block is enabled and monitors the current through the to the output, the output voltage may exceed the rated
sensing resistor. The voltage across the resistor is voltage before the overload protection triggers, resulting
compared with a preset AOCP level. If the sensing in the breakdown of the devices in the secondary side.
resistor voltage is greater than the AOCP level, the set To prevent this situation, an OVP circuit is employed. In
signal is applied to the latch, resulting in the shutdown of general, the peak voltage of the sync signal is
the SMPS. proportional to the output voltage and the FSQ-series

FSQ0565R, FSQ0765R Rev. 1.0.1 14

uses a sync signal instead of directly monitoring the 6. Burst Operation: To minimize power dissipation in
output voltage. If the sync signal exceeds 8V, an OVP is standby mode, the FPS enters burst-mode operation. As
triggered, shutting down the SMPS. To avoid undesired the load decreases, the feedback voltage decreases. As
triggering of OVP during normal operation, there are 2 shown in Figure 33, the device automatically enters
points to be considered which is depicted in Figure 32. burst-mode when the feedback voltage drops below
One is the making the peak voltage of the sync signal VBURL (350mV). At this point, switching stops and the
should be designed below 6V and the other is that be output voltages start to drop at a rate dependent on
sure to make the spike of sync pin as los as possible not standby current load. This causes the feedback voltage
to get longer than tOVP by decreasing the leakage to rise. Once it passes VBURH (550mV), switching
inductance shown at VCC winding coil. resumes. The feedback voltage then falls and the
VVcc_coil &VCC
process repeats. Burst-mode operation alternately
FSQ0765R Rev.00
enables and disables switching of the power SenseFET,
Absolue max VCC (20V) thereby reducing switching loss in standby mode.
VCC VVcc_coil
VO
VOset
VFB
Npri
VDC
NVcc
0.55V
Improper OVP triggering 0.35V

Vsync
VOVP (8V)
IDS
tOVP VSH2 (4.8V)
tOVP
VCLAMP
VDS
Figure 32. OVP Triggering
4.5 Thermal Shutdown with Hysteresis (TSD): The time

Switching Switching
SenseFET and the control IC are built in one package. disabled disabled
t1 t2 t3 t4
This makes it easy for the control IC to detect the FSQ0765R Rev.00
abnormally high temperature of the SenseFET. If the

temperature exceeds approximately 140°C, the thermal Figure 33. Waveforms of Burst Operation
shutdown triggers IC shutdown. The IC recovers its 7. Switching Frequency Limit: To minimize switching
operation when the junction temperature decreases loss and Electromagnetic Interference (EMI), the
60°C from TSD temperature and VCC reaches start-up MOSFET turns on when the drain voltage reaches its
voltage (Vstart). minimum value in quasi-resonant operation. However,
this causes switching frequency to increases at light load
conditions. As the load decreases or input voltage
5. Soft-Start: The FPS has an internal soft-start circuit increases, the peak drain current diminishes and the
that increases PWM comparator inverting input voltage switching frequency increases. This results in severe
with the SenseFET current slowly after it starts up. The switching losses at light-load condition, as well as
typical soft-start time is 17.5ms. The pulse width to the intermittent switching and audible noise. These problems
power switching device is progressively increased to create limitations for the quasi-resonant converter
establish the correct working conditions for transformers, topology in a wide range of applications.
inductors, and capacitors. The voltage on the output To overcome these problems, FSQ-series employs a
capacitors is progressively increased with the intention of frequency-limit function, as shown in Figures 34 and 35.
smoothly establishing the required output voltage. This Once the SenseFET is turned on, the next turn-on is
mode helps prevent transformer saturation and reduces prohibited during the blanking time (tB). After the
stress on the secondary diode during start-up.
blanking time, the controller finds the valley within the
detection time window (tW) and turns on the MOSFET, as
shown in Figures 34 and Figure 35 (Cases A, B, and C).

FSQ0565R, FSQ0765R Rev. 1.0.1 15

If no valley is found during tW, the internal SenseFET is 8. AVS (Alternating Valley Switching): Due to the
forced to turn on at the end of tW (Case D). Therefore, quasi-resonant operation with limited frequency, the
the devices have a minimum switching frequency of switching frequency varies depending on input voltage,
48kHz and a maximum switching frequency of 67kHz. load transition, and so on. At high input voltage, the
switching on time is relatively small compared to low
tsmax=21μs input voltage. The input voltage variance is small and the
IDS IDS switching frequency modulation width becomes small. To
improve the EMI performance, AVS is enabled when
input voltage is high and the switching on time is small.
A
tB=15μs Internally, quasi-resonant operation is divided into two
categories; one is first valley switching and the other is
ts second-valley switching after blanking time. In AVS, two
successive occurrences of first-valley switching and the
IDS IDS other two successive occurrences of second-valley
switching is alternatively selected to maximize frequency
B modulation. As depicted in Figure 35, the switching
frequency hops when the input voltage is high. The
tB=15μs internal timing diagram of AVS is described in Figure 36.
ts fs 1
Assume the resonant period is 2μs
15μs
67kHz
1
59kHz
17 μs
53kHz
IDS IDS 1
48kHz
19 μs
AVS trigger point
C
Constant 1
Variable frequency within limited range
tB=15μs frequency
21μs
CCM DCM
AVS region
ts
D C B A
IDS IDS
Vin
FSQ0765 R Rev.00
D Figure 35. Switching Frequency Range

tB=15μs
tW=6μs
tsmax=21μs FSQ0765R Rev. 00
Figure 34. QRC Operation with Limited Frequency
Vgate
Synchronize
Synchronize
Vgate continued 2 pulses Vgate continued another 2 pulses Vgate continued 2 pulses
GateX2 1st valley switching 2nd valley switching 1st valley switching
One-shot fixed fixed fixed fixed fixed fixed
AVS triggering de-triggering triggering

1st or 2nd is depend on GateX2 1st or 2nd is dependent on GateX2
VDS tB tB tB tB tB tB
GateX2: Counting Vgate every 2 pulses independent on other signals. 1st valley- 2nd valley frequency modulation.
Modulation frequency is approximately 17kHz.
FSQ0765R Rev. 00
Figure 36. Alternating Valley Switching (AVS)

FSQ0565R, FSQ0765R Rev. 1.0.1 16

PCB Layout Guide
Due to the combined scheme, FPS shows better noise
immunity than conventional PWM controller and
MOSFET discrete solution. Further more, internal drain
current sense eliminates the possibility of noise
generation caused by a sensing resistor. There are some
recommendations for PCB layout to enhance noise
immunity and suppress natural noise inevitable in power-
handling components.
There are typically two grounds in the conventional
SMPS: power ground and signal ground. The power
ground is the ground for primary input voltage and
power, while the signal ground is ground for PWM
controller. In FPS, those two grounds share the same
pin, GND. Normally the separate grounds do not share
the same trace and meet only at one point, the GND pin.
More, wider patterns for both grounds are good for large
currents by decreasing resistance.
Capacitors at the VCC and FB pins should be as close
as possible to the corresponding pins to avoid noise from
the switching device. Sometimes Mylar® or ceramic
capacitors with electrolytic for VCC is better for smooth
operation. The ground of these capacitors needs to
connect to the signal ground (not power ground). Figure 37. Recommended PCB Layout
The cathode of the snubber diode should be close to the
drain pin to minimize stray inductance. The Y-capacitor
between primary and secondary should be directly
connected to the power ground of DC link to maximize
surge immunity.
Because the voltage range of feedback and sync line is
small, it is affected by the noise of the drain pin. Those
traces should not draw across or close to the drain line.
When the heat sink is connected to the ground, it should
be connected to the power ground. If possible, avoid
using jumper wires for power ground and drain.
Mylar® is a registered trademark of DuPont Teijin Films.

FSQ0565R, FSQ0765R Rev. 1.0.1 17

Typical Application Circuit
Input Voltage Output Voltage

Application FPS™ Device Rated Output Power
Range (Maximum Current)
LCD Monitor 5.1V (2.0A)
FSQ0565R 85-265VAC 46W
Power Supply 12V (3.0A)
Features
Average efficiency of 25%, 50%, 75%, and 100% load conditions is higher than 80% at universal input
Low standby mode power consumption (<1W at 230VAC input and 0.5W load)
Reduce EMI noise through valley switching operation
Enhanced system reliability through various protection functions
Internal soft-start (17.5ms)
Key Design Notes

The delay time for overload protection is designed to be about 23ms with C105 of 33nF. If faster/slower triggering of
OLP is required, C105 can be changed to a smaller/larger value (e.g. 100nF for 70ms).
The input voltage of VSync must be between 4.7V and 8V just after MOSFET turn-off to guarantee hybrid control and
to avoid OVP triggering during normal operation.
The SMD-type 100nF capacitor must be placed as close as possible to VCC pin to avoid malfunction by abrupt pul-
sating noises and to improve surge immunity.
1. Schematic
FSQ0765R Rev.00 D201 L201
T1 5μH
EER3016 MBRF10H100
12V, 3A
10
1
C202
C201
R103 C104 1000μF
1000μF
R102 33kΩ 4.7nF 25V
2 8 25V
68kΩ 1W 630V
R104
D101
20Ω
C103 1N 4007
0.5W 3
100μF
2 400V
BD101
2KBP06M3N257 FSQ0565R
6
1 3 Vstr 1
Drain
5 R105 C106 C107 L202
D202
Sync 100Ω 100nF 47μF 5μH
MBRF1060
Vcc 0.5W SMD 50V
4 3 5V, 2A
4 Vfb 4 7
GND D102 C204
C102 C105 2 UF 4004 R107 C203
1000μF
150nF 33nF 18kΩ 1000μF
10V
275VAC 100V 6 10V
5
ZD101
1N4745A
C301
4.7nF
LF101 1kV
R108
34mH
12kΩ
R201
1kΩ
R101 R204
2MΩ 4kΩ
1W R202 C205
R203
1.2kΩ 47nF
1.2kΩ
Optional components IC301
FOD817A
IC201
C101 KA431
RT1 150nF R205
F1
5D-9 275VAC 4kΩ
FUSE
250V
2A
Figure 38. Demo Circuit of FSQ0565R

FSQ0565R, FSQ0765R Rev. 1.0.1 18

2. Transformer
FSQ0765R Rev.00 EER3016 FSQ0765R Rev.00 TAPE 4T

1
1 10 N /2 TAPE 1T
Lp/2
12V (0.4φ) 2
TAPE 2T
L12V/2
(TIW 0.5φ, 9 9 8 8
2 9 N /2 2parallel)
Np/2 12V TAPE 2T
LVcc(0.2φ) 4 5
TAPE 2T
L5V
3 8 (TIW 0.5φ, 7 7 6 6
Np/2 2parallel)
TAPE 2T
L12V/2 10 10 9 9
(TIW 0.5φ,
2parallel) TAPE 2T
4 7 2
Na N5V
Lp/2 TAPE 1T
(0.4φ) 3
5 6 Bottom of bobbin
Figure 39. Transformer Schematic Diagram of FSQ0565R
3. Winding Specification
Position No Pin (s→f) Wire Turns Winding Method

Top Insulation: Polyester Tape t = 0.025mm, 4 Layers
Np/2 2→1 0.4φ × 1 20 2-Layer Solenoid Winding
Insulation: Polyester Tape t = 0.025mm, 2 Layers
N12V/2 9→8 0.5φ × 2(TIW) 4 Center Solenoid Winding
Na 4→5 0.15φ × 1 10 Center Solenoid Winding
N5V 7→6 0.5φ × 2(TIW) 4 Center Solenoid Winding
N12V/2 10 → 9 0.5φ × 2(TIW) 5 Center Solenoid Winding
Bottom Np/2 3→2 0.4φ × 1 32 2-Layer Solenoid Winding
4. Electrical Characteristics
Pin Specification Remarks

Inductance 1-3 360µH ± 10% 100kHz, 1V
Leakage 1-3 15µH Maximum Short all other pins
5. Core & Bobbin

Core: EER3016 (Ae=109.7mm2)
Bobbin: EER3016

FSQ0565R, FSQ0765R Rev. 1.0.1 19

6. Demo Board Part List
Part Value Note Part Value Note

Resistor C205 47nF/50V Ceramic Capacitor
R101 2MΩ 1W C301 4.7nF/1kV Ceramic Capacitor
R102 68kΩ 1/2W Inductor
R103 33kΩ 1W L201 5µH 5A Rating
R104 20Ω 1W L202 5µH 5A Rating
R105 100Ω optional, 1/4W Diode
1A, 1000V General-Purpose
R107 18kΩ 1/4W D101 IN4007
Rectifier
R108 12kΩ 1/4W D102 UF4004 1A, 400V Ultrafast Rectifier
1W 16V Zener Diode
R201 1kΩ 1/4W ZD101 1N4745A
(optional)
R202 1.2kΩ 1/4W D201 MBRF10H100 10A,100V Schottky Rectifier
R203 1.2kΩ 1/4W D202 MBRF1060 10A,60V Schottky Rectifier
R204 5.2kΩ 1/4W IC
R205 4.7kΩ 1/4W IC101 FSQ0565R FPS™
Capacitor IC201 KA431 (TL431) Voltage Reference
C101 150nF/275VAC Box Capacitor IC202 FOD817A Opto-Coupler
C102 150nF/275VAC Box Capacitor Fuse
C103 100µF/400V Electrolytic Capacitor Fuse 2A/250V
C104 4.7nF/630V Film Capacitor NTC
C105 33nF/50V Ceramic Capacitor RT101 5D-9
C106 100nF/50V SMD (1206) Bridge Diode
C107 47µF/50V Electrolytic Capacitor BD101 2KBP06M2N257 Bridge Diode
Low ESR Electrolytic
C201 1000µF/25V Line Filter
Capacitor
C202 1000µF/25V LF101 34mH
Capacitor
C203 1000µF/10V Transformer
Capacitor
C204 1000µF/10V T1 EER3016 Ae=109.7mm2
Capacitor

FSQ0565R, FSQ0765R Rev. 1.0.1 20

Package Dimensions
TO-220F-6L (Forming)
MKT-TO220A06revB
Figure 40. 6-Lead, TO-220 Package

FSQ0565R, FSQ0765R Rev. 1.0.1 21


FSQ0565R, FSQ0765R Rev. 1.0.1 22

FSQ0565R, FSQ0765R Green-Mode Fairchild Power Switch (FPS™) For Quasi-Resonant Operation

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FSQ0565R, FSQ0765R Green-Mode Fairchild Power Switch (FPS™) For Quasi-Resonant Operation

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FSQ0565R, FSQ0765R — Green-Mode Farichild Power Switch (FPS™) for Quasi-Resonant Operation

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Free Datasheet http://www.datasheet4u.com/

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Free Datasheet http://www.datasheet4u.com/

Figure 1. Typical Flyback Application

Internal Block Diagram

Sync Vstr VCC Drain

Figure 2. Internal Block Diagram

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Figure 3. Pin Configuration (Top View)

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Symbol Parameter Min. Max. Unit

Symbol Parameter Package Value Unit

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Symbol Parameter Condition Min. Typ. Max. Unit

Continued on the following page...

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

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Symbol Parameter Condition Min. Typ. Max. Unit

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

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Function FSDM0x65RE FSQ-Series FSQ-Series Advantages

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pulling down the feedback voltage and reducing the duty

2.1 Pulse-by-Pulse Current Limit: Because current-

comparator (VFB*), as shown in Figure 23. Assuming

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Figure 27. After Vsync Finds First Valley

IDS IDS 4. Protection Circuits: The FSQ-series has several

internal delay FSQ0765R Rev. 00 t

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t12= CFB*(6.0-2.5)/Idelay output short occurs

Figure 31. Output Short Waveforms

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Improper OVP triggering 0.35V

Figure 32. OVP Triggering

4.5 Thermal Shutdown with Hysteresis (TSD): The time

abnormally high temperature of the SenseFET. If the

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Free Datasheet http://www.datasheet4u.com/

D Figure 35. Switching Frequency Range

tsmax=21μs FSQ0765R Rev. 00

Figure 34. QRC Operation with Limited Frequency

One-shot fixed fixed fixed fixed fixed fixed

AVS triggering de-triggering triggering

Figure 36. Alternating Valley Switching (AVS)

© 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com

Free Datasheet http://www.datasheet4u.com/

Mylar® is a registered trademark of DuPont Teijin Films.