INTEGRATED CIRCUIT DESIGN OF

A SEQUENTIAL STATE MACHINE

by
KAMALA N. VENKATARAMAN, B.S.E,

A THESIS

IN

ELECTRICAL ENGINEERING

Submitted to the Graduate Faculty

of Texas Tech University in
Partial Fulfillment of
the Requirements for
the Degree of
MASTER OF SCIENCE

IN

ELECTRICAL ENGINEERING

Approved

December, 1996
tnu- —

\ '^ 'I ^3 ACKNOWLEDGEMENTS

I express my sincere thanks to Dr. Micheal Parten, my thesis advisor, for his

guidance. I also express my gratitude to the graduate committee members. Dr. Sunanda

Mitra and Dr. Dirk Baldwin for their time and attention.

I am grateful to my friends for their encouragement and support. I dedicate this

work to my family, without whose blessings and support I would not have reached this

far.

11
 TABLE OF CONTENTS

ACKNOWLEDGEMENTS ii

LIST OF TABLES v

LIST OF nCURES vi

CHAPTER

I. INTRODUCTION 1

1.1 Perspective 1

1.1.1 Preview of Digital Systems 1

1.1.2 Sequential System Design I

1.2 Outiine 5

n. LOGIC DESIGN TECHNIQUES 6

2.1 Semi-Custom Techniques 6

2.1.1 Progranrunable Logic Device (PLD) 6

2.1.1.1 Programmable read only memories (PROMs) 7

2.1.1.2 Field Programmable Logic Arrays (FPLAs) 8

2.1.1.3 Programmable Array Logic (PAL) 10

2.1.1.4 Programmable Macro Logic (PML) 12

2.1.1.5 Sequential PLDs 14

2.1.2 Gate Arrays 16

2.1.3 Cell-Based Systems 17

2.2 Choice of Technique IX

iii
 III. STATE MACHINE DESIGN 23

3.1 Design Implementation Using Standard Building Blocks 23

3.2 General State Machine Architectiu-e 24

3.2.1 Input Forming Logic 24

3.2.2 Memory Element 27

3.2.3 Output Forming Logic 27

3.4 The Design Process 29

IV. DESIGN IMPLEMENTATION 35

V. RESULTS AND CONCLUSIONS 40

5.1 Results 40

5.1.1 Comparison 40

5.2 Conclusions 43

5.2.1 Advantages 43

REFERENCES 49

APPENDICES

A. DATA SHEETS OF STANDARD CELLS 51

B. SIMULATION OUTPUTS 65

IV
 m^

LIST OF TABLES

1.1 Integrated Cu*cuit Evolution 2

2.1 Comparison of the various implementation alternatives 21

3.1 Function Table 31

4.1 Mode Control Truth Table 37

5.1 Device count comparison 41

5.2 Chip coimt for the SSI/MSI implementation of the pop machine problem 42
 LIST OF FIGURES

1.1 General Model of a sequential state machine 2

2.1 Conceptual logic PROM diagram 7

2.2 Conceptual logic diagram of a FPLA 9

2.3 PAL conceptual logic diagram: a programmable AND - array followed by

a fixed OR - array 11

2.4 PML fundamental architecture 13

2.5 General architecture of a sequential PLD 14

2.6 Block Diagram of a programmable logic sequencer or registered PLA 14

2.7 Simple registered PAL-circuit diagram 15

2.8 Block-cell organization of gate arrays 17

2.9 Organization of a Standard Cell IC 18

3.1 General schematic of a 2° to 1 multiplexer 23

3.2 Architecture of the direct addressed multiplexer configuration 24

3.3 The Next State maps for multiplexer implementation 26

3.4 Input Forming Logic using MUXs 26

3.5 Use of output holding register 27

3.6 General Model of a sequential state machine using a shift register 30

3.7 Block Diagram of a general 4-bit shift register 30

3.8 Architecture of a 3-bit sequential state machine -using standard cells 34

4.1 General block diagram of the pop drop controller 35

VI
4.2 MDS diagram with the shift register sequence state assignement 36

4.3 The State Map and Action Map for the pop machine 36

4.4 The MODE CONTROL MAPS for the pop machine 37

4.5 The SERL\L LEFT DATA INPUT MAP for the pop machine 38

4.6 The Parallel Input Data Maps for the pop machine 38

4.7 State Map 38

4.8 The NEXT STATE or D maps for the pop machine 39

5.1 The output waveforms for the pop machine problem. 45

5.2 The shift register serial input and output waveforms. 46

5.3 The shift register parallel input and output waveforms. 47

5.4 The shift register output waveforms. 48

B. 1 The output waveforms for the pop machine problem (PSpice) 66

B.2 Output waveforms of the register for the pop machine problem (PSpice) 67

B.3 The shift register serial input and output waveforms (PSpice) 68

B.4 The shift register parallel input and output waveforms (PSpice) 69

vu
 CHAPTER I

INTRODUCTION

1.1. Perspective

The field of digital design has grown over the past few decades as design methods

and devices have been developed, tried and proven, paving the way into one of the most

fascinating and challenging fields of study. As new design techniques emerge, so comes

the necessity of making the designs more compact.

1. 1.1. Preview of Digital Systems

Digital systems can be broadly classified as combinational circuits and sequential

circuits [1]. Combinational circuits are logic systems whose outputs at any time are

determined from the present combination of inputs without regard to previous inputs.

Sequential circuits on the other hand have memory elements that form a feedback loop

from the output to input thus making the outputs depend on the previous history of inputs.

Finite State Machines or controlled digital systems [11, as they are called, are sequential

circuits that have some practical bounds goveming the number of different conditions

(states) in which a sequential machine can reside.

1.1.2. Sequential System Design

Sequential Systems in general consist of a next state decoder, memory and an

output decoder (Fig. 1.1). Traditionally sequential systems are designed from design
specifications through state diagrams, state assignments and present/next state maps.

These steps constitute a lengthy process when the problem is complex. The more

complex the problem, the more complex is the next state decoder design.

Next
Input Output
State •^Outputs
Combinational Memory Combinational
Logic Element Present Logic -• to the
or or State or -•Outside
Next State flip-flop Output -• Worid
Previous
Decoder Decoder
State
Inputs

Fig. 1.1 General Model of a sequential state machine [11

The issue of complexity raises the issue of implementation techniques. Though for almost

all problems the design techniques are the same, there are many ways to implement a

design in integrated circuits. Table 1.1 gives a summary of the various integration levels.

Table 1.1. Integrated Circuit Evolution [191

Integration Level Device count and description

Gate a few transistors and other components

SSI (Small Scale Integration)
MSI (Medium Scale Integration)
LSI (Large Scale Integration)
VLSI (Very Large Scale
Integration)
ASIC (Apphcation Specific
Integrated circuits)
combined to form an AND, OR or NOR
gate.
4 or more gates; NAND, NOR, OR-AND,
EXOR, NOT or INVERT.
up to 200 gates, registers, decoders.
multiplexers, etc.
several hundred gates, ALUs with scratch-
pad registers, interrupt controllers.
microprogram sequencers, ROMs, PROMs.
7(X) gates and up; CPUs, complex functions
up to 100,000 gates and increasing with
speeds at 1.4GHz and higher.
 As observed from the table, the density of the integrated circuits increases rapidly.

As levels of integration increase, the design effort needed for a full-custom design grows

drastically. A full-custom integrated circuit has traditionally 'hand-crafted' individual

transistors and other devices. The design time involved in such a design is very high. In

addition to the long and costly design, the development cost for the product is also very

high. For a full-custom design, all of the mask necessary to make an IC (integrated

cu-cuit) must be developed. Each new mask can only be used for that cu-cuit, which

significantiy increases the cost.

If predefined components or groups of components are used, the design can be

carried out at the functional level saving a lot of time and money. The concept of the

semi-custom integrated circuit is based on various techniques that have been developed for

achieving the objective stated above [181. The most common of these techniques can be

categorized as

• Gate-Arrays,

• Standard Cell based Systems,

• Programmable Logic Devices (Matrix Logic).

Each of these techniques has their own advantages and disadvantages. Looking at

them from the point of view of integration level, the gate-array is a regular matrix of logic

gates or components that are pre-defined up to the final stages of processing. This

normally involves patterning one or more layers of metal to form wires or tracks needed to

connect the pre-defined components together. In the standard cell approach, predesigned
functional cells that are equivalent to standard SSI and MSI logic families are stored in a

cell library in the form of separate cells. Cells can be selected from the library (according

to the eventual function that the chip is to perform) and arranged in parallel rows with

tracking lanes in between. The wires needed to connect the cells together are then routed

in metal through the tracking lanes. Programmable logic Devices or matrix logic contain a

matrix of AND-OR gates which may be a PLA/PAL along with some flip-flops. These are

different from the above two methods in that they are not mask-programmable but contain

fusible logic arrays.

All three methods can be used to implement any digital circuit. However, there are

tradeoffs in using each of these methods. Designers who need to make a choice of

implementation technique, have to know the pros and cons of each of these methods.

Some of the factors which influence their decision are development time, production time,

flexibility of the technique, etc.

Besides these factors another important issue which concerns designers is the

silicon area occupied by a technique. Existing techniques are continuously being improved

and new techniques are being investigated to produce a device which would occupy the

least space. However, these implementation methods may not be the best solution in all

cases. An alternative approach to implementation, may be sometimes relatively

advantageous in IC form.

The main objective of this thesis is to investigate a different IC implementation

technique and determine its effectiveness.

 1.3. Outiine

The paper is organized in the following fashion. Chapter II discusses the semi-

custom design techniques, primary PLD architectures, and defines the problem being dealt

with in this work. Chapter HI discusses the design in detail. Chapter TV discusses a

classical problem and its implementation using the new design and one of the standard

techniques. Chapter V gives a comparison of the methods employed and the results.
 CHAPTER II

LOGIC DESIGN TECHNIQUES

2.1. Semi-Custom Techniques

Semi-custom techniques can be broadly classified into three main categories,

Programmable Devices, Gate Arrays and Cell-Based Systems. As stated earlier, each of

these approaches has advantages and disadvantages. The choice of the technique depends

on the complexity of the design and the available resources.

2.1.1. Programmable Logic Device (PLD)

In recent times, programmable logic devices (PLD) seem to have gained a lot

of popularity with designers. One reason is that a PLD can replace many standard

SSI/MSI logic devices, depending on the complexity of the PLD and the circuitry

implemented in the device. Thus a design that would require a number of chips can

be implemented by using just one chip and programming it for the required apphcation.

This can significantly reduce the parts count and printed circuit board (PCB) area thereby

reducing inventory requirements and their costs. A designer has a range of PLDs to

choose from to implement his/her design. PLDs combine features found in standard

devices with those found in gate arrays, resulting in great versatility and utility. The

programmability provides ease of use for many required applications. However, the PLD

architecture results in some waste of silicon real estate.

 A PLD is a digital integrated circuit capable of being programmed to provide a

variety of different logical functions [4]. A PLD can be used for a number of unique

appUcations where common silicon is employed and only the chip's internal programming

is distinct. In this chapter, the primary PLD architectures, and designs using other

devices will be examined.

The most popular PLDs are programmable read only memories (PROMs), field

programmable logic arrays (FPLAs), programmable array logic (PAL), programmable

macro logic (PML) and other architectures like application specific PLDs which permit

more efficient use of silicon real estate compared to the general purpose PLDs.

2.1.1.1. Programmable read only memories (PROMs)

A PROM is a logic device that is in effect, composed of afixedAND array and a

programmable OR array [31, (Fig. 2.1).

8 words X 3 bits
Inputs
"OR" Ariay
(Program m able)
yb? Tcs' yi?

•O
•O -¥(r

•O

" A N D " Art.y

(Fix.d)
^ y ^ Outputs

Fig. 2.1. Conceptual logic PROM diagram

 This device has widespread application in data storage tables, code converters,

address decoding and character translation tables. PROM design can find application to

any design requiring complete decodability of its inputs. Thus, it is a device that can

implement a classic minterm expansion of an arbitrary logic function in n variables,

wherein every possible minterm is generated. Each minterm selects the address of the

word being addressed, and the output word is the selected "Oring" of each term [8].

However, most logic functions require only a small subset of the possible

minterms. Hence there is a large waste of chip resources, due to the presence of a surplus

of decoded terms that are unnecessary for the designer. Further, the PROM is limited to

some extent by the number of input variables. This is because of the PROM architecture

where the addition of one variable results in the doubling of the fuse matrix [ref3, ref9].

For example consider a PROM with 3 inputs; the possible input combinations are 2 = 8 .

Increasing by one variable makes the possible combinations 2"^=16 that is double of the

former number.

The size for a PROM is normally indicated as:

(Number of input combinations x Number of outputs)

or

(2n X number of outputs).

2.1.1.2. Field Programmable Logic Arrays (FPLA)

Limitations of the PROM led to the development of the FPLA wherein both the

AND array and the OR array are programmable for maximum flexibility [11], (Fig. 2.2).

8
The AND array combines the inputs together in selective ways to yield some collection of

product terms, the P-terms. The OR array combines the P-terms together in selective

ways to yield the output sum-of-product Boolean function [7,6]. These devices have the

capability of product term sharing that is, identical product terms occurring in different

output equations can be shared. This frees an AND gate for use in other equations [2].

To some extent, this device permits utilization of only the product terms required for a

specific application. The 2° growth problem of the PROM is lessened for larger word

sizes as full decodabUity is removed [3].

8 words X 3 bits

Inpu ts
"OR" Array
(Program mable)
^i? T^ "fi?
yfyfC y^yf. >[c>|c Q>
^oe^oe^o^
^<r e^oe^o^ ^^ ^< ^^

^oe^oe^o^ ->e ^e ^^

*7Tr y>|< yfyf—[> ^^ ^<: ^^

^oe^oe^^^ ^^ ^^

^oooe^e<—Q> ^^ ^<:

>oe^e^^e<—[>
" A N D " A rray
^99 O u tputs
(Program m able)

Fig. 2.2. Conceptual logic diagram of a FPLA

Acceptance of FPLA has been impeded by a number of factors, including lack of

design software, relatively slow propagation delays, and relatively high cost resulting from

its large die size. Since both the AND- and OR- arrays are placed on the same chip, the

number of fuses, and thus size of the chip, is large. Further as each product term can
connect to multiple sum terms, the additional capacitance of multiple sum terms slows the

worst-case propagation delay through the device [4]. Though IC technology

improvements have been trying to overcome these drawbacks, all these problems led to

the development of the programmable array logic. There is considerable literature

[12,13,14,15,16] on the ongoing research for new improved design techniques for the

FPLA.

2.1.1.3. Programmable Array Logic (PAL)

The PAL is a mixture of FPLA architecture and PROM architecture. It has a

programmable AND-array and a fixed OR-array as shown in the conceptual diagram

below[3]. Fig. 2.3. A set number of product terms are connected to each OR gate and

product terms are not shared. In effect, there is very little difference between designing

PLAs and designing PALs, except that it is easier to design the latter.

PAL architecture precludes the use of OR-array fuses and hence the amount of

silicon required to implement devices of similar complexity is considerably less with PALs

than with FPLAs. The propagation delay is also much less than the FPLA. The PAL

architecture supports logic implementation in the sum of products form (SOP),

which all combinatorial logic equations can be expressed in. Further it is supported by

relatively more user friendly software to help in the logic design process. This feature has

made this device universally popular.

10
 3 In-3 Out-8 Products

Inputs
•OR" Array
(Fixed)
N? M N^ r^

>ooeoe^—[>

" A N D " Array

7 7 9 Outputs
(Programmable)

Fig. 2.3. PAL conceptual logic diagram: a programmable

AND-array followed by a fixed OR-array.

PALs suffer from the limitation of restricting the number of AND gates which can

be "Ored" together in each output [9]. Even fairly complex PALs have only seven or

eight gates per output. So PAL- type devices work best for applications requiring sparse

usage of the AND array and lunited use of the (fixed) OR array. They are also best when

a large number of inputs are requked but there is more commonality between the outputs

[8]. Another drawback is that PAL devices are quite inefficient in the use of on-chip

logic. Unused product terms connected to an output sum term are wasted, and cannot be

used elsewhere on the chip. This is true even if additional product terms are needed by

another sum term. If more product terms are needed, a sum term has to be routed back to

11
the AND array and used as an input to another product term, wasting one output.

Additional logic delays are induced, since the logic has to propagate through two

additional levels of logic and also through the input output buffers before re-entering the

AND-array [4].

2.1.1.4. Programmable Macro Logic (PML)

PMLs is a family of PLD devices involving the use of a single NAND or NOR

array in conjunction with a central programmable logic implementation, in addition to

connections to input and output macros [3]. This was introduced by Signetics

Corporation in an attempt to overcome the two-level AND-OR bottleneck and provide the

user with a higher level of logic transformation to implement combination logic in sum-of-

products (SOP) form.

In PAL-type devices, the fixed inputs to the OR array confine their architectures to

a composite AND-OR, AND-OR-REGISTER logic defining independent I/O patiis

through the chip. This causes duplication of common product terms and waste of unused

AND gates, thus resulting in waste of chip resources. Further, in the PAL architecture

every macro is hardwired to an OR gate. This results m resources being partitioned and

committed to different pins on the device. If only a part of the resources is used, the

unused portion is wasted. However in PML the macros are independent of all other

resources. In addition, resources in the NAND array are shared by all macros. This

permits more efficient use of the NAND terms [3].

12
 The basic structure of the PML NAND array is shown in Figure 2.4. Each vertical

line represents the inputs of a NAND term; the solid horizontal lines represent driving

lines. The outputs of the NAND array are connected to other macros such as output

macros or process macros (i.e., flip-flop, counters, etc.). Thus, PML architecture does

not waste gates and chip resources as much as FPLA or PAL devices.

N X M NAND Array

-Do

Fig. 2.4. PML fundamental architecture [3].

The PML family uses the bipolar technology wherein the NAND gates provide the

fastest propagation times. However one of the major drawbacks of this technology is the

large power consimiption. This led to the fall of PML devices as, designs in CMOS

technology became more popular as they consume much lesser power than those in

bipolar technology.

13
2.1.1.5. Sequential PLDs

The PLDs discussed so far have all been combinatorial devices. State machine

applications need memory devices along with the input output logic to remember the past

history of inputs (Fig. 2.5).

FEEDBACK

AND OR ARRAY
^ ^ ^
Input Output

INPUT BLOCK OUTPUT BLOCK

(containing latches and (containing output
other programmable controls, flip-flops, etc.)
input options.)

Fig. 2.5. General architecture of a sequential PLD

ASPLDs (Application Specific PLDs) are becoming increasingly popular compared

to general-purpose PLDs for state machme applications due to the more efficient use of

sihcon area. The state machine oriented PLDs vary considerably in their architectures, and

support a range of state machine complexities. The simplest sequential PLD is called a

registered PAL/PAL or programmable logic sequencer [9,5]. Fig. 2.6 shows the block

diagram of a registered PLA.

PLA Edge- PLA

(AND-OR Triggered

Inputs •N array)
> flip-flops
(JK or D)
S (AND-OR
array) ; ^ Outputs

Fig. 2.6. Block Diagram of a programmable logic sequencer or registered PLA

14
 In this class of device, each output is loaded into a D- type flip-flop on an active

clock-edge; the registered output being fed back internally to the AND array. The

registered PALs can be used to implement simple state machines. These simple registered

PALs are however limited by the number of AND gates available for each output.

Fig. 2.7 gives the circuit diagram of a registered PAL.

Functional Diagram

INPUTS (0-31)
Lh>
1131419 1t17li1l JC112221 ]41S2(]r n » ] 0 1 1

O I I J 4147 I tlOII 1>ni41S 1I171(1« 2021222] 24292(27 2(2M0]1

Fig. 2.7. Simple Registered PAL-circuit diagram [23]

15
 Complex designs however requke a large number of gates and more sophisticated

architectures. To contain a high density design in a single device, CPLDs (Complex

Programmable Array Devices) or FPGAs (Field Programmable Gate Arrays) can be used.

CPLDs comprise a single chip with multiple PALs that interconnect on chip by a fast

switching matrix. FPGAs comprise universal logic elements in an interconnection

framework that often resembles a grid. CPLDs are faster than FPGAs which have more

density. CPLDs have a better performance for large state-machines in which propagation

time is of importance [10]. The CPLDs have more predictable timing than FPGAs

though they are less dense than FPGAs. However with FPGAs, the devices' large fan-

outsfromone logic cell to another can cause long delays. The major liability of higher

density CPLDs has been power dissipation. Generally, CPLDs above 15k gates run at a

power disadvantage relative to FPGAs, gate arrays, or discrete solutions [22].

2.1.2 Gate Arrays

Gate arrays, devices that contain a "sea of gates" [4], are becoming increasingly

popular. The underlying concept, on which all gate arrays are foimded, is of a chip

containing a regular matrix of logic gates or components which is preprocessed up to the

final stages of metal layer patterning [18].

The individual gates or components can be connected together in a unique way to

reaUze any function, often with only a single masking step. The final layers on a gate array

provide the interconnect wuing for the gates, thereby defining the logic functions to be

implemented by the array. Fig.2.8 shows one type of gate array organization.

16
 D D a D D D

ILJ D DD
Cell n m
1 1
D
D D n DD D
D D,
u° DD'-»
DD
D
D
Interconnection ^
Highway D D

Fig. 2.8. Block-cell organization of gate arrays

Gate arrays can accommodate virtually any purely digital function on a chip.

However the architecture of these devices does not permit very efficient use of the chips'

gates because in this approach, not all the array cells are used. The inefficient use of the

gates typically results in a significant amoimt of "wasted" silicon real-estate on a gate

array.

2.1.3. Cell-Based systems

Standard-cell devices, like gate arrays are semicustom devices, but are not

prefabricated. This technique requires the production of a full mask set, typically needing

as many masks as a full custom design. It exploits the hierarchy inherent in all logic

systems by partitioning the logic into functional blocks or cells. The cells themselves are

custom-designed and held in a cell library. For a given design appropriate cells are

selected from the library and placed in rows across the chip. Sufficient space is left

between the rows to allow for interconnections between cells. Fig. 2.9 is an example of a

typical standard cell layout

17
 In addition to the building block advantage offered by the standard-cell devices, a

second feature that is also notable is the time consumed to lay out chips. The automatic

placement and routing packages for standard cell ICs are capable of laying out chips

containing several hundred with 100% efficiency and consume relatively small amounts of

CPU time in the process [18].

• D n D D D
D CeU Row 1 =T] D

D Interconnect Qiannel
D
rj= CeU Row 2 =
D 11= CeU Row 3 =j1 '-'
Interconnect Channel
D D
7= CeU Row4 =
D - CeU Row 5 -| D
Interconnect Channel
D CeU Row 6 =
a
• D a D D [3

Fig. 2.9. Organization of a Standard Cell IC.

Further each cell in the cell library is a separate, distinct circuit, efficiently designed

using only the components required to implement the particular cell function. Each cell

then acts as a separate, standard SSI, MSI, or LSI device (without separate bonding

pads), having the high circuit density common to these devices. Because of this, standard-

cell devices do not contain as many unused gates, thereby maintaining very efficient use of

sihcon area. However routing takes up a large amount of siUcon area on the chip which

varies with the complexity of the design.

2.2. Choice of Technique

In order to make a choice of which implementation alternative is the best to use,

the designer must consider issues like device architectures, circuit board space.

18
development time, cost, design ease and flexibility. When considering the effective cost of

the various alternatives, the designer must take into account the total development costs

and the production cost.

The SSI/MSI technique is an easy straightforward method, which is its main

attraction to designers. It is flexible in that it allows most of tiie logic functions to be

implemented. The development cost here is relatively more since the different SSI/MSI

devices have to be procured separately and wu-ed up. This results in increased cost per

gate. The development time is relatively less.

However, there are quite a few drawbacks in this method. Though tiiis is a

straightforward method, error checking and tracing back becomes very difficult. So

debugging the system is cumbersome. Further routing may be a problem due to the large

number of interconnections that have to be made. This is a very inefficient method as far

as ckcuit board space is concerned. Nevertheless, this technique is still used for small

uncompUcated designs, for low to medium volume appHcations.

The gate array technique has been steadily increasing in popularity. This method

can incorporate any digital function. With CAD tools available, fault detection and

correction have become relatively easy. Because the gate interconnections must be

defined, gate array designs involve nonrecurring engineering (NRE) charges like mask

tooling charges and charges for computer-aided design. The time to design mainly

depends on the apphcation itself. With a well proven design, translation to gate array

logic and simulation can be completed in a matter of weeks, if the right tools are available.

This technique is better employed for high density designs as a single chip can contain

19
many more gates than a PLD can. Also because of the sizable NRE (non-recurring

engineering) charges, gate arrays are better suited for medium to high volume production.

However, the main problem with this method is that though it may seem to have a

large number of gates in a chip, a design requuing 2000 "real" gates would most likely

require a gate array with approximately 5000 gates; since the architecture of these devices

do not permit very efficient use of chips'gates. Typical gate efficiency has been 40%,

although newer gate array designs claim over 75% gate usage [4]. Translated into dollars

and cents, the inefficient use of gates typically results in a significant amount of "wasted"

silicon real-estate on a gate array— a cost that must be reflected and absorbed in the selling

price of the devices. Nonetheless, gate arrays are an attractive alternative to using

SSI/MSI technique.

Programmable Logic Devices are one of the most popular techniques now on the

market. Their attractiveness to designers stems from the versatility to perform most of the

functions, programmabihty and low development cost. The non-recurring engineering

charges are very small once the one-time costs for development of software and hardware

have been spent. Fault correction also is easy. There is considerable circuit board space

saving compared to SSI/MSI technique.

However, there are still some drawbacks. Many appUcations do not need the

functional versatiUty to the extent provided by a PLD. But designers tend to turn to this

technique due to the small development time and its advantages over the gate array and

SSI/MSI technique. Functional versatility results in the use of a larger sihcon area and

consequentiy more circuit board space is occupied.

20
 For state machine applications the most commonly used device is the PLD. The

PLA/PAL matrix provides all different combinations of a logic function. This provides the

device with the required versatility. However many of the state machine applications do

not make full use of the functionality provided. This is true specially in the case of small

applications involving eight to sixteen states. This results in unnecessary waste of silicon

area. An alternative implementation technique that fits between PLDs and SSI/MSI

integration could be advantageous.

Table 2.1 shows a comparison between the different techniques. Ordering (1 best,

5 worst) is done on the basis of implementing a total logic system in siUcon using one

particular technique [18].

Table 2.1. Comparison of the various implementation alternatives

SSI/MSI Gate-array Cell-based PLDs Full-custom

Development time 1 3 4 2 5

Development cost 1 3 4 2 5

Flexibility for design 1 2 1 1 1

Ease of debugging 2 5 3 3 4

Unit cost in production 5 3 2 4 1

Power consumption 5 3 2 4 1

Silicon area efficiency 5 4 2 3 1

Cell-based systems are emerging as a feasible alternative to other existing systems

in some cases. This can be attributed to the ease with which large systems can be designed

quickly due to the presence of a cell library. The costs of development however are much

higher than that of a gate array because of the complete set of masks that need to be

21
developed to manufacture the dies. However, building-block advantage offered by the

cell-based devices, result in efficient die usage. So an entire chip can have all the gates in

it to be "real gates" unlike the gate-array method. This provides for a more efficient use

of silicon area. Since die size is proportional to device cost (especially for large volumes),

standard cell devices generally cost less than gate arrays, for large volumes. Design time

compares favorably with gate arrays even with non-automated layout systems, but with

automated systems the design times are much shorter.

This thesis uses a ceU-based technique to build a small general state machine,

making use of the standard cells available in a cell Ubrary. A comparison is then attempted

between the proposed design and a PLD, by implementing an example with the proposed

design and with the smallest available PLD. A comparison is made with the SSI/MSI

technique also by implementing the same example with SSI/MSI gates.

22
 CHAPTER ni

THE DESIGN

3.1. Design Implementation using standard building blocks

Standard cells like multiplexers, decoders, registers, counters are easily available in

most cell hbraries, whereas that is not true for PLA/PAL. Small state machines with few

states can be easily designed using simple building blocks available in most cell libraries.

Also each of these cells being separate distinct circuits, are optimized to implement the

particular cell function and make very efficient use of the silicon area. This may result in a

device which is more economic silicon areawise. The present work uses the cell-based

technique to design a small, general-purpose sequential state machine.

A multiplexer (MUX) is a combination circuit that is one of the most widely used

standard circuits in digital design. Each input variable is controlled by a set of select

inputs. The schematic model of the general 2° to 1 MUX is shown in Figure 3.1.
Input select bnes

SoS >l SB-I

/
I/Po
I/P2

Input Y
Output
lines •^

Y/

>
Enable s
/-
or b
Strobe k

Fig. 3.1. General schematic of a 2" to 1 multiplexer [1]

23
The output is given by:

Output = mo(IPo) + mi(IPi) + m2(IP2) + ... + mj(IPj) + ... + m2°''(IP2°"')

where mj is the general MINTERM made up from the select inputs (So, Si,...S„.i) and

Ipj is the variable or expression connected to the jth input. This shows that a general

canonical SOP expression can be generated using a multiplexer. A technique can

therefore be derived whereby the PLA/PAL which does the same work can be replaced by

multiplexers.

Registers and counters are sequential devices composed of combination logic with

flip-flops designed to perform shifting and counting operations. Since counting and

shifting operations are closely allied to the process of state to state transition, and since

the state-to-state transition process must be synthesized for every system sequence using

plain flip-flops, we can utihze the counters and registers efficientiy to perform the same

job as flip-flops. This requires a proper design procedure which includes selecting the

right device for the job.

3.2. General State Machine Architecture

3.2.1. Input Forming Logic

A state machine is an organized collection of combinational logic functions, time

delays, and fedback inputs [2]. As stated before the input forming logic of the state

machine can be implemented in a variety of ways. A multiplexer (MUX) is one such

combination device which can be used for this purpose. One of the main reasons for

24
considering using a MUX for logic is to attempt to minimize the area occupied and

decrease the design time. Furthermore, no restrictions are placed on state assignments for

circuit minimization, allowing moreflexibilityin the overall design.

A general system configuration is developed using a MSI multiplexer. The general

arrangement of the direct-addressed MUX system is shown below in Fig. 3.2. Though the

diagram shows the input forming logic to contain gates and MUXs, the gates often are

very simple or not required at all.

Next State Decoder Next state

variables
/ \ Present state variables

Mux
-1/
Tt Output
Decoder
Inputs ''v Gates State
or ^ O utputs
1/^ iMux flip-
Output
flops
TT" forming
logic
-^ Mux
TTT

Fig. 3.2. Architecture of the direct addressed multiplexer configuration.

The multiplexers as observed are directly used to decode the present state of the

machine and select the proper inputs which determine the next state of the machine. So

the next state is in fact dependent on both the outside world inputs and the present state of

the machine. The advantage of using a multiplexer to do the combinational logic is that a

large number of outside world inputs can be easily accommodated without much

complexity. Further the input forming logic can be kept to a minimum too. However a

MUX is required for each stateflip-flopand each MUX must have n select lines, where n

25
is the number of state flip-flops. A direct addressed MUX design requires n-2": 1 MUXs

to design the input forming logic. This type of design uses D flip-flops, m general.

The implementation of the direct addressed multiplexer configuration is as follows:

(i) The problem is defined.

(ii) The MDS (Mnemonic Documented State Diagram) is drawn.

(iii) State assignments are made.

(iv) The next state map of the next state decoder is drawn in the form of variable entered
maps (VEMs).

(v) Connections to the multiplexer are made.

Consider an example with two state variables and the state map and the next state

maps as shown in Fig 3.3. Two multiplexers will be needed here as there are two state

variables. The state variables A and B are fed to each of the multiplexers' control inputs.

The variable present in each of the boxes is fed as inputs to the appropriate multiplexers.

Fig. 3.4 shows the input forming logic diagram for this example.

1 1 0 0
a c

b d 0 0 inp 1 inp 2

State Map D, DB

Fig. 3.3. The Next State maps for multiplexer implementation

0 1 0 I in p 2 0 n p 1 0
1 1 1 1 1 1 1 1
A 3 2 1 0 A 3 2 1 0

r B M U X 0 B M U X 1

L
C Ik
1 >''* l_ > •^•
1 1 1 1
B B /
A A /

Fig. 3.4. Input Forming Logic using MUXs

26
3.2.2. Memory element

A flip-flop is the basic memory element. Every flip-flop has two possible states

"set" or "reset". FUp-flops are used to build sequential machines like counters and shift-

registers. Traditionally state machine designs use plain flip-flops to perform the state-to-

state transitions. However counters and registers contain flip-flops and are already

designed to perform a sequential task. A state machine can be designed around these

sequential devices.

Counters are designed to perform the function of counting. If the state assignment

is carried out appropriately, counters can be used to function as the memory elements.

Nevertheless, the shift-register is more flexible for design and therefore is used here for the

present state machine implementation.

3.2.3. Output Forming Logic

The combinational circuitry that the state flip-flops drive to produce the output

signals is called the output-forming logic. The most common and easy method to

implement the output forming logic is the use of decoders.

The most important problem that generally needs to be considered here is the

output gUtch problem. Glitches are very narrow pulses, often havmg the width of a few

nanoseconds, that occur during the switching variables [5]. The output forming logic is

driven by the state flip-flops. Although the state changing clock transition is apphed

simultaneously to all state flip-flops, due to differences in clock-to-output delay times, the

27
flip-flop outputs will not change at exactiy the same time. Since these pulses drive the

output gates or decoders, the possibility of hazards must be considered.

A component that is added to eliminate the output ghtches is an output holding

register. One version of this scheme is shown in Fig. 3.5.

> Output
Input

Fig. 3.5. Use of output holding register.

In the holding register, one flip-flop is required for each output of the system. The

outputs from the decoder are presented to corresponding inputs of the holding register.

This information can be set into the holding register near the state beginning or at the

delayed state beginning. If it is done at the state beginning, the transition that loads the

holdmg register must be delayed relative to the state-changing transition. This delay must

exceed the clock-to-output delay of the state flip-flop plus the propagation delay of the

output gates. If the information is loaded into the holding register at the delayed state

begmning, the half period of the clock must exceed the clock-to-output delay of the

output gates. This requirement can be easily satisfied most of the time.

28
 For conditional outputs, the data changes at the midpoint of the state time. Thus

the data line must be allowed to settie before loading the holding register. In this case

inverter between the clock signal and holding register will serve as a delaying inverter too.

3.3. The Design Process

The first step in the top down design methodology is to define the problem and get

the specifications. For the present problem, the idea is to build a device which will

function as a general state machine. This has to be implemented using the standard

building blocks; the memory element being implemented by a sequential building block.

The devices that are used in this design are multiplexers, shift-registers, decoders and a

couple of gates.

A basic four-bit edge-triggered synchronous SIPO (Serial-in-parallel-out), PIPO

(Parallel-in-parallel-out), PISO (Parallel-in- Serial-out), SISO (Serial-in-serial-out), shift-

register is chosen for the task. This kind of device has been selected because of its edge-

triggered synchronous LOAD/SHUT operations with asynchronous RESET features

which prevents it from having the 1 's and O's catching problem. As the shift-register is

bemg used to perform the memory function, some design and state assignment constraints

have to be followed in order to make optimum use of the basic shifting property of this

device. A general model of a sequential state machine utilizing a shift register as memory

element is shown in Fig. 3.6.

29
 CLR M ulti-mode
shift register
CLK
3^—
Data
Inputs Next Inputs
-7 State
Control * Output Outputs
Serial « Decoder
Logic
Inputs

Mode
Control

Fig. 3.6. General Model of a sequential state machine using a shift register

Some of the decisions that have to be made while using a multi-mode shift register

as shown in Fig.3.6. are:

(i) Should a 0 be shifted left?

(ii) Should a 1 be shifted left?

(iii) Should a 0 be shifted right?

(iv) Should a 1 be shifted right?

(v) Should a parallel load be done?

To simplify the design, right-shifts are not allowed and only left-shifts and parallel loading

are allowed.

A block diagram of a four bit shift register is shown below in Fig.3.7.

Fig. 3.7. Block diagram of a general 4-bit shift register.

30
 Table 3.1 Function Table

Clock Reset SI S2 DR D0-D3 DL Operation Q0-Q3

0 * * * Reset 0-0
1 0 0 * Load D0-D3 D0-D3
1 0 1 * Shift Right DR-Q2N-I
1 1 0 * Shift Left Q1N-I-DL
1 1 1 * Hold No Change

SI and S2 determine the four different modes of the register. Table 3.1 gives the four

modes. DR and DL are the serial right and serial left inputs. When the register is in shift

right mode, tiie serial data input is accepted through DR. When the register is m shift left

mode, the serial data input is accepted through DL. The register being used is negative

edgetriggered, i.e., the outputs occur at the falling edge of the clock. The reset input is

used to clear the flip-flops at the start. The four data inputs are used for PIPO function.

The present design is that of a general state machine and is not confined to one

particular application. Hence the size of the state machine needs to be decided first. It has

been decided to implement a three bit sequential state machine. Therefore, the MDS

diagram (Mnemonic Documented State diagram) in the hmiting case will have eight states.

The register being used has four bits, out of which only three are needed. The first bit can

therefore be ignored. The register has been lunited to perform left shifts and parallel loads

only. Hence the significant bits for tiiis will be D1-D3 at the input and Q1-Q3 at the

output.

The shift register functions are controlled by the mode bits S1 and S2. The inputs

to these two bits depend on the state assignment and the outside world inputs.

31
Combinational logic is therefore needed for SI and S2. Two 8:1 multiplexers are used to

do the job of the combinational logic. The outside world inputs are fed by the user to the

inputs of the mutiplexer. The state variables which are the outputs of the shift register are

fed to the select control inputs of the multiplexer. Thus the outside world inputs need to

be mapped to the inputs of the multiplexer. This is done by drawing the action map and

the mode control maps.

A state map shows the states in the form of a table. It shows the sequence of

states, i.e., which state comes after which. Then an action map is plotted with the action

mnemonics, providing a visual display of what actions are called for in each state for the

next state to be generated. This map along with the mode control truth-table (S1, S2

truth-table) are used to plot the mode control maps. Here the user must enter into the S1

and S2 maps the proper code in order that the proper operation is specified for each state.

Though the mode control maps are plotted directiy from the MDS diagram, the more

complex conditional shifts and load entries must be properly taken care of

The modes through which the register is made to sequence is dependent on the

states and the external world inputs. Based on the state assignment, either data is fed in

by shifting one variable to the left or else data is loaded in parallel through the parallel data

inputs.

In order to facilitate parallel loading of data into the register, each of the parallel

data inputs of the register is fed to a multiplexer. So there are three 8:1 multiplexers to

enable data to be programmed into the register. Each of these multiplexers are controlled

32
by the 3-bit state variable output from the shift-register. Depending on the present state, a

1 or a 0 is programmed into the multiplexers to attain the next state.

A multiplexer is connected through a two-input OR gate to the serial left input DL.

Depending on whether a 0 or a 1 needs to be shifted left according to the given state

assignment to attain the next state, the appropriate inputs are fed into the multiplexer.

The multiplexer select-controls are connected to the 3-bit state variable output from the

register. The OR gate enables the machine to execute applications, wherein one state

branches to three states based on three different input conditions. The outside world input

which controls one of this branching is fed to the input of the OR gate. A detailed circuit

diagram of the design is shown in Fig. 3.8.

AppUcations requiring small state machines with a maximum of eight states can use

the present machine. The proposed state machine design has been tested by implementing

one of the classic examples, the pop machine problem. Simulations have been run on

PSpice. The layout has been done m MAGIC in 3uCM0SN technology [20,21]. The

CMOSN standard cell Ubrary has been utilized. The data sheets of the standard cells used

are detailed in Appendix A. The design has been successfully extracted into Spice. The

next chapter deals with the example chosen and its implementation using the proposed

design.

33
l\JiL_

IN8
IN7 8:1
INS1_8
1N8 IN6
INS1_7
IN7 INS MUX
INSJL6_ IN6 IN4
INSl,*! INS *='
IN3 ^
INiiUL IN4 MUX
IXiiO. IN2
1N3
IXSJ, IN2 INI
INSIJ INI CB A
SI
S2

ii HI SL
SR 3:8
INS
DECODER
IN7 8:1
4-BIT DO OUTl
IN6
D3 Dl OUT2
INS Q3 C2
MUX SHIFT
IN4 D2 OUT3
D2 Q2 CI
IN3 D3 OUT4
Dl Ql CO
4N2 REGISTER D4 OUTS
l\ST 8 QO
IN8 •INI DO DS OUT6
I\'.S9 7 C B A
IN7 1)6 0UT7
l \ S 7 (S
8:1 T
IN6 D7 OUT8
IVSJ? 5
'N5 MUX
I\*;T 4 IN8
IN4 ENABLE
I \ S ? T. 8:1
IN2 IN7 CLK TT
\\K-> ->

l\S? I
IN2
INI
IN6 MUX
INS
A- RST
—p—

r ,R A IN4
1N3
IN2
INI
r. R A

INS
IN7
IN6
INS
8:1
1N4
IN3 MUX
IN2
INI

-t .R A

Fig. 3.8. Architecture of a three-bit sequential state machine using standard cells

34
 CHAPTER IV

DESIGN IMPLEMENTATION

The classic pop machine problem [1], has been implemented using the proposed

design. The preUminary specifications of this problem is that: A digital control system

should be developed such that it wUl direct the control of the coin receiver, coin changer,

and pop drop mechanics providing a system capable of automaticaUy dispensing soda pop

at 300 per can. The system should also make proper change retrieval for coin sequences

of nickels, dimes, quarters and half-dollars. A block diagram of the requked system is

shown in Fig. 4.1.

sum = 30(i drop pop

sum > 300 retum nickel

Pop Drop Machine clear accumulator
sum < 300 "w
System Controller
decrement accumu
pop drop rdy

changer rdy

iL
coin present

Fig. 4.1. General block diagram of the pop drop controUer

The procedure to be followed while using the proposed design is described in the

foUowing text. Once the specifications of the application has been defined, the MDS

diagram is drawn. For the problem under consideration the system inputs are, coin

present (CP), coin not present (CP/), sum less than 300, sum equal to 300, sum greater

35
than 300, pop drop ready (PDR), changer ready (CR). The outputs are retum nickel

(RN), drop pop (DP), clear accumulator (CA), decrement accumulator (DA).

The MDS diagram is shown below in Fig. 4.2.

QBQCQD

(BU)

DA-Nr

Fig. 4.2. MDS diagram with the shift register sequence state assignment

The state assignment is shown in the MDS diagram. Depending on the next state either a

left-shift or parallel loading is performed on the present state. Shift left has been indicated

by SL (1 or 0), unconditional parallel loading by BU (branch unconditional) and

conditional paraUel loading by BC (branch conditional).

The state map and action map is plotted as shown below in Fig.4.3.

QBQ( QBQ(
00 01 11 10 00 01 11 10
QD QD

0 a 0 f g 0 SLIC 0 BC BU

SL1C+
b c d e 1 SLIC SLOC+ BC BU
1
RC

State Map Action Map

(a) (b)
Fig. 4.3. The State Map and Action Map for the pop machine.

36
 Based on these maps and the mode-control truth table (Table 4.1), the mode

control maps for S1 and S2 are drawn up (Fig. 4.4).

Table 4.1. Mode Control Truth Table

SI 32 Action

0 0 Hold
0 1 SR
1 0 SL
1 1 Branch

The user enters into SI and S2 maps the operations specified for each state. Though these

maps are plotted directly from the MDS diagram, whenever there is the situation of

complex conditional shifts care must be taken to see that proper entry is made. For

example observe the entry for the SI and S2 maps in state c. The complex operation of

SLlC-f-SLOC+BC has been resolved carefuUy.

QBQC QBQC
00 01 11 10 00 01 11 10
QD QD ^

0 CP 0 CR 1 0 0 0 CR 1

sum <
CP/ 1 PDR 1 1 0 300 PDR 1

SI Map S2Map

Fig. 4.4. The MODE CONTROL MAPS for the pop machine

Lastiy the input data maps for the serial and parallel data are plotted (Figs. 4.5, 4.6). One

for serial left data input and three for the parallel inputs. These are drawn based on the

Action map.

37
 QBQC
GO 01 11 10
QD

0 1 0 0 0

1 sum
0 0
= 300

Fig. 4.5. The SERIAL LEFT DATA INPUT MAP for the pop
machine.

QBQC QBQC
QBQC
00 01 11 10 00 01 11 10 00 01 11 10
QD QD
QD
0 0 1 0 0 0 0 1
0 0 0

0 0 1 0 0 0 1 0

Fig. 4.6. The Parallel Input Data Maps for the pop machine.

Using the above maps connections are made to implement the pop machine problem using

the designed circuit. The pop machine implementation using this new approach has been

executed in PSpice. The sunulation waveforms are included in the next chapter.

The same example has also been implemented using the traditional SSI/MSI gates.

D flip-flops are used as memory elements. The input forming logic and the output forming

logic is performed using SSI gates. The state diagram is the same as before. The state

map is indicated below along with the next state decoder map.

Q.Qb
00 01 11 10

a 0 d f
0

b c e g

Fig. 4.7. State Map

38
 Q.Qb Q.Qb Q.Qb
00 01 11 10 \ 00 01 11 10 00 01 11
Qc
0 1 1 Qc^ PDR
0 0 0 0 1 0 CP 0 CR
0
1 0 =+> 0 0 1 CP/ = 0 1 1 0 0 1

Fig. 4.8. The NEXT STATE or D maps for the pop machine.

From the above maps, we get the following equations after simpUfication of the K-maps.

Da=(A/)(B)(= + >) + (A)(C/)

Db = (A/) (B) (=) + (B/) (C) (CP/) + (B) (C/) + (A) (B/) (C)

Dc = (A/) (B/) (CP) + (B) (C/) (PDR) + (A) (B/) (CR) + (B/) (C).

The system outputs are obtained very easily from the outputs of the D-flip-flops. They

can be stated as:

DA = (A) (B/) (C)

RN = (A) (B/) (C/)

CA = (A) (B) (C)

DP = (A) (B) (C/).

This implementation of the above problem has been simulated in PSpice and the

layout has been done in MAGIC in 3u CMOSN technology. The next chapter gives a

comparison of the two implementation techniques.

39
 CHAPTER V

RESULTS AND CONCLUSIONS

5.1. Results

A general three-bit sequential state machine utilizing a multi-mode shift register for

memory has been successfully implemented using the ceU-based implementation technique.

The machine has been laid out in MAGIC layout tool in 3u CMOSN technology. The

layout has been extracted into Spice. The classic pop machine problem has been

unplemented using this design and simulations have been run on PSpice. The resultant

waveforms are included at the end of this chapter (Fig. 5.1, 5.2, 5.3, 5.4).

Full-custom implementation of the pop machine has also been carried out. The

circuit has been laid out in MAGIC using 3u CMOSN technology and has been extracted

mto Spice. The example was also implemented using a PLD. This was achieved by

simulating the circuit in PLSyn and choosing the smallest PLD avaUable to incorporate the

design. The PLSyn results are also included at the end of this chapter.

5.1.1. Comparison

Layout comparisons of the full-custom technique and cell-based technique show

that the total area occupied by the fuU-custom implementation is 1223 x 1486 and that

occupied by the proposed technique is 1575 x 1486. The full-custom method utilizes a

smaller amount of sUicon area than the proposed method. However the proposed

technique is only about 30% larger than the custom design. The reason for this is that

40
tiiere are more cell interconnections in the fuU-custom method. Making a large number of

mterconnects is a cumbersome task for the designer and results in increased development

trnie as against the proposed method. The proposed method does not requke Karnaugh

map minimization which needs to be done for fuU-custom technique. Further the

proposed design is a general purpose state machine which can implement otiier problems

too, and pop machine is just one such example. So the difference in area is not very

significant. Table 5.1 gives a device count comparison between the two methods.

Table 5.1. Device count comparison

Custom-Technique Proposed Technique

3-input AND gates - 11 8:1 multiplexers - 6

2-input AND gates - 3 4-bit shift-register - 1
2-input OR gates-2 2-input or gates-1
4-input OR gates -2 3:8 decoder-1
D-flip-flop-3

SSI/MSI implementation of the example involves using a larger amount of circuit

board area due to the large chip count as against one single chip in the above two

methods.

As observed from Table 5.2, SSI/MSI technique employs eight chips to do the

same task that is done using one chip designed with the proposed technique. So the

SSI/MSI method occupies large ckcuit board space, and needs lot of wking.

41
 Table 5.2. Chip count for the SSI/MSI implementation of the pop machme problem

Logic device # of devices Chip name # of logic devices in Chip

required the chip count
3-input AND 11 74LS11 3 4
2-input AND 3 74LS08 4 1
2-input OR 2 74LS32 4 1
4-input OR 2 74LS802 3 1
D-fUp-flop (edge 3 74LS175 4 1
triggered)

A comparison of the proposed method with a PLD would be quite interesting. An

architecture comparison shows that the next state decoding function which is done by the

PLA/PAL in a PLD is done by programmable multiplexers in the proposed method. The

function of memory is carried out by a multi-mode shift register. The smaUest PLD

capable of implementing the given problem is a eight-bit PLD.

The EP310DC was recommended by the software program PLSyn to be the best

fit for this simple example. Appendix B contains the data sheets of this PLD. This PLD

contains 8 macrocells with up to 18 inputs and 8 outputs. Each macrocell basically

contains eight AND gates, one OR gate and one D flip-flop. The output can be

configured to be combinatorial or registered.

It is observed that for simple problems using the aforesaid PLD definitely seems to

be an overkiU. This is because for smaU applications involving 8-16 states only three to

four flip-flops are needed, however because of the PLD architecture eight macrocells are

needed with four of them being used to perform the output logic. This results in a waste

of four flip-flops.

42
 A comparison of the sum and product terms shows that the present design has 24

sum terms and 6 product terms as against 8 sum terms and 18 product terms. This

indicates the generality of the present design. Also in the present design a 3:8 decoder is

used to perform the output logic as against the matrix logic employed by the PLD. The

decoder seems to occupy a smaUer space than that occupied by the output logic matrix in

a PLD.

5.2. Conclusions

From the comparison, it is seen that the proposed technique wiU work well for

smaU appUcations involving 8-16 states. This is definitely a much better unplementation

than an SSI/MSI type of implementation. The area comparison between the full-custom

implementation and the proposed design, which is a general purpose state machine shows

that there is not a great difference between the areas occupied by the two designs.

5.2.1. Advantages

Finally, the advantages of the present design can be stated as:

• The proposed machine can be implemented in a single chip, with all pins being brought

out. Though this would result in a bigger die size, the main advantage is that state

machine appUcations can be convenientiy executed by connecting some of the

programmable inputs to the power rails. This means that no tedious programming is

requu-ed as is necessary with a PLD. Also changes can be easily made by changmg a

small number of interconnects instead of replacing the chip.

43
• Instead of bringing all the pins out, the proposed machine can, have all the cell

interconnections made on the wafer up to thefinalmask containing the metal

connections to the power rails, for the programmable inputs.

• At the cost of reduced versatility, the programmable multiplexers can be replaced by

SSI type gates. This wiU decrease the number of input combinations that can be

executed however, this will occupy less siUcon space than that with multiplexers.

So, relatively for simple state machines this implement approach may be an

attractive alternative to traditional PLDs.

44
 s.ou
SEL>>; / clock

a U1(Uclk)
5.0U-r 1 o-

cpr
OU-^o-
a U1(US11)
5 . OU T°
cprbar
OU o
a U1(US12)
1.0uU
chanrdy
LQ-

-1.0uU
a U(66)
5.0U

TL
popdrray
OU-^o-
o U(68)
5.0U
sumeq
OU-ho-
10U-r
outdp
-^o

-10U
o U(33)
5 . OU -r

outrn
OU-^a-
a U(34)
5.0U-r-
outca

-5.0U
a U(35)
5.0U-r
outda
a-

SEL» J
-5.0U + - 1 1
r r
Qs 1.0US 2.0US 3.0US ii.Ous 5.

Fig. 5.1. The output waveforms for the pop machine problem.

45
 S.OU-r--
I

SEL»; ciock
OU-^o-
a U1(Ucll<)
6 . 0 U C5-

DL
-5.0U h

10U
Co- rcgini ^"

-10U
a U(46)
5.0U
U.0-
reginZ

-5.0U-^
a U(21)
s.m
regin3
L.O-

-S.OU-^
o U(12)
10U
regouti
L-o-
y^
•10U
a U(9)
1QU
regout2 />-
\-o-

-10U
a U(7)
10U

regout3!
SEL» I
-10U + - --r
OS 1.0US 2.0US 3.0US li.Ous 5.1
a U(6)

Fig.5.2. The shift register serial input and output waveforms.

46
 5.0U TO—

SEL»; dock-
OU-^o-
o U1(Uclk)

10U

SI \ r
-10U
a U(43)
S.OU-r
S2

- 5 . OU
a U(30)

10U
rcgini _J^
[_o-
I
-10U
a U(l»6)
s.ou regin2

- 5 . OU
o U(21)
S.OU
regin3
l-o.

- 5 . OU
a U(12)
10U
regoutl
y^
-10U
a U(9)
10U
regoutZ ja-
l-D-

-10U
° U(7)
10U
__jr regout3!
sEL»;
-10U + 1

OS 1.0US 2.eus 3.0US ii.Ous 5.1

a U(6)

Fig. 5.3. The shift register parallel input and output waveforms.

47
 S.OU-r--

SEL» i clock
OU^a-
a U1(Uclk)

1QU

SI \—r
-10U-^
a U(l43)
. U U -r

S2
-o-

- S . OU
a U(30)

6 . 0 U cs

DL
-S.OU h

10U
reginl -J"
i-a-

-10U
a U(U6)
S.OU
reginZ
l-O-

- 5 . OU
a U(21)
S.OU
regin3

-S.OU
a U(12)
10U
regouti
!-a- y^-
-10U
a U(9)
10U
regoutZ ^-
-o^

-10U
o U(7)
10U
Uo- •^ regout3!
SEL»!
-10U +
OS 1.0US 2.0US 3.0US ii.Ous 5.1
a U(6)

Fig. 5.4. The shift register output waveforms.

48
 REFERENCES

1. WiUiam I.Fletcher, An Engineering Approach to Digital Design, 1980, Prentice-HaU,

Englewood Cliffs, NJ.

2. Michael Treseler, Designing State Machine Controllers using Programmable Logic,

1992, Prentice-HaU, Englewood CUffs, NJ.

3. Von L. Burton, The programmable Logic Device Handbook, 1989, TAB Professional
and Reference Books, Blue Ridge Summit, PA.

4. Roger C. Alford, Programmable Logic Designer's Guide, 1989, Howard Sams and
Company, Indianapolis, Indiana.

5. David J. Comer, Digital Logic and State Machine Design, 1995, Saunders College
Publishing, Orlando, FL.

6. Christos A. Papachristou, Debabrata Sarma, "An approach to sequential circuit

construction in LSI programmable arrays," lEE Proceedings, Vol. 130, Pt. E, No. 5,
pp. 159-164, September 1983.

7. Yahiko Kambayashi, "Logic Design of Programmable Logic Arrays," IEEE

Transactions on Computers, Vol. C-28, No. 9, pp.609-617, September 1979.

8. James D. Broesch, Practical Programmable Circuits, 1991, Academic Press, Inc., San
Diego, CA.

9. Geoff Bostock, Programmable Logic Devices-Technology and Applications, 1987,

McGraw-HiU Book Company, New York.

10. John GaUant, "Designing for speed with high performance PLDs," EDN, July 20,
1995.

11. Mcluskey.E.J., "Designing with PLAs," Proceedings of the 13th Asilomar conference
on cu-cuits systems and computers. New York, 1979: IEEE Conference Record, pp.
442-445.

12. De MicheU G., and Sangiovanni-ViecentelU. A., "Multiple Constrained Folding of

Programmble Logic Arrays: Theory and applications," IEEE Transactions on CAD,
Vol. CAD-2,No.3, July 1983.

49
13. Karthikeyan Kannappan, Partition based algorithms for PLA folding. Master's
Thesis, Department of Computer Science, Texas Tech University, Lubbock, Texas,
1989.

14. Abe K.; Omari T, Naraoka M., "A programmable logic array suitable for use in digital
system design laboratories," IEEE Transactions on Education, Vol. 35, No.4,
pp. 338-350.

15. Yun Hong Kim, hi ChU Lim, "Design of high speed dynamic CMOS PLA," Journal of
Korean Institute of Telematics and Electronics, Vol. 28B, No. 11, pp. 8-14.

16. Gupta B., Rajsuman R, "On designing robust testable PLA for path delay faults,"
Conference Record, 23rd Asilomar Conference on Signals, Systems and Computers,
p.2 Vol. xix+1064, 999-1001, Vol.2.

17. Intel, Programmable Logic Databook, 1992, Intel Corporation, Mt.Prospect, IL.

18. HurstS.L., Sage.M.W, Semi-Custom IC Design and VLSI, lEE Digital Electronics
and Computing Series 2, 1983, Peter Peregrinus Ltd., London, UK.

19. D.E. White, Logic Design for Array-Based Circuits, 1992, Academic Press, Inc., San
Diego, CA.

20. Robert N Mayo, Michael H Arnold, Walter S Scott, Don Stark, Gordon T Hamachi,
WRL Research Report-1990 DECWRLILivermore Magic Release, Western Research
Laboratory, Palo Alto, CA.

21. MOSIS, CMOSN Cell Notebook, Release 2.0, MOSIS Service, Marina del Rey, CA.

22. John H. Mayer, "CPLD market to jump to $800 miUion by 2000," Computer Design,
July 1996.

23. Harris, CMOS Digital Data Book, Harris Corporation, 1986, Cathedral Station,
Boston, MA

50
 APPENDDC A

STANDARD CELL DATA SHEETS

51
8:1 MUX W/ ENABLE MUX4
LOGIC SYMBOL INPUT CAPACITANCE (PF)
Signal L2U
INI .22
IN2 .22
IN3 .21
IN4 .20
INS .22
IN6 .22
IN7 .20
IN8 .20
SELl .99
SEL2 .60
SEL3 .39
ENBAR .20
FTHRUl .04

FU NCTIO N T A EILE

ENBAR SELl SEL2 SEL3 INI IN2 IN3 IN4 INS IN6 IN7 INS OUT
0 0 0 0 INI
0 0 0 1 IN2
0 0 1 0 INS
0 0 1 1 IN4
0 1 0 0 * * * * * * * * * INS
0 1 0 1 IN6
0 1 1 0 IN7
0 1 1 1 INS
1 0

LOGIC EQUATIONS

OUT = [(SELl • SEL2 • SEL3 • INI) + (SELl • SEL2 • SEL3 • IN2) + (SELl • SEL2 • SEL3
IN3) + ( 5 1 0 • SEL2 •SEL3 • IN4) + (SELl • SEL2 • SEL3 • INS) + (SELl • SEL2 • SEL3
IN6) + (SELl • SEL2 • SEL3 • INT) + (SELl • SEL2 • SEL3 • IN8)] • ENBAR

SIZE
X: 230x250
1.2^: 138 X ISO
2.0pi: 184 X 200
Revision 2.0A CMOSN CcU Ubrary
8/29/89

52
8:1 MUX W/ ENABLE
MUX4
FUNCTIONAL DIAGRAM

sa2
se.1 p f
{> o—-•
>-l
SELa
o—•
i>n E^B^n

IN8 c > .
{>
hi tsi
IN4 O -
{>
±- «l <

Kl
IN6 O -
> s
K
IN2D-
{>
OLfT
< - ^ i
IN7 O -
i> K
i K
INaO"
i> El
INS
^ ' El
L I K
INI D -
i>-Kl
FTHRUl [3» - ^ FTMRUI
FEED-THRU

CMOSN CcU Ubrary Revision 2.0A

8/29/89

53
 4.INPUT NOR/OR
NRI4
LOGIC S Y M B O L
FUNCTIONAL DIAGRAM
IN1
IN2
IN3 GLTri
IN4 0UT2

INPUT CAPACITANCE (PF) FUNCTION T A B L E

Siflial L2u IN1 IN2 IN3 IN4 0UT1 OUT2
INI .20 0 0 0 0 1 0
IN2 .20 1 * * * 0 1
* 1 * *
IN3 .20 0 1
* * 1 *
IN4 .21 0 1
* * *
1 0 1

LOGIC E Q U A T I O N S

OUTl = INI + IN2 + IN3 + IN4

0UT2 = INI + IN2 + IN3 + IN4

SIZE
X:70x2S0
1.2^1: 42 X ISO
2.0^l: S6 X 200

Revision 2.0A CMOSN CeU Ubrary

8/29/89

54
 2.INPUT NAND/AND (2X DRIVE)
NDI2X:
LOGIC SYMBOL
FUNCTIONAL DIAGRAM

O OLTTI

0UT2

INPUT CAPACITANCE (PF) FUNCTION T A B L E

Signal 1.2^1 INI IN2 OUTl 0UT2
INI .33 0 0 1 0
IN2 .33 0 1 1 0
1 0 1 0
1 1 0 1

LOGIC EQUATIONS

OUTl = INI • IN2

0UT2 = INI • IN2

SIZE
X:4Ox2S0
1.2[i:24x ISO
2.0n: 32 X 200

Revision 2.0A CMOSN CeU Ubrary

8/29/89

55
2-INPUT NOR/OR NRI2
LOGIC SYMBOL FUNCTIONAL DIAGRAM
IN OUT1 OOUT1
IN2 0UT2

O 0UT2

INPUT CAPACITANCE (PF) FUNCTION T A B L E

Si^al L2ii IN1 IN2 OUT1 OUT2
INI .37 0 0 1 0
IN2 .36 0 1 0 1
1 0 0 1
1 1 0 1

LOGIC EQUATIONS

OUTl = INI + IN2

0UT2 = INI + IN2

SIZE
X:4Ox2S0
1.2^1: 24 X ISO
2.0^1: 32 X 200

Revision 2.0A CMOSN CcU Ubrary

8/29/89

56
 P - F L I P FLOP W/ ASY RESET
DFFR
LOGIC S Y M B O L
FUNCTIONAL DIAGRAM

DATA [ >

OOBAfl

INPUT CAPACITANCE (PF) FUNCTION TABLE

Sign?! 1.2u CLOCK DATA RESET QBAR
CLOCK .14
1 DATA DATA
DATA .20
RESET .30 1 QN-1 QBAR N-1
0 > 1

LOGIC EQUATIONS
QN = (QN-I • CLOCK + DATA • CLOCK) • RESET
QBARN = NOT [((2N.I . CLOCK + DATA • CLOCK) • RESET]

SIZE
X:80x2S0
1.2^: 48 X ISO
2.0^: 64 X 200

Note: Please refer to page 102 of recommendations in tying off the data input of this cell.

Revision 2.0A CMOSN CcU Ubrary

8/29/89

57
3-INPUT NAND/AND NDI3
LOGIC S Y M B O L FUNCTIONAL DIAGRAM
IN1 — I ^
IN2 — b — 0UT1
INS — I /^^— 0UT2

FTHRUI[:> - O FTHRUl
FEED-TWRU

INPUT CAPACITANCE (PF) FUNCTION T A B L E

Signal 1.2u IN1 IN2 IN3 0UT1 0UT2
INI .34 0 0 0 0
IN2 .3S 0 0 1 0
IN3 .36 0 1 0 0
FTHRUl .03 0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0 1

LOGIC EQUATIONS ^
OUTl = INI • IN2 • IN3
0UT2 = INI • IN2 • IN3

SIZE
X: 60 X 2S0
1.2^i:36xlS0
2.0vi: 48 X 200

Revision 2.0A CMOSN CeU Ubraiy

8/29/89

58
3:8 DECODER W/ ENABLE DEC4
LOGIC S Y M B O L FUNCTIONAL DIAGRAM

BMflLE

FEED-tVMJ

nvwus^- • FT>«US

INPUT C A P A C I T A N C E ( P F ) FUNCTION 'TABLE

1.2ii ENABLE 02 01 00 DO D1 02 09 04 05 06 07
Signal
0 0 0 0 1 0 0 0 0 0 0 0
CO .16 0 0 0 1 0 1 0 0 0 0 0 0
CI .16 0 0 1 0 0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0 0
C2 .17 0 1 0 0 0 0 0 0 1 0 0 0
ENABLE .16 0 1 0 1 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 0 0 0 1 0
FTHRUl .04 0 1 1 1 0 0 0 0 0 0 0 1
FTHRU2 .04 1 * * * 0 0 0 0 0 0 0 0
FTHRU3 .04
FTHRU4 .04
LOGIC E Q U A T I O N S
FTHRU5 .04
DO = ENABLE • CO• Cl • C2 D4= ENABLE-CO* CI • C2
Dl = ENABLE • CO • Cl • Q DS = ENABLE • CO • Cl • C2
D2 = ENABLE • CO • Cl • C2 D6 = ENABLE • CO • Cl • C2
D3 = ENABLE • CO • Cl • C2 D7 = ENABLE • (X • Cl • C2

SIZE
X: 280 X 2S0
12ji: 168 X ISO
2.0n: 224 x 200

CMOSN CeU Ubrary Revision 2.0A

138 8/29/89

59
4-BIT SHIFT REGISTER
SR4
LOGIC SYMBOL
INPUT CAPACITANCE ( P F )
2i£QaI L2u Signal L2u
SI .15 Dl .20
S2 .17 D2 .20
CLOCK .16 D3 .20
RESET .16 FTHRUl .03
DR .21 •••
DL .23 FTHRUl 1 .03
DO .20 •

FUNCTION T A B L E
CLOCK RESET 31 S2 DR D0-D3 DL OPERATION Q0-Q3
0 * RESET 0 0
1 0 0 * LOAD D0-D3 DO D3
1 0 1 * *
SHIFT RIGHT DR 02.
1 1 0 * * * SHIFT LEFT 0 1 N . I - DL
1 1 1 * * HOLD NO CHANGE

DESCRIPTION
SR4 is a 4 bit bi-directional shift register with parallel/sciial inputs arvd
parallel/serial outputs. It has four modes of operation: hold, shift left, shift
right, and parallel load. The mode is determined by the SI and S2 inputs.
RESET is asychronous. All outputs occur on the negative edge of CLOCK,

SlZE
X: 700x250
1.2n: 420x150
2.0ti: 560 X 200

CMOSN CeU Ubrary Revision 2.0A

8/29/89

60
4-BIT SHIFT REGISTER SR4
FUNCTIONAL DIAGRAM
DO Dl D2 D3 DL

LOAD LOAD
1 LOAD LOAD
I LOAD LOAD
1 LOAD
RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT RIGHT
DR CR Q CR Q CR Q
HOLD HOLD HOLD HOLD HOLD HOLD HOLD
DL Q DL 0 DL
RESET RESET RESET RESET RESET RESET RESET
CLOCK aocK aocK CLDGK CLOCK CLOCK CLOCK
LEFT LEFT LEFT LEFT LEFT LEFT LEFT
sncT SRBO SRBT SRBT

cmbb
—^5b
0 0 0
QO 01 02
{2
d CC FTHRUl O - -C^ FTHRUl
FEED-THRU
FTHRUl l D - -D^FTHRUII

Functional diagrams for SRCT, SRBO, SRBT, and SRBN appear on the
foUowing four pages.

Revision 2.0A CMOSN Cell Ubrary

8/29/89

61
4.BIT SHIFT REGISTER
SR4
FUNCTIONAL DIAGRAM
SRCT

DRO • O DR

S1 O

•O LOAD

. O RIGHT

<D> LEFT

-O HOLD

S2 O

OJOCKO
C ^ ^ - O CLOCK

RESET C >
D - ^ •O RESET

FTHRUI[:> •C> FTHRU1

FEED-THRU
FTHRU40- •C>FTVIRU4

SRCT

Shift Register control logic stage

CMOSN Cell Ubrary Revision 2.0A

8/29/89

62
4-BIT SHIFT REGISTER SR4
FUNCTIONAL DIAGRAM
SRBO

CR o ^ DL
LOAD o O LOAD
RIGKTO O RIGHT
LEFT O *—O LEFT
HOLD D> '—O HOLD
DATA O

O Q

RESET O C > RESET

aocK O OCLOCK
t ^ FTHRUl
FTHRUl O
OFTVIRU2
FTHRUZO
SRBO

Shift Register BitO stage

Stage - to - Stage Connections

BitO Bill
LOAD LOAD
RIGHT RIGHT
LEFT LEFT
HOLD HOLD
Q DR
DL Q
RESET RESET
CLOCK CLOCK
Revision 2.0A CMOSN CeU Ubrary
8/29/89

63
 4.BIT SHIFT REGISTER
SR4
FUNCTIONAL DIAGRAM
SRBN

DR o
LOAD O < a DL
RIGHT C >
LEFT O
HOLD O
DATA O

O Q

RESET C>
CLOCK O -
FTHRU10 O FTHRU1
FEED-THRU
SRBN

Shift Register 1 bit end stage

Revision 2.0A CMOSN CeU Ubrary

8/29/89

64
 APPENDIX B

SIMULATION OUTPUTS

65
TM1 :OUTO 1 1 1 1 1 i 1 1 L L

TM3 :OUTO 1 1 1 1 1 1 1 1 1 1

THi* :OUTO 1 1 1 1 1 1 1 1 1 1

TM5 :OUTO 1

Tri6 :OUTO 1 1 1 1 1 j 1 1 1 1
TM7 :OUTO 1

TM8 :OUTO 1 1 1 1 1 i 1 1 1 1
rn 1 1 - 1 ~\ 1

dp 1 1 1 • 1
da i 1 I . I 1 1

cab i 1 1 1

O.Ons 0.511)5 1.0P)S 1 .Sns 2.0ms

Time

Fig. B.l The output waveforms for the pop-machine problem (PSpice).

66
reg:CLK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
regiSI 1 I I I 1 1 I I 1
reg:SO I I I 1
reg:SL 1 1 I I
reg:A
reg:B 1 1
reg:C
reg:D 1 1
reg:Q()
reg:QB 1 1
reg:QC 1 1
reg:QD 1 1 1

I ' '
O.Oms O.Sns 1.0ms 1 .Sns 2.0
Time

Fig. B.2 Output waveforms of the register for the pop machine problem (PSpice).

67
reg:CLK 1 r
reg:S1
req:SO

req:SL
req:OB
req:QC

reg:QD

— I — I
0.0ns 0.5ms 1.0ns 1.5ms 2.0ns
Tine

Fig. B.3 The shift register serial input and output waveforms (PSpice).

68
regzCLK
regiSI
reg:SO
reg:B
reg:C
regiD
reg:QB
reg:QC
reg:QD

0.0ns 0.5ns 1.0ms 1.5ns 2.0

Time

Fig. B.4 The shift register parallel input and output waveforms (PSpice).

69
PLDocument: C:\SAI\P0PD.DOC TITLE PAGE Wed Sep 11 13:42:32 1996

FILE : C:\SAI\POPD
DATE : Wed Sep 11 13:42:32 1996

MODULES :

Document Generator 3.50

File Handler 3.3
Language Compiler 3.64
Architectural Optimizer 3.69
Device Lib Scan 3.92
Device Library 3.157
Device Partition 3.154
Device Fusemap

SWITCH VALUES :

(Value in parenthesis represents batch mode switch value)

PLCOMP PRODUCT TERM LIMIT : 1024

PLOPT PRODUCT TERM LIMIT : 1024
PLOPT REDUCTION : Espresso (1)
NODE GENERATION : Procedure Instantiation
Arithmetic and Relational Operators (1)

70
PLDocument: C:\SAI\P0PD.DOC EQUATIONS Wed Sep 11 13:42:32 1996

EQUATIONS FOR SYSTEM

INPUT SIGNALS (8):

NPL_0023
NPL_0024
NPL_0025
NPL_0003
NPL_0026
NPL_0004
NPL_0006
NPL_0007

OUTPUT SIGNALS (4):

outda
outdp
outca
outm

PHYSICAL NODE SIGNALS (3):

ls74.U16A.x
ls74.U17A.x
1S74.U18A.X

REDUCED EQUATIONS:

outda.EQN = ls74.U16A.x*/Is74.U17A.x*ls74.U18A.x; "(1 term, 3 symbols)

outdp.EQN = /Is74.U16A.x*ls74.U17A.x*Is74.U18A.x; "(1 tcnn, 3 symbols)

outca.EQN = ls74.U16A.x*ls74.U17A.x*ls74.U18A.x ; "(1 term, 3 symbols)

outm.EQN = /ls74.U16A.x*/ls74.U17A.x*Is74.U18A.x ; "(1 term, 3 symbols)

ls74.UI6A.x.D = NPL_0023*/ls74.U17A.x*ls74.U18A.x
+ NPL_0024*/ls74.U16A.x*ls74.U17A.x
+ NPL_0025*/ls74.Ui7A.x*/ls74.U18A.x
+ ls74.U16A.x*/ls74.U17A.x ; "(4 terms. 6 s>'mbols)
ls74.U16A.x.CLK = NPL_0006 ; "(1 term, 1 symbol)
ls74.U16A.x.RESET = /NPL_0007 ; "(1 term, 1 symbol)

ls74.U17A.x.D = NPL_0003*ls74.U17A.x*/ls74.U18A.x
+ NPL 0026*Is74.U16A.x*/ls74.U17A.x
+ ls74.U16A.x*/ls74.U17A.x*
ls74.U18A.x
+ /ls74.U16A.x*ls74.U17A.x ; "(4 terms, 5 symbols)
ls74.U17A.x.CLK = NPL_0006 ; "(1 term, 1 symbol)

71
ls74.U17A.x.RESET = /NPL_0007 ; "(1 term, I symbol)

ls74.U18A.x.D = NPL_0003*ls74.U17A.x*/ls74.U18A.x
+ NPL_0004*ls74.U17A.x*/ls74.U18A.x
+ /ls74.U16A.x*ls74.U18A.x ; "(3 terms, 5 symbols)
ls74.U18A.x.CLK = NPL_0006 ; "(1 term, 1 symbol)
ls74.U18A.x.RESET = /NPL 0007 ; "(1 term, 1 symbol)

72
PLDocument: C:\SAI\P0PD.DOC SOLUTIONS Wed Sep 1113:42:32 1996

PARTITIONING CRITERIA :

AVAILABLE 'plsynlib.avl';

WEIGHT PRICE 8 ;

WEIGHT SIZE 10 ;

MANUFACTURER = ALT OR AMD ;

PARTITIONING SOLUTIONS

Solution 1:P300
Solution 2: P22V10
Solution 3: P600
Solution 4: P20RA10
Solution 5: P29MA16
Solution 6: P29M16
Solution 7:P630
Solution 8: P26V12
SoluUon 9:P900
Solution 10: P1800

73
 PERMISSION TO COPY

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It is understood that any copying or publication of this thesis for financial gain
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