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  • (Rs1) (RD) (Rs2) : U11 Registerfile

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    Rajini Kasala
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    1. The document appears to describe the design of a register file and control logic for a 5-stage pipelined processor. 2. It shows the register file receiving read addresses and writing values back. It also shows control signals for reading, writing, and resetting the register file. 3. Additional logic is described for selecting the program counter value, performing ALU operations, controlling the PC, and handling memory access.

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    Original Title

    rv32i

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    1. The document appears to describe the design of a register file and control logic for a 5-stage pipelined processor. 2. It shows the register file receiving read addresses and writing values back. It also shows control signals for reading, writing, and resetting the register file. 3. Additional logic is described for selecting the program counter value, performing ALU operations, controlling the PC, and handling memory access.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    7 views1 page

    (Rs1) (RD) (Rs2) : U11 Registerfile

    Uploaded by

    Rajini Kasala
    1. The document appears to describe the design of a register file and control logic for a 5-stage pipelined processor. 2. It shows the register file receiving read addresses and writing values back. It also shows control signals for reading, writing, and resetting the register file. 3. Additional logic is described for selecting the program counter value, performing ALU operations, controlling the PC, and handling memory access.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 1

    1 2 3 4 5

    U11
    RegisterFile
    rd_clk 1 5 insn[19..15] (rs1)
    WR AA
    (rd) insn[24..20] 2 6 rs1_val[31..0]
    WA AD
    rd_val[31..0] 3 7 insn[24..20] (rs2)
    A WD BA A
    reset 4 8 rs2_val[31..0]
    Reset BD

    pc_alu_sel

    U12
    U16 U15

    A0
    4
    I1 U13 U14

    Q
    rd_sel[1]
    A1 A Q

    pc_alu[31..0]
    rd_sel[0] I0

    I1
    I0

    I0
    I1
    A0 alu_a_sel alu_b__sel
    Q + A0 A0

    I3
    I2
    I1
    I0

    Q
    B
    U18
    U17 PC
    pc_clk
    Cp
    I0 pc[31..0] U19
    Q Din Dout

    mem_sx[31..0]
    I1 reset ALU

    A0
    RESET

    B
    Func

    A<UB
    pc_next_sel sub/sra

    A<B
    EQ
    imm_x[4..0]

    Q
    shamt
    B B
    U20 Sheet: imm_sx
    sx

    imm_x[31..0]
    File: mbr_sx.sch

    INSN insn imm_x


    Sheet: mbr_sx

    insn_clk
    Cp File: imm_sx.sch
    insn[31..0]
    Din Dout
    reset
    size
    mbr

    RESET
    sx_size[2..0]

    alu[31..0]

    U21

    I1
    I0
    addr_sel Sheet: control_fsm
    A0 sub_sra
    sub_sra
    alu_func[2..0]

    Q
    func
    addr_sel
    addr_sel
    rd_sel[1..0]
    C A<UB rd_sel[1..0] C
    alu_a_sel
    mem_out[31..0]

    A<B alu_a_sel
    U22 alu_b_sel
    EQ alu_b_sel
    MEM insn[6..0] mem_clk
    addr[31..0] opcode mem_clk
    insn[14..12] rd_clk
    funct3 rd_clk
    ReadAddress insn[30] pc_clk
    sub_sra_in pc_clk
    WriteAddress insn_clk
    mem_clk ir_clk
    WE pc_alu_sel
    pc_alu_sel
    Dout Din pc_next_sel
    pc_next_sel
    rs2_val[31..0] sx_size[2..0]
    sx_size[2..0]
    CLK reset
    reset
    File: control.sch

    D D

    Sheet: /
    File: rv32i.sch
    Title: RV32I
    Size: A Date: 2021-10-04 Rev: 1.1
    KiCad E.D.A. kicad 5.1.5+dfsg1-2build2 Id: 1/4
    1 2 3 4 5

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