RV32I Control Timing Diagrams

pc clk
pc alu sel +4

pc alu 0x00000004 0x00000008 0x0000000c 0x00000010 0x00000014 0x00000018

pc next sel pc alu

pc 0x00000000 0x00000004 0x00000008 0x0000000c 0x00000010 0x00000014

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13

Figure 1: Program counter behavior.

00000000: 000087b7 lui x15,0x8 // x15 = 0x00008000

00000004: 12345117 auipc x2,0x12345 // x2 = 0x00000004 + 0x12345000 = 0x12345004
00000008: 00a10093 addi x1,x2,10 // x1 = 0x12345004 + 0x0000000a = 0x1234500e
0000000c: 4027da13 srai x20,x15,2 // x20 = 0x00008000 >> 2 = 0x00002000
00000010: 00f100b3 add x1,x2,x15 // x1 = 0x12345004 + 0x00008000 = 0x1234d004
00000014: 402a00b3 sub x1,x20,x2 // x1 = 0x00002000 - 0x12345004 = 0xedcbcffc

lui x15,0x8 auipc x2,0x12345 addi x1,x2,10 srai x20,x15,2 add x1,x2,x15 sub x1,x20,x2

CLK
insn[6..0] opcode = 0x37 opcode = 0x17 opcode = 0x13 opcode = 0x13 opcode = 0x33 opcode = 0x33

insn[14.12] funct3 = addi funct3 = srx funct3 = add/sub funct3 = add/sub

insn[30] funct7 = sra funct7 = add funct7 = sub

rd 15 2 1 20 1 1

pc clk
pc alu sel +4

pc alu 0x00000004 0x00000008 0x0000000c 0x00000010 0x00000014 0x00000018

pc next sel pc alu

pc 0x00000000 0x00000004 0x00000008 0x0000000c 0x00000010 0x00000014

insn clk
insn 0x000087b7 0x12345117 0x00a10093 0x4027da13 0x00f100b3 0x402a00b3

rs1 2 15 2 20

rs2 15 2

imm x 0x00008000 0x12345000 0x0000000a 0x00000002

addr sel pc

addr 0x00000000 0x00000004 0x00000008 0x0000000c 0x00000010 0x00000014

mem out 0x000087b7 0x12345117 0x00a10093 0x4027da13 0x00f100b3 0x402a00b3

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13

Figure 2: Fetch and decode cycles of U-type, R-type, and some I-type instructions.

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00000000: 000087b7 lui x15,0x8 // x15 = 0x00008000
00000004: 12345117 auipc x2,0x12345 // x2 = 0x00000004 + 0x12345000 = 0x12345004
00000008: 00a10093 addi x1,x2,10 // x1 = 0x12345004 + 0x0000000a = 0x1234500e
0000000c: 4027da13 srai x20,x15,2 // x20 = 0x00008000 >> 2 = 0x00002000
00000010: 00f100b3 add x1,x2,x15 // x1 = 0x12345004 + 0x00008000 = 0x1234d004
00000014: 402a00b3 sub x1,x20,x2 // x1 = 0x00002000 - 0x12345004 = 0xedcbcffc

lui x15,0x8 auipc x2,0x12345 addi x1,x2,10 srai x20,x15,2 add x1,x2,x15 sub x1,x20,x2

CLK
EQ
A<B
A<UB
insn[6..0] opcode = 0x37 opcode = 0x17 opcode = 0x13 opcode = 0x13 opcode = 0x33 opcode = 0x33

insn[14.12] funct3 = addi funct3 = srx funct3 = add/sub funct3 = add/sub

insn[30] funct7 = sra funct7 = add funct7 = sub

rd clk
rd sel 1 = alu 1 = alu 1 = alu 1 = alu 1 = alu 1 = alu

rd 15 2 1 20 1 1

rd val 0x00008000 0x12345004 0x12345008 0x1234500e 0x00002000 0x1234d004 0xedcbcffc

pc clk
pc alu sel +4

pc alu 0x00000004 0x00000008 0x0000000c 0x00000010 0x00000014 0x00000018

pc next sel pc alu

pc 0x00000000 0x00000004 0x00000008 0x0000000c 0x00000010 0x00000014

insn clk
insn 0x000087b7 0x12345117 0x00a10093 0x4027da13 0x00f100b3 0x402a00b3

rs1 2 15 2 20

rs1 val 0x12345004 0x00008000 0x12345004 0x00002000

rs2 15 2

rs2 val 0x00008000 0x12345004

alu a sel rs1 pc rs1

alu b sel rs2 imm x rs2

alu func Q=B Q=A+B Q=A+B Q=A>>shamt Q=A+B Q=A+B

sub sra add srl sub sra add srl sub sra

imm x 0x00008000 0x12345000 0x0000000a 0x00000002

alu 0x00008000 0x12345004 0x12345008 0x1234500e 0x00002000 0x1234d004 0xedcbcffc

mem clk
addr sel pc

addr 0x00000000 0x00000004 0x00000008 0x0000000c 0x00000010 0x00000014

mem out 0x000087b7 0x12345117 0x00a10093 0x4027da13 0x00f100b3 0x402a00b3

sx size[2..0]
mem sx
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13

Figure 3: Fetch, decode, and execute cycles of U-type, R-type, and some I-type instructions.

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00000018: 0027a423 sw x2,8(x15) // m32(0x00008000 + 0x00000008) = 0x12345004
0000001c: 0087a803 lw x16,8(x15) // x16 = sx(m32(0x00008000 + 0x00000008)) = 0x12345004
00000020: 008000ef jal x1,0x28 // x1 = 0x00000024, pc = 0x00000020 + 0x00000008 = 0x00000028

00000028: 03000267 jalr x4,48(x0) // x4 = 0x0000002c, pc = (0x00000030 + 0x00000000) & 0xfffffffe = 0x00000030

00000030: 02f00063 beq x0,x15,0x50 // pc += (0x00000000 == 0x00008000 ? 0x00000020 : 4) = 0x00000034

00000034: 03010063 beq x2,x16,0x54 // pc += (0x12345004 == 0x12345004 ? 0x00000020 : 4) = 0x00000054

sw x2,8(x15) lw x16,8(x15) jal x1,0x28 jalr x4,48(x0) beq x0,x15,0x50 beq x2,x16,0x54

CLK
EQ
A<B
A<UB
insn[6..0] opcode = 0x23 opcode = 0x03 opcode = 0x6f opcode = 0x67 opcode = 0x63 opcode = 0x63

insn[14.12] funct3 = sw funct3 = lw funct3 = 0 funct3 = beq funct3 = beq

insn[30]
rd clk
rd sel 1 = mem sx 3 = pc alu 3 = pc alu

rd 16 1 4

rd val 0x12345004 0x00000024 0x0000002c 0x0000002c 0x00000034

pc clk
pc alu sel +4 +imm x

pc alu 0x0000001c 0x00000020 0x00000024 0x0000002c 0x00000034 0x00000038 0x00000054

pc next sel pc alu alu pc alu

pc 0x00000018 0x0000001c 0x00000020 0x00000028 0x00000030 0x00000034 0x00000054

insn clk
insn 0x0027a423 0x0087a803 0x008000ef 0x03000267 0x02f00063 0x03010063

rs1 15 15 0 0 2

rs1 val 0x00008000 0x00008000 0x00000000 0x00000000 0x12345004

rs2 2 15 16

rs2 val 0x12345004 0x00008000 0x12345004

alu a sel rs1 pc rs1

alu b sel imm x rs2

alu func Q=A+B Q=A+B Q=A+B Q=A+B Q=A+B Q=A+B

sub sra add srl sub sra

imm x 0x00000008 0x00000008 0x00000008 0x00000030 0x00000020 0x00000020

alu 0x00008008 0x00008008 0x00000028 0x00000030 0x00000030 0xffff8000 0x00000000

mem clk
addr sel pc alu pc alu pc

addr 0x00000018 0x00008008 0x0000001c 0x00008008 0x00000020 0x00000028 0x00000030 0x00000034

mem out 0027a423 0087a803 0x12345004 0x008000ef 0x03000267 0x02f00063 0x03010063

sx size[2..0] 0

mem sx 0x12345004

t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13

Figure 4: Fetch, decode, and execute of load, store, jump, and branch instructions.

©
Copyright 2019, 2020 John Winans. All Rights Reserved
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jwinans@niu.edu 2020-10-21 17:36:56 -0500 v2.0-760-ga9a2e50